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The SPARC Architecture Manual

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The SPARC Architecture Manual The SPARC Architecture Manual Version 8 Revision SAV080SI9308 The SPARC Architecture Manual Version 8 Revision SAV080SI9308 SPARC International Inc. 535 Middlefield Road, Suite 210 Menlo Park, CA 94025 415-321-8692 SPARC International, Inc. SPARC® is a registered trademark of SPARC International, Inc. The SPARC logo is a registered trademark of SPARC International, Inc. UNIX® and OPEN LOOK® are registered trademarks of UNIX System Labora- tories, Inc. Copyright © 1991,1992 SPARC International, Inc. − Printed in U.S.A. All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, recording or otherwise, without the prior permission of the copyright owners. Restricted rights legend: use, duplication, or disclosure by the U.S. government is subject to restrictions set forth in subparagraph (c)(1)(ii) of the Rights in Technical Data and Computer Software clause at DFARS 52.227-7013 and in similar clauses in the FAR and NASA FAR Supplement. Contents Chapter 1 Introduction .......................................................................................................... 1 1.1. SPARC Attributes ........................................................................................................... 1 Design Goals ................................................................................................................... 1 Register Windows ........................................................................................................ 1 1.2. SPARC System Components .................................................................................... 2 Reference MMU ............................................................................................................ 2 Supervisor Software .................................................................................................... 2 Memory Model .............................................................................................................. 2 1.3. SPARC Compliance Definitions ............................................................................. 2 1.4. SPARC Features .............................................................................................................. 3 1.5. Conformability to SPARC ......................................................................................... 4 1.6. Fonts in Manual ................................................................................................................ 4 1.7. Notes ....................................................................................................................................... 5 1.8. Glossary ................................................................................................................................ 5 1.9. References ............................................................................................................................ 7 Chapter 2 Overview ................................................................................................................ 9 2.1. SPARC Processor ............................................................................................................ 9 Integer Unit (IU) ............................................................................................................ 9 Floating-point Unit (FPU) ....................................................................................... 10 Coprocessor (CP) .......................................................................................................... 10 2.2. Instructions .......................................................................................................................... 11 Load/Store ......................................................................................................................... 11 Alignment Restrictions ........................................................................................ 11 − v − Contents — Continued Addressing Conventions ..................................................................................... 11 Load/Store Alternate ............................................................................................. 11 Separate I&D Memories ...................................................................................... 12 Arithmetic/Logical/Shift .......................................................................................... 12 Control Transfer ............................................................................................................ 12 State Register Access ................................................................................................. 13 Floating-Point/Coprocessor Operate ................................................................. 13 2.3. Memory Model ................................................................................................................. 13 Input/Output ..................................................................................................................... 14 2.4. Traps ....................................................................................................................................... 14 Trap Categories .............................................................................................................. 14 Chapter 3 Data Formats ....................................................................................................... 17 Chapter 4 Registers ................................................................................................................. 23 4.1. IU r Registers ..................................................................................................................... 23 Windowed r Registers ................................................................................................ 24 Overlapping of Windows ......................................................................................... 24 Doubleword Operands ............................................................................................... 25 Special r Registers ........................................................................................................ 25 Register Usage ................................................................................................................ 25 4.2. IU Control/Status Registers ....................................................................................... 28 Processor State Register (PSR) ............................................................................. 28 PSR_implementation (impl) .............................................................................. 28 PSR_version (ver) ................................................................................................... 28 PSR_integer_cond_codes (icc) ........................................................................ 28 PSR_negative (n) ..................................................................................................... 28 PSR_zero (z) ............................................................................................................... 29 PSR_overflow (v) .................................................................................................... 29 PSR_carry (c) ............................................................................................................ 29 PSR_reserved ............................................................................................................. 29 PSR_enable_coprocessor (EC) ........................................................................ 29 PSR_enable_floating-point (EF) .................................................................... 29 − vi − Contents — Continued PSR_proc_interrupt_level (PIL) ..................................................................... 29 PSR_supervisor (S) ................................................................................................ 29 PSR_previous_supervisor (PS) ....................................................................... 29 PSR_enable_traps (ET) ........................................................................................ 29 PSR_current_window_pointer (CWP) ........................................................ 29 Window Invalid Mask Register (WIM) ........................................................... 30 Trap Base Register (TBR) ....................................................................................... 31 TBR_trap_base_address (TBA) ...................................................................... 31 TBR_trap_type (tt) ................................................................................................. 31 TBR_zero (0) ............................................................................................................. 31 Multiply/Divide Register (Y) ................................................................................. 32 Program Counters (PC, nPC) ................................................................................. 32 Ancillary State Registers (ASR) .......................................................................... 32 IU Deferred-Trap Queue ........................................................................................... 33 4.3. FPU f Registers ................................................................................................................. 33 Double
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