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(2) Buy an ASIC-Vendor Library from a Library Vendor (3) You Can Build Your Own Cell Library ASICs... the course Michael John Sebastian Smith This course is based on ASICs... the book Application-Specific Integrated Circuits Michael J. S. Smith VLSI Design Series 1,040 pages ISBN 0-201-50022-1 LOC TK7874.6.S63 Addison Wesley Longman, http://www.awl.com Additional material (figures, resources, source code) is located at ASICs... the website http://spectra.eng.hawaii.edu/~msmith/ASICs/HTML/ASICs.htm Some material in this work is reprinted from IEEE Std 1149.1-1990, “IEEE Standard Test Access Port and Boundary-Scan Archi- tecture,” Copyright © 1990; IEEE Std 1076/INT-1991 “IEEE Standards Interpretations: IEEE Std 1076-1987, IEEE Standard VHDL Language Reference Manual,” Copyright © 1991; IEEE Std 1076-1993 “IEEE Standard VHDL Language Reference Manual,” Copyright © 1993; IEEE Std 1164-1993 “IEEE Standard Multivalue Logic System for VHDL Model Interoperability (Std_logic_1164),” Copyright © 1993; IEEE Std 1149.1b-1994 “Supplement to IEEE Std 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture,” Copyright © 1994; IEEE Std 1076.4-1995 “IEEE Standard for VITAL Applica- tion-Specific Integerated Circuit (ASIC) Modeling Specification,” Copyright © 1995; IEEE 1364-1995 “IEEE Standard Descrip- tion Language Based on the Verilog® Hardware Description Language,” Copyright © 1995; and IEEE Std 1076.3-1997 “IEEE Standard for VHDL Synthesis Packages,” Copyright © 1997; by the Institute of Electrical and Electronics Engineers, Inc. The IEEE disclaims any responsibility or liability resulting from the placement and use in the described manner. Information is reprinted with the permission of the IEEE. Figures describing Xilinx FPGAs are courtesy of Xilinx, Inc. ©Xilinx, Inc. 1996, 1997, 1998. All rights reserved. Figures describing Altera CPLDs are courtesy of Altera Corporation. Altera is a trademark and service mark of Altera Corporation in the United States and other countries. Altera products are the intellectual property of Altera Corporation and are protected by copyright laws and one or more U.S. and foreign patents and patent applications. Figures describing Actel FPGAs iare courtesy of Actel Corporation. The programs and applications presented in this work have been included for their instructional value. They have been tested with care but are not guaranteed for any particular purpose. The author does not offer any warranties, representations, or accept any lia- bilities with respect to the programs or applications. Many of the designations used by manufacturers and sellers to distinguish their products are claimed as trademarks. Where those designations appear in this work, and the author was aware of a trademark claim, the designations have been printed in initial caps or all caps. Figures copyright © 1997 by Addison Wesley Longman, Inc. Text copyright © 1997, 1998 by Michael John Sebastian Smith. ASICs...THE COURSE (1 WEEK) INTRODUCTION 1 TO ASICs Key concepts: The difference between full-custom and semicustom ASICs • The difference between standard-cell, gate-array, and programmable ASICs • ASIC design flow • Design economics • ASIC cell library An ASIC (“a-sick”) is an application-specific integrated circuit A gate equivalent is a NAND gate F = A • B (IBM uses a NOR gate), or four transistors History of integration: small-scale integration (SSI, ~10 gates per chip, 60’s), medium- scale integration (MSI, ~100–1000 gates per chip, 70’s), large-scale integration (LSI, ~1000–10,000 gates per chip, 80’s), very large-scale integration (VLSI, ~10,000–100,000 gates per chip, 90’s), ultralarge scale integration (ULSI, ~1M–10M gates per chip) History of technology: bipolar technology and transistor–transistor logic (TTL) preceded metal-oxide-silicon (MOS) technology because it was difficult to make metal-gate n-chan- nel MOS (nMOS or NMOS); the introduction of complementary MOS (CMOS, never cMOS) greatly reduced power The feature size is the smallest shape you can make on a chip and is measured in l or lambda Origin of ASICs: the standard parts, initially used to design microelectronic systems, were gradually replaced with a combination of glue logic, custom ICs, dynamic random- access memory (DRAM) and static RAM (SRAM) History of ASICs: The IEEE Custom Integrated Circuits Conference (CICC) and IEEE Inter- national ASIC Conference document the development of ASICs Application-specific standard products (ASSPs) are a cross between standard parts and ASICs 1.1 Types of ASICs ICs are made on a wafer. Circuits are built up with successive mask layers. The number of masks used to define the interconnect and other layers is different between full-custom ICs and programmable ASICs 1 2 SECTION 1 INTRODUCTION TO ASICs ASICS... THE COURSE silicon die A silicon chip or integrated cicuit (IC) is more properly called a die 0.1 inch (a) (b) 1.1.1 Full-Custom ASICs All mask layers are customized in a full-custom ASIC. It only makes sense to design a full-custom IC if there are no libraries available. Full-custom offers the highest performance and lowest part cost (smallest die size) with the disadvantages of increased design time, complexity, design expense, and highest risk. Microprocessors were exclusively full-custom, but designers are increasingly turning to semicustom ASIC techniques in this area too. Other examples of full-custom ICs or ASICs are requirements for high-voltage (automobile), analog/digital (communications), or sensors and actuators. 1.1.2 Standard-Cell–Based ASICs A cell-based ASIC (CBIC—“sea-bick”) • Standard cells standard-cell 1 • Possibly megacells, megafunctions, full- area custom blocks, system-level macros (SLMs), 2 3 fixed blocks, cores, or Functional Standard Blocks (FSBs) fixed blocks • All mask layers are customized—transistors and interconnect 4 5 • Custom blocks can be embedded 0.02in • Manufacturing lead time is about eight weeks. 500 mm In datapath (DP) logic we may use a datapath compiler and a datapath library. Cells such as arithmetic and logical units (ALUs) are pitch-matchedto each other to improve timing and density. ASICs... THE COURSE 1.1 Types of ASICs 3 VDD m1 n-well cell bounding box (BB) contact ndiff pdiff Z A1 B1 via metal2 poly ndiff cell abutment box (AB) p-well pdiff pdiff GND 10l Looking down on the layout of a standard cell from a standard-cell library 1.1.3 Gate-Array–Based ASICs A gate array, masked gate array, MGA, or prediffused array uses macros (books) to reduce turnaround time and comprises a base array made from a base cell or primitive cell. There are three types: • Channeled gate arrays • Channelless gate arrays • Structured gate arrays 4 SECTION 1 INTRODUCTION TO ASICs ASICS... THE COURSE 1 expanded view of part of flexible no connection block 1 connection metal2 to power to power 250l pads metal1 pads terminal VSS VDD VSS VDD Z row-end cells feedthrough cell A.11 cell A.14 cell A.23 spacer cell A.132 metal2 cells I1 metal2 power cell metal1 metal1 rows of standard cells 50l Routing a CBIC (cell-based IC) • A “wall” of standard cells forms a flexible block • metal2 may be used in a feedthrough cell to cross over cell rows that use metal1 for wir- ing • Other wiring cells: spacer cells, row-end cells, and power cells A note on the use of hyphens and dashes in the spelling (orthography) of compound nouns: Be careful to distinguish between a “high-school girl” (a girl of high-school age) and a “high school girl” (is she on drugs or perhaps very tall?). We write “channeled gate array,” but “channeled gate-array architecture” because the gate array is channeled; it is not “channeled-gate array architecture” (which is an array of chan- neled-gates) or “channeled gate array architecture” (which is ambiguous). We write gate-array–based ASICs (with a en-dash between array and based) to mean (gate array)-based ASICs. ASICs... THE COURSE 1.1 Types of ASICs 5 1.1.4 Channeled Gate Array A channeled gate array base cell • Only the interconnect is customized • The interconnect uses predefined spaces between rows of base cells • Manufacturing lead time is between two days and two array of base cells weeks (not all shown) 1.1.5 Channelless Gate Array A channelless gate array (channel-free gate array, sea- base cell of-gates array, or SOG array) • Only some (the top few) mask layers are customized— the interconnect • Manufacturing lead time is between two days and two array of base cells weeks. (not all shown) 1.1.6 Structured Gate Array 6 SECTION 1 INTRODUCTION TO ASICs ASICS... THE COURSE An embedded gate array or structured gate embedded array (masterslice or masterimage) block • Only the interconnect is customized • Custom blocks (the same for each design) can be embedded array of • Manufacturing lead time is between two days base cells and two weeks. (not all shown) 1.1.7 Programmable Logic Devices Examples and types of PLDs: read-only memory (ROM) • programmable ROM or PROM • electrically programmable ROM, or EPROM • An erasable PLD (EPLD) • electrically eras- able PROM, or EEPROM • UV-erasable PROM, or UVPROM • mask-programmable ROM • A mask-programmed PLD usually uses bipolar technology Logic arrays may be either a Programmable Array Logic (PAL®, a registered trademark of AMD) or a programmable logic array (PLA); both have an AND plane and an OR plane A programmable logic device (PLD) • No customized mask layers or logic cells • Fast design turnaround macrocell • A single large block of programmable intercon- nect • A matrix of logic macrocells that usually consist of programmable array logic followed by a flip-flop or programmable latch interconnect ASICs... THE COURSE 1.2 Design Flow 7 1.1.8 Field-Programmable Gate Arrays A field-programmable gate array (FPGA) or complex PLD • None of the mask layers are customized programmable • A method for programming the basic logic basic logic cells and the interconnect cell • The core is a regular array of programmable basic logic cells that can implement combina- tional as well as sequential logic (flip-flops) • A matrix of programmable interconnect sur- rounds the basic logic cells programmable • Programmable I/O cells surround the core interconnect • Design turnaround is a few hours 1.2 Design Flow A design flow is a sequence of steps to design an ASIC 1.
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