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Field Programmable Gate Arrays with Hardwired Networks on Chip Field Programmable Gate Arrays with Hardwired Networks on Chip PROEFSCHRIFT ter verkrijging van de graad van doctor aan de Technische Universiteit Delft, op gezag van de Rector Magnificus prof. ir. K.C.A.M. Luyben, voorzitter van het College voor Promoties, in het openbaar te verdedigen op dinsdag 6 november 2012 om 15:00 uur door MUHAMMAD AQEEL WAHLAH Master of Science in Information Technology Pakistan Institute of Engineering and Applied Sciences (PIEAS) geboren te Lahore, Pakistan. Dit proefschrift is goedgekeurd door de promotor: Prof. dr. K.G.W. Goossens Copromotor: Dr. ir. J.S.S.M. Wong Samenstelling promotiecommissie: Rector Magnificus voorzitter Prof. dr. K.G.W. Goossens Technische Universiteit Eindhoven, promotor Dr. ir. J.S.S.M. Wong Technische Universiteit Delft, copromotor Prof. dr. S. Pillement Technical University of Nantes, France Prof. dr.-Ing. M. Hubner Ruhr-Universitat-Bochum, Germany Prof. dr. D. Stroobandt University of Gent, Belgium Prof. dr. K.L.M. Bertels Technische Universiteit Delft Prof. dr.ir. A.J. van der Veen Technische Universiteit Delft, reservelid ISBN: 978-94-6186-066-8 Keywords: Field Programmable Gate Arrays, Hardwired, Networks on Chip Copyright ⃝c 2012 Muhammad Aqeel Wahlah All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form or by any means, electronic, mechanical, photocopying, recording, or otherwise, without permission of the author. Printed in The Netherlands Acknowledgments oday when I look back, I find it a very interesting journey filled with different emotions, i.e., joy and frustration, hope and despair, and T laughter and sadness. At the same time, I feel that I am lucky enough to have some great people around, without whom the journey could not have been possible. I would like to express my gratitude to all of them as following. First of all I would like to convey my gratitude to Kees Goossens, my pro- moter and supervisor, for his erudite and invaluable supervision with sustained inspirations and incessant motivation. He guided me to explore the challenging research problems while giving me the complete flexibility, which provided the rationale to unleash my ingenuity and creativity along with an in-depth explo- ration of various research issues. Despite being a busy person, he still managed to extract time to provide me with his sufficient feedback. His encouragement and meticulous feedback wrapped in constructive criticism helped me to keep the impetus and to remain streamlined on the road of research that resulted in the triumphant completion of this work. I would also like to thank the PhD committee, i.e., Kees Goossens, Sebastien Pillment, Dirk Stroobandt, Michael Hubner, Koen Bertels, and Stephan Wong for investing their precious time to read the thesis and providing me with their valuable feedback. I am grateful to Higher Education Commission (HEC) Pakistan for financially supporting my research work during the initial four years of my PhD that en- abled me to work and do research in the Computer engineering department of Technical University of Delft, one of the leading universities in the world. I would like to pay my thanks to all of the colleagues from the Computer engineering department for their discussions and feedback. In particular, I want to thank Dr. Jae Young Hur for the many discussions, motivational talks and valuable guidance during my first two years of PhD. I also want to extend my thanks to Dr. Chunyang Guo for being such a nice friend and office mate in all those PhD years. Furthermore, I want to acknowledge the support of our chair secretary Lidwina Tromp, and administrators Erik de Vries and Eef Hartman to provide a good working environment. I would like to pay my deepest gratitude to my parents (Muhammad Siddique Wahlah and Razia Sultana) and my siblings (Anwar-us-Saeed, Riffat Shahid, Tasneem Khalid, Muhammad Shafique, Naseem Atif), and my in-laws (Razia 3 Naveed, Afzal Naveed, and Saba Naveed) for their never-ending support, sin- cere prayers, and encouragement throughout my Ph.D studies. In particular, I am thankful and pay salute to my parents (Muhammad Siddique Wahlah and Razia Sultana) for their unconditional love and exceptional sacrifice. I always found them standing beside me whenever I needed them. I must say that I can not thank enough to Almighty Allah, Who gave me such great parents. Finally, I get to the persons who I owe the most for the completion of this journey. My wife Tahira Aqeel, who always stood beside me through this long journey. I must say that she endures all the efforts that were put in to produce the thesis. I would not have reached this point without her loving and caring support, and I want to take this opportunity to thank her from the core of my heart. I also want to present bundle of thanks and love to my little three years old princess Ayesha Aqeel, whose smile and little acts always freshens up my mind and brightens up my days. More so often she makes me feel how beautiful life could have been, and how much blessed a person I am. I dedicate this thesis to all of my family members, and my advisor Prof. Kees Goossens. 4 Field Programmable Gate Arrays with Hardwired Networks on Chip Muhammad Aqeel Wahlah Abstract echnology down-scaling and platform-based designs have enforced a number of application and architecture trends for system-on-chip T (SOC) designs. A modern SOC is now a multi-functional machine that can execute a large number of complex applications by using tens or even hundreds of intellectual properties (IPs). Meanwhile, due to a number of constraints, e.g., short time to market, fickle market demands, and high non-recurring engineering (NRE) costs to name a few, Field Programmable Gate Arrays (FPGAs) have gained popularity to implement SOC designs. The applications in an SOC can be dynamically started and stopped thus forming multiple use-cases. The applications can also have diverse Quality-of-Service (QoS) constraints ranging from non real-time to soft, firm, and hard real-time constraints. At the same time the IP cores in an SOC are heterogenous in nature and run at diverse clock frequencies. The IPs can be microprocessors, DSP slices, memories, and ALU units, etc. The increasing number and diversity of applications and IPs require a powerful onchip communication architecture for quick integration and appropriate QoS. In contemporary FPGAs the onchip interconnect would be soft, i.e., programmed in the configurable fabric. The above-mentioned application and architecture trends have triggered a se- ries of problems. (1) An increasing number of applications on an FPGA often requires dynamic reconfiguration of an application, which in turn can produce interference with other running applications. (2) The increasing complexity of an application may mean that it can not be mapped entirely on the FPGA, which in turn can encounter loss of state of data during intra-application dy- namic partial reconfiguration. (3) The diverse natures of applications make it difficult to fulfill the Quality-of-Service constraints of an application. (4) Sim- ilarly, it is hard to achieve (physical) timing closure in an SOC, because of the i increasing number and diversity of the IP cores. (5) The technology down- scaling leads to FPGA architectures that are more prone to faults, e.g., config- uration memories and logic elements in an FPGA can be stuck at a particular value. (6) Because communication architecture and IPs are both mapped as soft IPs in the same logic plane of the FPGA, their placement has many re- strictions to allow for dynamic partial reconfiguration. In this thesis, we aim to address the above-mentioned problems by proposing the architecture and design flow of a new FPGA. As the main contribution of the thesis, we propose the FPGA architecture with a hardwired network on chip (HWNoC), and multiple test, configuration, and functional regions (TCFRs). We call it hardwired, because the NoC in an FPGA is built in sil- icon and not by using the reconfigurable elements. By having a HWNOC we can have a globally asynchronous locally synchronous (GALS) environ- ment, which in turn ensures that data is not lost during inter-IP communi- cation. The HWNOC separates the communication and computation in two disjoint planes, which alleviates restrictions on the placement of IPs. As the second contribution of the thesis, we show how we can use the HWNOC to transport unified test, configuration, and functional data to TCFRs, for testing, faster configuration, and interference-free communication during execution of applications. As the third contribution of the thesis, we demonstrate that how the proposed design flow ensures predictable application behavior by fulfill- ing the QoS constraints. We also present a 3-tier reconfiguration model that uses the HWNOC, which ensures contention-free communication at archi- tecture level, to overcome the problems of interference and state-loss during inter-application and intra-application reconfiguration respectively. Another contribution of the thesis is that it proposes a non-intrusive test methodology that uses the HWNOC as a test access mechanism to test the presence of faults reliability of FPGA architecture. In other words, the proposed methodology makes sure that applications are always reconfigured and executed on a reliable region of an FPGA, and without effecting the other running applications. ii Table of contents Acknowledgments ............................ 3 Abstract .................................. i List of Tables ............................... ix List of Figures .............................. xi List of Algorithms ............................ xvii 1 Introduction ............................. 1 1.1 Trends . 2 1.1.1 Application Point of View . 2 1.1.2 Architecture Point of View . 6 1.1.3 Summary . 11 1.2 Problems . 12 1.2.1 Application Point of View .
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