Field Programmable Gate Arrays with Hardwired Networks on Chip
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RTEMS CPU Supplement Documentation Release 4.11.3 ©Copyright 2016, RTEMS Project (Built 15Th February 2018)
RTEMS CPU Supplement Documentation Release 4.11.3 ©Copyright 2016, RTEMS Project (built 15th February 2018) CONTENTS I RTEMS CPU Architecture Supplement1 1 Preface 5 2 Port Specific Information7 2.1 CPU Model Dependent Features...........................8 2.1.1 CPU Model Name...............................8 2.1.2 Floating Point Unit..............................8 2.2 Multilibs........................................9 2.3 Calling Conventions.................................. 10 2.3.1 Calling Mechanism.............................. 10 2.3.2 Register Usage................................. 10 2.3.3 Parameter Passing............................... 10 2.3.4 User-Provided Routines............................ 10 2.4 Memory Model..................................... 11 2.4.1 Flat Memory Model.............................. 11 2.5 Interrupt Processing.................................. 12 2.5.1 Vectoring of an Interrupt Handler...................... 12 2.5.2 Interrupt Levels................................ 12 2.5.3 Disabling of Interrupts by RTEMS...................... 12 2.6 Default Fatal Error Processing............................. 14 2.7 Symmetric Multiprocessing.............................. 15 2.8 Thread-Local Storage................................. 16 2.9 CPU counter...................................... 17 2.10 Interrupt Profiling................................... 18 2.11 Board Support Packages................................ 19 2.11.1 System Reset................................. 19 3 ARM Specific Information 21 3.1 CPU Model Dependent Features.......................... -
NASDAQ Stock Market
Nasdaq Stock Market Friday, December 28, 2018 Name Symbol Close 1st Constitution Bancorp FCCY 19.75 1st Source SRCE 40.25 2U TWOU 48.31 21st Century Fox Cl A FOXA 47.97 21st Century Fox Cl B FOX 47.62 21Vianet Group ADR VNET 8.63 51job ADR JOBS 61.7 111 ADR YI 6.05 360 Finance ADR QFIN 15.74 1347 Property Insurance Holdings PIH 4.05 1-800-FLOWERS.COM Cl A FLWS 11.92 AAON AAON 34.85 Abiomed ABMD 318.17 Acacia Communications ACIA 37.69 Acacia Research - Acacia ACTG 3 Technologies Acadia Healthcare ACHC 25.56 ACADIA Pharmaceuticals ACAD 15.65 Acceleron Pharma XLRN 44.13 Access National ANCX 21.31 Accuray ARAY 3.45 AcelRx Pharmaceuticals ACRX 2.34 Aceto ACET 0.82 Achaogen AKAO 1.31 Achillion Pharmaceuticals ACHN 1.48 AC Immune ACIU 9.78 ACI Worldwide ACIW 27.25 Aclaris Therapeutics ACRS 7.31 ACM Research Cl A ACMR 10.47 Acorda Therapeutics ACOR 14.98 Activision Blizzard ATVI 46.8 Adamas Pharmaceuticals ADMS 8.45 Adaptimmune Therapeutics ADR ADAP 5.15 Addus HomeCare ADUS 67.27 ADDvantage Technologies Group AEY 1.43 Adobe ADBE 223.13 Adtran ADTN 10.82 Aduro Biotech ADRO 2.65 Advanced Emissions Solutions ADES 10.07 Advanced Energy Industries AEIS 42.71 Advanced Micro Devices AMD 17.82 Advaxis ADXS 0.19 Adverum Biotechnologies ADVM 3.2 Aegion AEGN 16.24 Aeglea BioTherapeutics AGLE 7.67 Aemetis AMTX 0.57 Aerie Pharmaceuticals AERI 35.52 AeroVironment AVAV 67.57 Aevi Genomic Medicine GNMX 0.67 Affimed AFMD 3.11 Agile Therapeutics AGRX 0.61 Agilysys AGYS 14.59 Agios Pharmaceuticals AGIO 45.3 AGNC Investment AGNC 17.73 AgroFresh Solutions AGFS 3.85 -
IBIS Open Forum Minutes
IBIS Open Forum Minutes Meeting Date: March 12, 2010 Meeting Location: Teleconference VOTING MEMBERS AND 2010 PARTICIPANTS Actel (Prabhu Mohan) Agilent Radek Biernacki, Ming Yan, Fangyi Rao AMD Nam Nguyen Ansoft Corporation (Steve Pytel) Apple Computer (Matt Herndon) Applied Simulation Technology (Fred Balistreri) ARM (Nirav Patel) Cadence Design Systems Terry Jernberg*, Wenliang Dai, Ambrish Varma Cisco Systems Syed Huq*, Mike LaBonte*, Tony Penaloza, Huyen Pham, Bill Chen, Ravindra Gali, Zhiping Yang Ericsson Anders Ekholm*, Pete Tomaszewski Freescale Jon Burnett, Om Mandhana Green Streak Programs Lynne Green Hitachi ULSI Systems (Kazuyoshi Shoji) Huawei Technologies (Jinjun Li) IBM Adge Hawes* Infineon Technologies AG (Christian Sporrer) Intel Corporation (Michael Mirmak), Myoung (Joon) Choi, Vishram Pandit, Richard Mellitz IO Methodology Lance Wang* LSI Brian Burdick* Mentor Graphics Arpad Muranyi*, Neil Fernandes, Zhen Mu Micron Technology Randy Wolff* Nokia Siemens Networks GmbH Eckhard Lenski* Samtec (Corey Kimble) Signal Integrity Software Walter Katz*, Mike Steinberger, Todd Westerhoff, Barry Katz Sigrity Brad Brim, Kumar Keshavan Synopsys Ted Mido Teraspeed Consulting Group Bob Ross*, Tom Dagostino Toshiba (Yasumasa Kondo) Xilinx Mike Jenkins ZTE (Huang Min) Zuken Michael Schaeder OTHER PARTICIPANTS IN 2010 AET, Inc. Mikio Kiyono Altera John Oh, Hui Fu Avago Razi Kaw Broadcom Mohammad Ali Curtiss-Wright John Phillips ECL, Inc. Tom Iddings eSilicon Hanza Rahmai Exar Corp. Helen Nguyen Mindspeed Bobby Altaf National Semiconductor Hsinho Wu* NetLogic Microsystems Eric Hsu, Edward Wu Renesas Technology Takuji Komeda Simberian Yuriy Shlepnev Span Systems Corporation Vidya (Viddy) Amirapu Summit Computer Systems Bob Davis Tabula David Banas* TechAmerica (Chris Denham) Texas Instruments Bonnie Baker Independent AbdulRahman (Abbey) Rafiq, Robert Badal In the list above, attendees at the meeting are indicated by *. -
IT Acronyms.Docx
List of computing and IT abbreviations /.—Slashdot 1GL—First-Generation Programming Language 1NF—First Normal Form 10B2—10BASE-2 10B5—10BASE-5 10B-F—10BASE-F 10B-FB—10BASE-FB 10B-FL—10BASE-FL 10B-FP—10BASE-FP 10B-T—10BASE-T 100B-FX—100BASE-FX 100B-T—100BASE-T 100B-TX—100BASE-TX 100BVG—100BASE-VG 286—Intel 80286 processor 2B1Q—2 Binary 1 Quaternary 2GL—Second-Generation Programming Language 2NF—Second Normal Form 3GL—Third-Generation Programming Language 3NF—Third Normal Form 386—Intel 80386 processor 1 486—Intel 80486 processor 4B5BLF—4 Byte 5 Byte Local Fiber 4GL—Fourth-Generation Programming Language 4NF—Fourth Normal Form 5GL—Fifth-Generation Programming Language 5NF—Fifth Normal Form 6NF—Sixth Normal Form 8B10BLF—8 Byte 10 Byte Local Fiber A AAT—Average Access Time AA—Anti-Aliasing AAA—Authentication Authorization, Accounting AABB—Axis Aligned Bounding Box AAC—Advanced Audio Coding AAL—ATM Adaptation Layer AALC—ATM Adaptation Layer Connection AARP—AppleTalk Address Resolution Protocol ABCL—Actor-Based Concurrent Language ABI—Application Binary Interface ABM—Asynchronous Balanced Mode ABR—Area Border Router ABR—Auto Baud-Rate detection ABR—Available Bitrate 2 ABR—Average Bitrate AC—Acoustic Coupler AC—Alternating Current ACD—Automatic Call Distributor ACE—Advanced Computing Environment ACF NCP—Advanced Communications Function—Network Control Program ACID—Atomicity Consistency Isolation Durability ACK—ACKnowledgement ACK—Amsterdam Compiler Kit ACL—Access Control List ACL—Active Current -
The Cortex-M Series: Hardware and Software
The Cortex-M Chapter Series: Hardware 2 and Software Introduction In this chapter the real-time DSP platform of primary focus for the course, the Cortex M4, will be introduced and explained. in terms of hardware, software, and development environments. Beginning topics include: • ARM Architectures and Processors – What is ARM Architecture – ARM Processor Families – ARM Cortex-M Series – Cortex-M4 Processor – ARM Processor vs. ARM Architectures • ARM Cortex-M4 Processor – Cortex-M4 Processor Overview – Cortex-M4 Block Diagram – Cortex-M4 Registers ECE 5655/4655 Real-Time DSP 2–1 Chapter 2 • The Cortex-M Series: Hardware and Software What is ARM Architecture • ARM architecture is a family of RISC-based processor archi- tectures – Well-known for its power efficiency; – Hence widely used in mobile devices, such as smart phones and tablets – Designed and licensed to a wide eco-system by ARM • ARM Holdings – The company designs ARM-based processors; – Does not manufacture, but licenses designs to semiconduc- tor partners who add their own Intellectual Property (IP) on top of ARM’s IP, fabricate and sell to customers; – Also offer other IP apart from processors, such as physical IPs, interconnect IPs, graphics cores, and development tools 2–2 ECE 5655/4655 Real-Time DSP ARM Processor Families ARM Processor Families • Cortex-A series (Application) Cortex-A57 Cortex-A53 – High performance processors Cortex-A15 Cortex-A9 Cortex-A Cortex-A8 capable of full Operating Sys- Cortex-A7 Cortex-A5 tem (OS) support; Cortex-R7 Cortex-R5 Cortex-R – Applications include smart- Cortex-R4 Cortex-M4 New!: Cortex-M7, Cortex-M33 phones, digital TV, smart Cortex-M3 Cortex-M1 Cortex-M Cortex-M0+ books, home gateways etc. -
Accelerated V2X Provisioning with Extensible Processor Platform
Accelerated V2X provisioning with Extensible Processor Platform Henrique S. Ogawa1, Thomas E. Luther1, Jefferson E. Ricardini1, Helmiton Cunha1, Marcos Simplicio Jr.2, Diego F. Aranha3, Ruud Derwig4 and Harsh Kupwade-Patil1 1 America R&D Center (ARC), LG Electronics US Inc. {henrique1.ogawa,thomas.luther,jefferson1.ricardini,helmiton1.cunha}@lge.com [email protected] 2 University of Sao Paulo, Brazil [email protected] 3 Aarhus University, Denmark [email protected] 4 Synopsys Inc., Netherlands [email protected] Abstract. With the burgeoning Vehicle-to-Everything (V2X) communication, security and privacy concerns are paramount. Such concerns are usually mitigated by combining cryptographic mechanisms with a suitable key management architecture. However, cryptographic operations may be quite resource-intensive, placing a considerable burden on the vehicle’s V2X computing unit. To assuage this issue, it is reasonable to use hardware acceleration for common cryptographic primitives, such as block ciphers, digital signature schemes, and key exchange protocols. In this scenario, custom extension instructions can be a plausible option, since they achieve fine-tuned hardware acceleration with a low to moderate logic overhead, while also reducing code size. In this article, we apply this method along with dual-data memory banks for the hardware acceleration of the PRESENT block cipher, as well as for the F2255−19 finite field arithmetic employed in cryptographic primitives based on Curve25519 (e.g., EdDSA and X25519). As a result, when compared with a state-of-the-art software-optimized implementation, the performance of PRESENT is improved by a factor of 17 to 34 and code size is reduced by 70%, with only a 4.37% increase in FPGA logic overhead. -
Efpgas : Architectural Explorations, System Integration & a Visionary Industrial Survey of Programmable Technologies Syed Zahid Ahmed
eFPGAs : Architectural Explorations, System Integration & a Visionary Industrial Survey of Programmable Technologies Syed Zahid Ahmed To cite this version: Syed Zahid Ahmed. eFPGAs : Architectural Explorations, System Integration & a Visionary Indus- trial Survey of Programmable Technologies. Micro and nanotechnologies/Microelectronics. Université Montpellier II - Sciences et Techniques du Languedoc, 2011. English. tel-00624418 HAL Id: tel-00624418 https://tel.archives-ouvertes.fr/tel-00624418 Submitted on 16 Sep 2011 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. Université Montpellier 2 (UM2) École Doctorale I2S LIRMM (Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier) Domain: Microelectronics PhD thesis report for partial fulfillment of requirements of Doctorate degree of UM2 Thesis conducted in French Industrial PhD (CIFRE) framework between: Menta & LIRMM lab (Dec.2007 – Feb. 2011) in Montpellier, FRANCE “eFPGAs: Architectural Explorations, System Integration & a Visionary Industrial Survey of Programmable Technologies” eFPGAs: Explorations architecturales, integration système, et une enquête visionnaire industriel des technologies programmable by Syed Zahid AHMED Presented and defended publically on: 22 June 2011 Jury: Mr. Guy GOGNIAT Prof. at STICC/UBS (Lorient, FRANCE) President Mr. Habib MEHREZ Prof. at LIP6/UPMC (Paris, FRANCE) Reviewer Mr. -
The Past and Future of FPGA Soft Processors
The Past and Future of FPGA Soft Processors Jan Gray Gray Research LLC [email protected] ReConFig 2014 Keynote 9 Dec 2014 Copyright © 2014, Gray Research LLC. Licensed under Creative Commons Attribution 4.0 International (CC BY 4.0) license. http://creativecommons.org/licenses/by/4.0/ In Celebration of Soft Processors • Looking back • Interlude: “old school” soft processor, revisited • Looking ahead 9 Dec 2014 ReConFig 2014 2 New Engines Bring New Design Eras 9 Dec 2014 ReConFig 2014 3 1. EARLY DAYS 9 Dec 2014 ReConFig 2014 4 1985-1990: Prehistory • XC2000, XC3000: not quite up to the job – Early multi-FPGA coprocessors – ~8-bit MISCs 9 Dec 2014 ReConFig 2014 5 1991: XC4000 9 Dec 2014 ReConFig 2014 6 1991: RISC4005 [P. Freidin] • The first monolithic general purpose FPGA CPU • “FPGA Devices: 1 Xilinx XC4005 ... On-board RAM: 64K Words (16 bit words) Notes: A 16 bit RISC processor that requires 75% of an XC4005, 16 general registers, 4 stage pipeline, 20 MHz. Can be integrated with peripherals on 1 FPGA, and ISET can be extended. … Includes a macro assembler, gate level simulator, ANSI C compiler, and a debug monitor.” [Steve Guccione: List of FPGA-based Computing Machines, http://www.cmpware.com/io.com/guccione/HW_list.html] Freidin Photos: Photos: Philip 9 Dec 2014 ReConFig 2014 7 1994-95: Gathering Steam • Communities: FCCM, comp.arch.fpga [http://fpga-faq.org/archives/index.html] • Research, commercial interest – OneChip, V6502 9 Dec 2014 ReConFig 2014 8 1995: J32 • 32-bit RISC + “SoC” • Integer only • 33 MHz ÷ 2φ • 4-stage pipeline • -
Embedded Design Handbook
Embedded Design Handbook Subscribe EDH | 2020.07.22 Send Feedback Latest document on the web: PDF | HTML Contents Contents 1. Introduction................................................................................................................... 6 1.1. Document Revision History for Embedded Design Handbook........................................ 6 2. First Time Designer's Guide............................................................................................ 8 2.1. FPGAs and Soft-Core Processors.............................................................................. 8 2.2. Embedded System Design...................................................................................... 9 2.3. Embedded Design Resources................................................................................. 11 2.3.1. Intel Embedded Support........................................................................... 11 2.3.2. Intel Embedded Training........................................................................... 11 2.3.3. Intel Embedded Documentation................................................................. 12 2.3.4. Third Party Intellectual Property.................................................................12 2.4. Intel Embedded Glossary...................................................................................... 13 2.5. First Time Designer's Guide Revision History............................................................14 3. Hardware System Design with Intel Quartus Prime and Platform Designer................. -
Architecture Exploration of FPGA Based Accelerators for Bioinformatics Applications Springer Series in Advanced Microelectronics
Springer Series in Advanced Microelectronics 55 B. Sharat Chandra Varma Kolin Paul M. Balakrishnan Architecture Exploration of FPGA Based Accelerators for BioInformatics Applications Springer Series in Advanced Microelectronics Volume 55 Series editors Kukjin Chun, Seoul, Korea, Republic of (South Korea) Kiyoo Itoh, Tokyo, Japan Thomas H. Lee, Stanford, CA, USA Rino Micheloni, Vimercate (MB), Italy Takayasu Sakurai, Tokyo, Japan Willy M.C. Sansen, Leuven, Belgium Doris Schmitt-Landsiedel, München, Germany The Springer Series in Advanced Microelectronics provides systematic information on all the topics relevant for the design, processing, and manufacturing of microelectronic devices. The books, each prepared by leading researchers or engineers in their fields, cover the basic and advanced aspects of topics such as wafer processing, materials, device design, device technologies, circuit design, VLSI implementation, and subsystem technology. The series forms a bridge between physics and engineering and the volumes will appeal to practicing engineers as well as research scientists. More information about this series at http://www.springer.com/series/4076 B. Sharat Chandra Varma Kolin Paul • M. Balakrishnan Architecture Exploration of FPGA Based Accelerators for BioInformatics Applications 123 B. Sharat Chandra Varma M. Balakrishnan Department of Electrical and Electronic Department of Computer Science Engineering and Engineering The University of Hong Kong Indian Institute of Technology Delhi Hong Kong New Delhi, Delhi Hong Kong India Kolin Paul Department of Computer Science and Engineering Indian Institute of Technology Delhi New Delhi, Delhi India ISSN 1437-0387 ISSN 2197-6643 (electronic) Springer Series in Advanced Microelectronics ISBN 978-981-10-0589-3 ISBN 978-981-10-0591-6 (eBook) DOI 10.1007/978-981-10-0591-6 Library of Congress Control Number: 2016931344 © Springer Science+Business Media Singapore 2016 This work is subject to copyright. -
Profiling Nios II Systems
Profiling Nios II Systems AN-391-3.0 Application Note This application note describes the methods to measure the performance of a Nios® II system with the GNU profiler (nios2-elf-gprof), the performance counter component, and the timestamp interval timer component. This application note also includes two tutorials to measure performance in the Altera® Nios II Software Build Tools (SBT) development flow. Requirements You must be familiar with the Nios II SBT development flow for Nios II systems, including the Quartus® II software and Qsys to use the tutorials. Obtaining the Hardware Design The tutorials in this application note work with the Nios II Ethernet Standard Design Example. To use the design example, unzip the .zip for your development kit to a working directory on your system. 1 This application note refers the software example directory as <project_directory>. Obtaining the Software Examples To obtain the software examples for this application note, follow these steps: 1. Download the profiler_software_examples.zip. 2. Unzip the profiler_software_examples.zip to <project_directory> in your system. 1 This application note refers the directory as <profiler_software_examples>. © 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off. and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in 101 Innovation Drive accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. -
Run-Time Dynamically-Adaptable FPGA-Based Architecture for High-Performance Autonomous Distributed Systems
Departamento de Automática, Ingeniería Eléctrica y Electrónica e Informática Industrial Escuela Técnica Superior de Ingenieros Industriales Run-Time Dynamically-Adaptable FPGA-Based Architecture for High-Performance Autonomous Distributed Systems Autor: Juan Valverde Alcalá Ingeniero Industrial por la Universidad Politécnica de Madrid Directores: Jorge Portilla Berrueco Doctor por la Universidad Politécnica de Madrid en Ingeniería Electrónica Eduardo de la Torre Arnanz Doctor Ingeniero Industrial por la Universidad Politécnica de Madrid 2015 Tribunal Tribunal nombrado por el Excmo. y Magfco. Sr. Rector de la Universidad Politécnica de Madrid, el día 6 de Noviembre de 2015. Presidente: Carlos López Barrio, Universidad Politécnica de Madrid Vocales: Roberto Sarmiento Rodríguez, Universidad de Las Palmas de Gran Canaria Christian De Schryver, Universidad Kaiserslautern Secretario: Teresa Riesgo Alcaide, Universidad Politécnica de Madrid Suplentes: Marta Portela García, Universidad Carlos III de Madrid Ángel de Castro Martín, Universidad Autónoma de Madrid Realizado el acto de lectura y defensa de la Tesis Doctoral el día 16 de Diciembre de 2015 en la Escuela Técnica Superior de Ingenieros Industriales de la Universidad Politécnica de Madrid. Calificación: EL PRESIDENTE LOS VOCALES EL SECRETARIO Посвета Ова докторска теза је посвећена мом животном партнеру. Зато што само са њом уживам у сваком тренутку свог живота. Зато што ме она учи како да будем снажан без обзира шта се деси. Зато што, кад сам са њом, знам да је све савршено и да сам спокојан. Зато што смо победили време и раздаљину и сада можемо да радимо шта год пожелимо. Agradecimientos A mis padres, mi hermana y Estefa, por traerme hasta aquí día tras día viéndome sufrir y trabajar, y diciéndome, “venga, otro pasito más”.