The Economics of Technology Working Paper Number 9
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Field Programmable Gate Arrays with Hardwired Networks on Chip
Field Programmable Gate Arrays with Hardwired Networks on Chip PROEFSCHRIFT ter verkrijging van de graad van doctor aan de Technische Universiteit Delft, op gezag van de Rector Magnificus prof. ir. K.C.A.M. Luyben, voorzitter van het College voor Promoties, in het openbaar te verdedigen op dinsdag 6 november 2012 om 15:00 uur door MUHAMMAD AQEEL WAHLAH Master of Science in Information Technology Pakistan Institute of Engineering and Applied Sciences (PIEAS) geboren te Lahore, Pakistan. Dit proefschrift is goedgekeurd door de promotor: Prof. dr. K.G.W. Goossens Copromotor: Dr. ir. J.S.S.M. Wong Samenstelling promotiecommissie: Rector Magnificus voorzitter Prof. dr. K.G.W. Goossens Technische Universiteit Eindhoven, promotor Dr. ir. J.S.S.M. Wong Technische Universiteit Delft, copromotor Prof. dr. S. Pillement Technical University of Nantes, France Prof. dr.-Ing. M. Hubner Ruhr-Universitat-Bochum, Germany Prof. dr. D. Stroobandt University of Gent, Belgium Prof. dr. K.L.M. Bertels Technische Universiteit Delft Prof. dr.ir. A.J. van der Veen Technische Universiteit Delft, reservelid ISBN: 978-94-6186-066-8 Keywords: Field Programmable Gate Arrays, Hardwired, Networks on Chip Copyright ⃝c 2012 Muhammad Aqeel Wahlah All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form or by any means, electronic, mechanical, photocopying, recording, or otherwise, without permission of the author. Printed in The Netherlands Acknowledgments oday when I look back, I find it a very interesting journey filled with different emotions, i.e., joy and frustration, hope and despair, and T laughter and sadness. -
NASDAQ Stock Market
Nasdaq Stock Market Friday, December 28, 2018 Name Symbol Close 1st Constitution Bancorp FCCY 19.75 1st Source SRCE 40.25 2U TWOU 48.31 21st Century Fox Cl A FOXA 47.97 21st Century Fox Cl B FOX 47.62 21Vianet Group ADR VNET 8.63 51job ADR JOBS 61.7 111 ADR YI 6.05 360 Finance ADR QFIN 15.74 1347 Property Insurance Holdings PIH 4.05 1-800-FLOWERS.COM Cl A FLWS 11.92 AAON AAON 34.85 Abiomed ABMD 318.17 Acacia Communications ACIA 37.69 Acacia Research - Acacia ACTG 3 Technologies Acadia Healthcare ACHC 25.56 ACADIA Pharmaceuticals ACAD 15.65 Acceleron Pharma XLRN 44.13 Access National ANCX 21.31 Accuray ARAY 3.45 AcelRx Pharmaceuticals ACRX 2.34 Aceto ACET 0.82 Achaogen AKAO 1.31 Achillion Pharmaceuticals ACHN 1.48 AC Immune ACIU 9.78 ACI Worldwide ACIW 27.25 Aclaris Therapeutics ACRS 7.31 ACM Research Cl A ACMR 10.47 Acorda Therapeutics ACOR 14.98 Activision Blizzard ATVI 46.8 Adamas Pharmaceuticals ADMS 8.45 Adaptimmune Therapeutics ADR ADAP 5.15 Addus HomeCare ADUS 67.27 ADDvantage Technologies Group AEY 1.43 Adobe ADBE 223.13 Adtran ADTN 10.82 Aduro Biotech ADRO 2.65 Advanced Emissions Solutions ADES 10.07 Advanced Energy Industries AEIS 42.71 Advanced Micro Devices AMD 17.82 Advaxis ADXS 0.19 Adverum Biotechnologies ADVM 3.2 Aegion AEGN 16.24 Aeglea BioTherapeutics AGLE 7.67 Aemetis AMTX 0.57 Aerie Pharmaceuticals AERI 35.52 AeroVironment AVAV 67.57 Aevi Genomic Medicine GNMX 0.67 Affimed AFMD 3.11 Agile Therapeutics AGRX 0.61 Agilysys AGYS 14.59 Agios Pharmaceuticals AGIO 45.3 AGNC Investment AGNC 17.73 AgroFresh Solutions AGFS 3.85 -
IBIS Open Forum Minutes
IBIS Open Forum Minutes Meeting Date: March 12, 2010 Meeting Location: Teleconference VOTING MEMBERS AND 2010 PARTICIPANTS Actel (Prabhu Mohan) Agilent Radek Biernacki, Ming Yan, Fangyi Rao AMD Nam Nguyen Ansoft Corporation (Steve Pytel) Apple Computer (Matt Herndon) Applied Simulation Technology (Fred Balistreri) ARM (Nirav Patel) Cadence Design Systems Terry Jernberg*, Wenliang Dai, Ambrish Varma Cisco Systems Syed Huq*, Mike LaBonte*, Tony Penaloza, Huyen Pham, Bill Chen, Ravindra Gali, Zhiping Yang Ericsson Anders Ekholm*, Pete Tomaszewski Freescale Jon Burnett, Om Mandhana Green Streak Programs Lynne Green Hitachi ULSI Systems (Kazuyoshi Shoji) Huawei Technologies (Jinjun Li) IBM Adge Hawes* Infineon Technologies AG (Christian Sporrer) Intel Corporation (Michael Mirmak), Myoung (Joon) Choi, Vishram Pandit, Richard Mellitz IO Methodology Lance Wang* LSI Brian Burdick* Mentor Graphics Arpad Muranyi*, Neil Fernandes, Zhen Mu Micron Technology Randy Wolff* Nokia Siemens Networks GmbH Eckhard Lenski* Samtec (Corey Kimble) Signal Integrity Software Walter Katz*, Mike Steinberger, Todd Westerhoff, Barry Katz Sigrity Brad Brim, Kumar Keshavan Synopsys Ted Mido Teraspeed Consulting Group Bob Ross*, Tom Dagostino Toshiba (Yasumasa Kondo) Xilinx Mike Jenkins ZTE (Huang Min) Zuken Michael Schaeder OTHER PARTICIPANTS IN 2010 AET, Inc. Mikio Kiyono Altera John Oh, Hui Fu Avago Razi Kaw Broadcom Mohammad Ali Curtiss-Wright John Phillips ECL, Inc. Tom Iddings eSilicon Hanza Rahmai Exar Corp. Helen Nguyen Mindspeed Bobby Altaf National Semiconductor Hsinho Wu* NetLogic Microsystems Eric Hsu, Edward Wu Renesas Technology Takuji Komeda Simberian Yuriy Shlepnev Span Systems Corporation Vidya (Viddy) Amirapu Summit Computer Systems Bob Davis Tabula David Banas* TechAmerica (Chris Denham) Texas Instruments Bonnie Baker Independent AbdulRahman (Abbey) Rafiq, Robert Badal In the list above, attendees at the meeting are indicated by *. -
Efpgas : Architectural Explorations, System Integration & a Visionary Industrial Survey of Programmable Technologies Syed Zahid Ahmed
eFPGAs : Architectural Explorations, System Integration & a Visionary Industrial Survey of Programmable Technologies Syed Zahid Ahmed To cite this version: Syed Zahid Ahmed. eFPGAs : Architectural Explorations, System Integration & a Visionary Indus- trial Survey of Programmable Technologies. Micro and nanotechnologies/Microelectronics. Université Montpellier II - Sciences et Techniques du Languedoc, 2011. English. tel-00624418 HAL Id: tel-00624418 https://tel.archives-ouvertes.fr/tel-00624418 Submitted on 16 Sep 2011 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. Université Montpellier 2 (UM2) École Doctorale I2S LIRMM (Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier) Domain: Microelectronics PhD thesis report for partial fulfillment of requirements of Doctorate degree of UM2 Thesis conducted in French Industrial PhD (CIFRE) framework between: Menta & LIRMM lab (Dec.2007 – Feb. 2011) in Montpellier, FRANCE “eFPGAs: Architectural Explorations, System Integration & a Visionary Industrial Survey of Programmable Technologies” eFPGAs: Explorations architecturales, integration système, et une enquête visionnaire industriel des technologies programmable by Syed Zahid AHMED Presented and defended publically on: 22 June 2011 Jury: Mr. Guy GOGNIAT Prof. at STICC/UBS (Lorient, FRANCE) President Mr. Habib MEHREZ Prof. at LIP6/UPMC (Paris, FRANCE) Reviewer Mr. -
Architecture Exploration of FPGA Based Accelerators for Bioinformatics Applications Springer Series in Advanced Microelectronics
Springer Series in Advanced Microelectronics 55 B. Sharat Chandra Varma Kolin Paul M. Balakrishnan Architecture Exploration of FPGA Based Accelerators for BioInformatics Applications Springer Series in Advanced Microelectronics Volume 55 Series editors Kukjin Chun, Seoul, Korea, Republic of (South Korea) Kiyoo Itoh, Tokyo, Japan Thomas H. Lee, Stanford, CA, USA Rino Micheloni, Vimercate (MB), Italy Takayasu Sakurai, Tokyo, Japan Willy M.C. Sansen, Leuven, Belgium Doris Schmitt-Landsiedel, München, Germany The Springer Series in Advanced Microelectronics provides systematic information on all the topics relevant for the design, processing, and manufacturing of microelectronic devices. The books, each prepared by leading researchers or engineers in their fields, cover the basic and advanced aspects of topics such as wafer processing, materials, device design, device technologies, circuit design, VLSI implementation, and subsystem technology. The series forms a bridge between physics and engineering and the volumes will appeal to practicing engineers as well as research scientists. More information about this series at http://www.springer.com/series/4076 B. Sharat Chandra Varma Kolin Paul • M. Balakrishnan Architecture Exploration of FPGA Based Accelerators for BioInformatics Applications 123 B. Sharat Chandra Varma M. Balakrishnan Department of Electrical and Electronic Department of Computer Science Engineering and Engineering The University of Hong Kong Indian Institute of Technology Delhi Hong Kong New Delhi, Delhi Hong Kong India Kolin Paul Department of Computer Science and Engineering Indian Institute of Technology Delhi New Delhi, Delhi India ISSN 1437-0387 ISSN 2197-6643 (electronic) Springer Series in Advanced Microelectronics ISBN 978-981-10-0589-3 ISBN 978-981-10-0591-6 (eBook) DOI 10.1007/978-981-10-0591-6 Library of Congress Control Number: 2016931344 © Springer Science+Business Media Singapore 2016 This work is subject to copyright. -
Run-Time Dynamically-Adaptable FPGA-Based Architecture for High-Performance Autonomous Distributed Systems
Departamento de Automática, Ingeniería Eléctrica y Electrónica e Informática Industrial Escuela Técnica Superior de Ingenieros Industriales Run-Time Dynamically-Adaptable FPGA-Based Architecture for High-Performance Autonomous Distributed Systems Autor: Juan Valverde Alcalá Ingeniero Industrial por la Universidad Politécnica de Madrid Directores: Jorge Portilla Berrueco Doctor por la Universidad Politécnica de Madrid en Ingeniería Electrónica Eduardo de la Torre Arnanz Doctor Ingeniero Industrial por la Universidad Politécnica de Madrid 2015 Tribunal Tribunal nombrado por el Excmo. y Magfco. Sr. Rector de la Universidad Politécnica de Madrid, el día 6 de Noviembre de 2015. Presidente: Carlos López Barrio, Universidad Politécnica de Madrid Vocales: Roberto Sarmiento Rodríguez, Universidad de Las Palmas de Gran Canaria Christian De Schryver, Universidad Kaiserslautern Secretario: Teresa Riesgo Alcaide, Universidad Politécnica de Madrid Suplentes: Marta Portela García, Universidad Carlos III de Madrid Ángel de Castro Martín, Universidad Autónoma de Madrid Realizado el acto de lectura y defensa de la Tesis Doctoral el día 16 de Diciembre de 2015 en la Escuela Técnica Superior de Ingenieros Industriales de la Universidad Politécnica de Madrid. Calificación: EL PRESIDENTE LOS VOCALES EL SECRETARIO Посвета Ова докторска теза је посвећена мом животном партнеру. Зато што само са њом уживам у сваком тренутку свог живота. Зато што ме она учи како да будем снажан без обзира шта се деси. Зато што, кад сам са њом, знам да је све савршено и да сам спокојан. Зато што смо победили време и раздаљину и сада можемо да радимо шта год пожелимо. Agradecimientos A mis padres, mi hermana y Estefa, por traerme hasta aquí día tras día viéndome sufrir y trabajar, y diciéndome, “venga, otro pasito más”. -
IBIS Open Forum Minutes
IBIS Open Forum Minutes Meeting Date: September 10, 2010 Meeting Location: Teleconference VOTING MEMBERS AND 2010 PARTICIPANTS Agilent Radek Biernacki, Ming Yan, Fangyi Rao, Gilbert Berger, Amolak Badeasa, Jose Pino, Junaid Khan AMD Nam Nguyen* Ansys (Ansoft Corporation) Danil Kirsanov Apple Computer (Matt Herndon) Applied Simulation Technology (Fred Balistreri) ARM (Nirav Patel) Cadence Design Systems Terry Jernberg*, Wenliang Dai, Ambrish Varma Cisco Systems Syed Huq, Mike LaBonte*, Tony Penaloza, Huyen Pham, Bill Chen, Ravindra Gali, Zhiping Yang Ericsson Anders Ekholm*, Pete Tomaszewski Freescale Jon Burnett, Om Mandhana Green Streak Programs Lynne Green Hitachi ULSI Systems Yutaka Uematsu Huawei Technologies (Jinjun Li) IBM Adge Hawes, Greg Edlund* Infineon Technologies AG Christian Sporrer Intel Corporation Michael Mirmak*, Myoung (Joon) Choi, Vishram Pandit, Richard Mellitz IO Methodology Lance Wang* LSI Brian Burdick* Mentor Graphics Arpad Muranyi*, Neil Fernandes, Zhen Mu Micron Technology Randy Wolff* Nokia Siemens Networks GmbH Eckhard Lenski* Samtec (Corey Kimble) Signal Integrity Software Walter Katz*, Mike Steinberger, Todd Westerhoff, Barry Katz Sigrity Brad Brim, Kumar Keshavan, Srdjan Djordjevic, Ben Franklin Synopsys Ted Mido, Paul Lo, Geoffrey Ying, Frank Lee Teraspeed Consulting Group Bob Ross*, Tom Dagostino Texas Instruments Bonnie Baker* Toshiba Yoshihiro Hamaji Xilinx Mike Jenkins ZTE (Huang Min) Zuken Michael Schaeder, Ralf Bruening OTHER PARTICIPANTS IN 2010 Actel (Prabhu Mohan) AET, Inc. Mikio Kiyono Altera -
Partial Reconfiguration on Fpgas
PPaarrttiiaall RReeccoonnffiigguurraattiioonn oonn FFPPGGAAss Dirk Koch ([email protected]) 1 Introduction: Terms and Definitions Definition of the term „Reconfigurable Computing“ (RC) ° A good definition for a reconfigurable hardware system was introduced with the Rammig Machine (by Franz Rammig 1977): … a system, which, with no manual or mechanical inter- ference, permits the building, changing, processing and destruction of real (not simulated) digital hardware ° Reconfigurable computing (RC) is defined as the study of computation using reconfigurable devices This includes architectures, algorithms and applications ° The term RC is often used to express that computation is carried out using dedicated hardware structures (often utilizing a high level of parallelism) which are mapped on reconfigurable hardware (this is opposed to the sequential von Neumann computer paradigm!!!). 2 How does it Work? Look-up Tables Example of a SRAM-based look-up table (LUT) function generator. A LUT is basically a multiplexer that evaluates the truth table stored in the configuration SRAM cells (can be seen as a one bit wide ROM). A k-input LUT has 2k SRAM cells. 0 configuration SRAM cell tradeoff between Vdd 1 config power enable 2 and speed config 3 data 0 0 optimized for 4 1 1 state lowest power flip-flop 5 configura- L 6 tion cell 7 Q L F F . A0 A . 0 . A A 1 connection to 1 A2 A2 switch matrix A A3 3 FF 3 How does it Work? Look-up Tables Configuration examples Note that by permutating LUT values, inputs can be swapped (usefull for routing); it is also possible to rouite through a LUT. -
An Open-Source FPGA Research and Prototyping Framework
PRGA: An Open-Source FPGA Research and Prototyping Framework Ang Li David Wentzlaff angl(at)princeton(dot)edu wentzlaf(at)princeton(dot)edu Princeton University Princeton University Princeton, New Jersey Princeton, New Jersey ABSTRACT 1 INTRODUCTION Field Programmable Gate Arrays (FPGA) are being used in a fast- Field Programmable Gate Arrays (FPGAs) have become an in- growing range of scenarios, and heterogeneous CPU-FPGA systems creasingly important tool to enable application performance in are being tapped as a possible way to mitigate the challenges posed a post Moore’s Law [19] world. Whether they are being used as by the end of Moore’s Law. This growth in diverse use cases has a standalone compute fabric or a supplement to processors at the fueled the need to customize FPGA architectures for particular chip-level [8, 10, 29], board-level [20], system-level, or datacenter- applications or application domains. While high-level FPGA models level [1, 5], the diversity of use cases and importance of FPGAs can help explore the FPGA architecture space, as FPGAs move to have been increasing. Ideally, an FPGA architecture should be op- more advanced design nodes, there is an increased need for low- timized for each unique use case. In practice, though, it is very level FPGA research and prototyping platforms that can be brought challenging to evaluate different FPGA designs in detail and even all the way to fabrication. more challenging and time-consuming to prototype and bring those This paper presents Princeton Reconfigurable Gate Array FPGAs to fabrication. This is because FPGA chip design flow has (PRGA), a highly customizable, scalable, and complete open-source diverged from the design flows of other digital ASICs like pro- framework for building custom FPGAs. -
FPGA Devices & FPGA Design Flow ECE 448 Lecture 5
ECE 448 Lecture 5 FPGA Devices & FPGA Design Flow ECE 448 – FPGA and ASIC Design with VHDL George Mason University Required reading • Spartan-6 FPGA Configurable Logic Block: User Guide § CLB Overview § Slice Description 2 What is an FPGA? Configurable Logic Blocks Block RAMs Block RAMs I/O Blocks Block RAMs ECE 448 – FPGA and ASIC Design with VHDL 3 Modern FPGA RAMRAM bblockslocks Multipliers/DSPMultipliers units LogicLog resourcesic blocks (#Logic resources, #Multipliers/DSP units, #RAM_blocks) Graphics based on The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) 4 Major FPGA Vendors SRAM-based FPGAs • Xilinx, Inc. ~ 51% of the market ~ 85% • Altera Corp. ~ 34% of the market • Lattice Semiconductor • Atmel • Achronix • Tabula Flash & antifuse FPGAs • Microsemi SoC Products Group (formerly Actel Corp.) • Quick Logic Corp. ECE 448 – FPGA and ASIC Design with VHDL 5 Xilinx u Primary products: FPGAs and the associated CAD software Programmable Logic Devices ISE Alliance and Foundation Series Design Software u Main headquarters in San Jose, CA u Fabless* Semiconductor and Software Company u UMC (Taiwan) {*Xilinx acquired an equity stake in UMC in 1996} u Seiko Epson (Japan) u TSMC (Taiwan) u Samsung (Korea) ECE 448 – FPGA and ASIC Design with VHDL 6 Xilinx FPGA Families Technology Low-cost High- performance 220 nm Virtex 180 nm Spartan-II, Spartan-IIE 120/150 nm Virtex-II, Virtex-II Pro 90 nm Spartan-3 Virtex-4 65 nm Virtex-5 45 nm Spartan-6 40 nm Virtex-6 28 nm Arx-7 Virtex-7 FPGA Family 8 Spartan-6 FPGA Family ECE 448 – FPGA and ASIC Design with VHDL 9 CLB Structure ECE 448 – FPGA and ASIC Design with VHDL George Mason University General structure of an FPGA Programmable interconnect Programmable logic blocks The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. -
Hardware Acceleration
CprE 488 – Embedded Systems Design Lecture 8 – Hardware Acceleration Joseph Zambreno Electrical and Computer Engineering Iowa State University www.ece.iastate.edu/~zambreno rcl.ece.iastate.edu First, solve the problem. Then, write the code. – John Johnson Motivation: Moore’s Law • Every two years: – Double the number of transistors – Build higher performance general-purpose processors • Make the transistors available to the masses • Increase performance (1.8×↑) • Lower the cost of computing (1.8×↓) • Sounds great, what’s the catch? Gordon Moore Zambreno, Spring 2017 © ISU CprE 488 (Hardware Acceleration) Lect-08.2 Motivation: Moore’s Law (cont.) • The “catch” – powering the transistors without melting the chip! 10,000,000,000 2,200,000,000 1,000,000,000 Chip Transistor 100,000,000 Count 10,000,000 1,000,000 100,000 10,000 2300 1,000 130W 100 10 0.5W 1 0 1970 1975 1980 1985 1990 1995 2000 2005 2010 2015 Zambreno, Spring 2017 © ISU CprE 488 (Hardware Acceleration) Lect-08.3 Motivation: Dennard Scaling • As transistors get smaller their power density stays constant Transistor: 2D Voltage-Controlled Switch Dimensions Voltage ×0.7 Doping Robert Dennard Concentrations Area 0.5×↓ Capacitance 0.7×↓ Frequency 1.4×↑ Power = Capacitance × Frequency × Voltage2 Power 0.5×↓ Zambreno, Spring 2017 © ISU CprE 488 (Hardware Acceleration) Lect-08.4 Motivation Dennard Scaling (cont.) • In mid 2000s, Dennard scaling “broke” Transistor: 2D Voltage-Controlled Switch Dimensions Voltage ×0.7 Doping Concentrations Area 0.5×↓ Capacitance 0.7×↓ Frequency 1.4×↑ Power -
Field Programmable Gate Array Implementation Technology
International Journal of Engineering and Advanced Technology (IJEAT ) ISSN: 2249 – 8958, Volume-2, Issue-1, October 2012 Field Programmable Gate Array Implementation Technology Syed.Awais Hyder, D.Sri Kanth, C.Chandrasekhar, E.Sammaiah “personality” when you recompile a different configuration Abstract— A field-programmable gate array (FPGA) is an of circuitry. In the past, FPGA technology could be used only integrated circuit designed to be configured by a customer or a by engineers with a deep understanding of digital hardware designer after manufacturing hence "field-programmable". The design. The rise of high-level design tools, however, is FPGA configuration is generally specified using hardware changing the rules of FPGA programming, with new (HDL), similar to that used for an application-specific integrated technologies that convert graphical block diagrams or even C circuit (ASIC) (circuit diagrams were previously used to specify code into digital hardware circuitry. FPGA chip adoption the configuration, as they were for ASICs, but this is across all industries is driven by the fact that FPGAs combine increasingly rare). FPGAs can be used to implement any logical function that an ASIC could perform. The ability to update the the best parts of ASICs and processor-based systems. FPGAs functionality after shipping, partial re-configuration of a portion provide hardware-timed speed and reliability, but they do not of the design and the low non-recurring engineering costs require high volumes to justify the large upfront expense of relative to an ASIC design (notwithstanding the generally higher custom ASIC design. Reprogrammable silicon also has the unit cost), offer advantages for many applications.