ECE 545 Digital System Design with VHDL – K

ECE 545 Digital System Design with VHDL Fall 2015 Kris Gaj Research and teaching interests: • reconfigurable computing • computer arithmetic • cryptography • network security Contact: The Engineering Building, room 3225 [email protected] Office hours: Thursday, 6:00-7:00 PM, Tuesday, 6:00-7:00 PM, and by appointment Course Web Page ECE web page → Courses → Digital System Design with VHDL (or Google “Kris Gaj”) ECE 545 Part of: MS in Computer Engineering One of five core courses (must be passed with B or better) Fundamental course for the specialization areas: Digital Systems Design Digital Signal Processing Elective course in the remaining specialization areas MS in Electrical Engineering Elective ECE 545 Part of: PhD in Electrical and Computer Engineering Knowledge tested at the Technical Qualifying Exam (TQE) Topic 2: Digital Design and Computer Organization Recommended I am interested I want to specialize program & in… primarily in… specialization CAD tools & Design Automation MS CpE VLSI Hardware Description Languages Digital Systems Design Digital Systems Design FPGAs & Reconfigurable computing ASICs & FPGAs Computer Arithmetic VHDL/Verilog Front-end ASIC Design (algorithmic downto gate level) CAD Tools Back-end ASIC Design (circuit and mask layout levels) Reconfigurable Computing Analog & Digital Circuit Design Microelectronics VLSI Fabrication VLSI Fabrication Microelectronics MS EE Nanoelectronics Nanoelectronics Microelectronics/ Semiconductor Devices Nanoelectronics Design level Courses Digital System Computer VLSI Design VLSI Test Design with VHDL Arithmetic for ASICs Concepts algorithmic ECE ECE ECE 545 699 645 SW/HW register-transfer Codesign ECE ECE gate 681 682 ECE 586 transistor Digital ECE Integrated 680 Circuits layout Physical VLSI Design Semiconductor MOS Device ECE 584 ECE684 devices Device Fundamentals Electronics CpE CpE Digital Systems Design Microprocessors and Embedded Systems ECE 545 Digital System Design ECE 510 Real-Time Concepts with VHDL ECE 511 Microprocessors Pre- ECE 586 Digital Integrated Circuits ECE 611 Advanced Microprocessors Approved ECE 645 Computer Arithmetic ECE 612 Real-Time Emb. Systems ECE 681 VLSI Design for ASICs ECE 641 Computer System Arch. Electives ECE 682 VLSI Test Concepts ECE 699 SW/HW Codesign ECE 699 SW/HW Codesign ECE 699 Green Computing and ECE 740 DSP HW Architectures Heterogeneous Architectures ECE 545, 645, 681 (digital design) Suggested ECE 584, 684, … (technology) CS 571 (operating systems) ECE 511, 611, … (microprocessors) CS 540, 583 (languages, algorithms) Electives ECE 535, 537, 646, …(applications: CS 580 (artificial intelligence) DSP, image processing, crypto, etc.) ECE 542, 642, 742 (networks) ECE 548 (sequential mach. theory) K. Gaj, H. Homayoun, J-P. Kaps H. Homayoun, J. Kaps, P. Pachowicz, Professors T. Storey, A. Cohen C. Sabzevari DIGITAL SYSTEMS DESIGN 1. ECE 545 Digital System Design with VHDL – K. Gaj, project, FPGA design with VHDL 2. ECE 699 Software/Hardware Codesign – K. Gaj, homework, SoC design with VHDL and C 3. ECE 645 Computer Arithmetic – K. Gaj, project, FPGA design with VHDL or Verilog 4. ECE 681 VLSI Design for ASICs – H. Homayoun, project/lab, front-end and back-end ASIC design with Synopsys tools 5. ECE 586 Digital Integrated Circuits – D. Ioannou, R. Mulpuri, homework 6a. ECE 682 VLSI Test Concepts – T. Storey, homework 6b. ECE 740 Digital Signals Processing Hardware Architectures – A. Cohen, project, FPGA design with VHDL and Matlab/Simulink MICROPROCESSOR AND EMBEDDED SYSTEMS 1. ECE 510 Real-Time Concepts – P. Pachowicz, project, design of real-time systems 2. ECE 511 Microprocessors – J.P. Kaps, project, system based on MSP430 microcontroller 3. ECE 611 Advanced Microprocessors – H. Homayoun, project, computer architecture simulation tools 4. ECE 612 Real-Time Embedded System – C. Sabzevari, project, programming distributed real-time systems 5. ECE 641 Computer System Architecture – H. Homayoun, project, computer architecture simulation tools 6. ECE 699 Software/Hardware Codesign – K. Gaj, homework, SoC design with VHDL and C 7. ECE 699 Heterogeneous Architectures and Green Computing – H. Homayoun, project, computer architecture simulation tools TA Sanjay Deshpande • help with the installation and configuration of CAD tools • help with understanding of tutorials and the operation of tools • help with VHDL and tool-oriented homework assignments • limited help with debugging your MS Thesis Student project codes in the Cryptographic Engineering Research Group (CERG) Getting Help Outside of Office Hours • System for asking questions 24/7 • Answers can be given by students and instructors • Student answers endorsed (or corrected) by instructors • Average response time in Fall 2014 = 1.5 hour • You can submit your questions anonymously • You can ask private questions visible only to the instructors Grading Scheme • Homework - 15% • Project - 35% • Midterm Exam - 20% • Final Exam - 30% • Class Activity - Bonus 5% Bonus Points for Class Activity • Based on class exercises during lecture • “Small” points earned each week posted on BlackBoard • Up to 5 “big” bonus points • Scaled based on the performance of the best student For example: Small points Big points 1. Alice 40 5 2. Bob 36 4.5 … … … 28. Charlie 8 1 Midterm exam 1 ü 2 hours 40 minutes ü in class ü design-oriented ü open-books, cheat sheet ü practice exams available on the web Tentative date: Last week of October Final exam ü 2 hours 45 minutes ü in class ü design-oriented ü open-books, cheat sheet ü practice exams available on the web Date: Thursday, December 17, 7:30-10:15pm Textbooks 17 Required Textbook Pong P. Chu, RTL Hardware Design Using VHDL, Wiley-Interscience, 2006. K?<JB@CCJ8E;>L@;8E:<E<<;<;KF D8JK<IIKC?8I;N8I<;<J@>E K_`j Yffb k\XZ_\j i\X[\ij _fn kf jpjk\dXk`ZXccp [\j`ê \]ÔZ`\ek# gfikXYc\# Xe[ jZXcXYc\ I\^`jk\i KiXej]\i C\m\c IKC [`^`kXc ZìZl`kj ljè^ k_\ M?;C _Xi[nXi\ [\jZi`gk`fe cXe^lX^\ Xe[ jpek_\j`j jf]knXi\% =fZljè^ fe k_\ df[lc\$c\m\c [\j`ê# n_`Z_ `j Zfdgfj\[ f] :?L ]leZk`feXc le`kj# iflkè^ ZìZl`k# Xe[ jkfiX^\# k_\ Yffb `ccljkiXk\j k_\ i\cXk`fej_`g Y\kn\\e k_\M?;CZfejkilZkjXe[k_\le[\icpè^_Xi[nXi\Zfdgfe\ekj#Xe[j_fnj_fnkf[\m\cfg IKC?8I;N8I<;<J@>E Zf[\jk_Xk]X`k_]lccpi\Õ\Zkk_\df[lc\$c\m\c[\j`êXe[ZXeY\jpek_\j`q\[èkf\]ÔZ`\ek ^Xk\$c\m\c`dgc\d\ekXk`fe% J\m\iXcle`hl\]\Xkli\j[`jkè^l`j_k_\Yffb1 :f[è^jkpc\k_Xkj_fnjXZc\Xii\cXk`fej_`gY\kn\\eM?;CZfejkilZkjXe[ _Xi[nXi\Zfdgfe\ekj :feZ\gklXc[`XîXdjk_Xk`ccljkiXk\k_\i\Xc`qXk`fef]M?;CZf[\j <dg_Xj`jfek_\Zf[\i\lj\ GiXZk`ZXc\oXdgc\jkf[\dfejkiXk\Xe[i\è]fiZ\[\j`êZfeZ\gkj# gifZ\[li\j#Xe[k\Z_e`hl\j LJ@E>M?;C KnfZ_Xgk\ijfei\Xc`qè^j\hl\ek`XcXc^fi`k_djè_Xi[nXi\ KnfZ_Xgk\ijfejZXcXYc\Xe[gXiXd\k\i`q\[[\j`êjXe[Zf[è^ IKC ?8I;N8I<;<J@>E Fe\Z_Xgk\iZfm\iè^k_\jpeZ_ife`qXk`feXe[èk\i]XZ\Y\kn\\edlck`gc\ ZcfZb[fdXèj 8ck_fl^_k_\]fZljf]k_\Yffb`jIKCjpek_\j`j#`kXcjf\oXdè\jk_\jpek_\j`jkXjb]ifdk_\ LJ@E>M?;C g\ijg\Zk`m\f]k_\fm\iXcc[\m\cfgd\ekgifZ\jj%I\X[\ijc\Xie^ff[[\j`êgiXZk`Z\jXe[ ^l`[\cè\jkf\ejli\k_XkXeIKC[\j`êZXeXZZfddf[Xk\]lkli\j`dlcXk`fe#m\i`ÔZXk`fe#Xe[ k\jkèê\\[j#Xe[ZXeY\\Xj`cpèZfigfiXk\[èkfXcXi^\ijpjk\dfii\lj\[%;`jZljj`fe`jè$ [\g\e[\ekf]k\Z_efcf^pXe[ZXeY\Xggc`\[kfYfk_8J@:Xe[=G>8[\m`Z\j% N`k_ X YXcXeZ\[ gi\j\ekXk`fe f] ]le[Xd\ekXcj Xe[ giXZk`ZXc \oXdgc\j# k_`j `j Xe \oZ\c$ c\ekk\okYffb]filgg\i$c\m\cle[\iîX[lXk\fiîX[lXk\Zflij\jèX[mXeZ\[[`^`kXccf^`Z% <e^è\\ijn_fe\\[kfdXb\\]]\Zk`m\lj\f]kf[XpËjjpek_\j`jjf]knXi\Xe[=G>8[\m`Z\j JZXcXY`c`kp GfikXY`c`kp#Xe[ :f[è^]fi<]ÔZ`\eZp# j_flc[Xcjfi\]\ikfk_`jYffb% GFE>G%:?L#G?;#`j8jjfZ`Xk\Gif]\jjfièk_\;\gXikd\ekf]<c\Zki`ZXcXe[:fdglk\i :f[è^]fi<]ÔZ`\eZp#GfikXY`c`kp#Xe[JZXcXY`c`kp <e^è\\iè^# :c\m\cXe[ JkXk\ Le`m\ij`kp% ?\ _Xj i\Z\`m\[ îXekj ]ifd Yfk_ E8J8 Xe[ k_\ EXk`feXcJZ`\eZ\=fle[Xk`feXe[_XjkXl^_kle[\iîX[lXk\Xe[îX[lXk\$c\m\c[`^`kXcjpjk\dj Xe[Zfdglk\iXiZ_`k\Zkli\Zflij\j]fidfi\k_XeX[\ZX[\% GFE>G%:?L Supplementary Textbook – Basics Refresher Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Design, McGraw-Hill, 3rd or 2nd Edition Supplementary Textbook – Advanced Hubert Kaeslin, Digital Integrated Circuit Design: From VLSI Architectures to CMOS Fabrication, Cambridge University Press; 1st Edition, 2008. Technology & Tools 21 What is an FPGA? Configurable Logic Blocks (CLB) / Adaptive Logic Modules (ALM) Block RAMs Block RAMs I/O Blocks Block RAMs Modern FPGA RAMRAM bblockslocks Multipliers/DSPMultipliers units LogicLogic b resourceslocks (CLBs or ALMs) (#Logic resources, #Multipliers/DSP units, #RAM_blocks) Graphics based on The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) 23 General structure of an FPGA Programmable interconnect Programmable logic blocks The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) ECE 448 – FPGA and ASIC Design with VHDL 24 4-input LUT (Look-Up Table) (used in earlier families of FPGAs) • Look-Up tables x1 x 2 y x x x x y x3 LUT x x x x y are primary 1 2 3 4 x 1 2 3 4 0 0 0 0 1 4 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 elements for 0 0 1 0 1 0 0 1 0 0 0 0 1 1 1 0 0 1 1 0 logic 0 1 0 0 1 0 1 0 0 0 0 1 0 1 1 0 1 0 1 1 0 1 1 0 1 0 1 1 0 0 implementation 0 1 1 1 1 0 1 1 1 1 1 0 0 0 1 1 0 0 0 0 1 0 0 1 1 1 0 0 1 1 • Each LUT can 1 0 1 0 1 1 0 1 0 0 1 0 1 1 1 1 0 1 1 0 implement any 1 1 0 0 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 x x x x function of 1 1 1 0 0 1 2 3 4 1 1 1 0 0 1 1 1 1 0 1 1 1 1 0 4 inputs x1 x2 y y 25 6-Input LUT of Spartan-6 ECE 448 – FPGA and ASIC Design with VHDL 26 Two competing implementation approaches ASIC FPGA Application Specific Field Programmable Integrated Circuit Gate Array • designed all the way • no physical layout design; from behavioral description design ends with to physical layout a bitstream used to configure a device • designs must be sent for expensive and time • bought off the shelf consuming fabrication and reconfigured by in semiconductor foundry designers themselves FPGAs vs.

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