Oriented Conferences Four Solutions

Total Page:16

File Type:pdf, Size:1020Kb

Oriented Conferences Four Solutions Delivering Solutions and Technology to the World’s Design Engineering Community Four Solutions- Oriented Conferences • System-on-Chip Design Conference • IP World Forum • High-Performance System Design Conference • Wireless and Optical Broadband Design Conference Special Technology Focus Areas January 29 – February 1, 2001 • Internet and Information Exhibits: January 30–31, 2001 Appliance Design Santa Clara Convention Center • Embedded Design Santa Clara, California • RF, Optical, and Analog Design NEW! • IEC Executive Forum International Engineering Register by January 5 and Consortium save $100 – and be entered to win www.iec.org a Palm Pilot! Practical Design Solutions Practical design-engineering solutions presented by practicing engineers—The DesignCon reputation of excellence has been built largely by the practical nature of its sessions. Design engineers hand selected by our team of professionals provide you with the best electronic design and silicon-solutions information available in the industry. DesignCon provides attendees with DesignCon has an established reputation for the high design solutions from peers and professionals. quality of its papers and its expert-level speakers from Silicon Valley and around the world. Each year more than 100 industry pioneers bring to light the design-engineering solutions that are on the leading edge of technology. This elite group of design engineers presents unique case studies, technology innovations, practical techniques, design tips, and application overviews. Who Should Attend Any professionals who need to stay on top of current information regarding design-engineering theories, The most complete educational experience techniques, and application strategies should attend this in the industry conference. DesignCon attracts engineers and allied The four conference options of DesignCon 2001 provide a professionals from all levels and disciplines. Professionals complete educational experience, including the practical design attending DesignCon work in ASIC design, communica- solutions you need. DesignCon is the only meeting that brings tions, digital design, radio frequency (RF) and analog leading designers together to discuss the current industry trends, design, test and measurement, mixed signal, field learn the best design solutions, network with industry peers, and programmable gate arrays (FPGAs), printed circuit boards interact with the companies that provide the equipment that (PCBs), programmable logic devices (PLDs), circuit-board makes solutions possible. At DesignCon 2001, you will find the design, integrated-circuit (IC) design, software optionality best educational value available in the industry. control and applications design, systems architecture, hardware/software integration, convergent technologies, Selected paper presentations at DesignCon are closely tied to packaging, testing, debugging, applications design, and technological exhibits. Attendees will see the technological future more. in action! Take part in the DesignCon difference today and • Advisory Engineers • Internet and Information become part of the most prestigious and most complete • Chief Scientists Appliance Designers educational conference offered in design engineering. • Circuit Designers • Technical Staff • CMOS Circuit Analysis and • Program Directors Development Engineers • Project Engineers, Leaders, • Presidents, Vice Presidents, and Managers Attendees find valuable networking and Chief Executive Officers • Research Engineers opportunities throughout the conference. • Design Engineers and • R&D Engineers Principals • Semiconductor Product • Directors of Research and Managers Development • Senior Engineers • EDA Engineering Managers • Senior Members of Technical • Editors and Executives of the Staff Technical Media • Senior Productivity Engineers • Embedded System Designers • Signal Integrity Engineers • Engineering Fellows • Software Engineers • Engineering Managers • System Architects • Field Applications Engineers • System-Design Engineers and • Hardware Engineers Managers • Hardware Verification • Technical Vice Presidents Engineers • Venture-Capital Analysts • Hardware/Software IC Design 2 DesignCon 2001 January 29 – February 1, 2001 Keynotes and Plenary Panel Tuesday, January 30 • 12:00 pm – 1:00 pm Wednesday, January 31 • 11:00 am – 12:00 pm Tuesday Keynote Presentation Plenary Panel Walden Rhines, President and Chief Executive Design Engineering and the World Wide Web: Officer, Mentor Graphics, is on the board of Where They Meet to Create Ultimate Value directors for the Electronic Design Automation Consortium (EDAC) and is a board member for Chip and system design engineers are being offered new Web- the Oregon Independent College Foundation and based options for access to EDA tools, component data, and for Lewis and Clark College. Prior to joining computer services. It is uncertain whether such services will only Mentor Graphics, Dr. Rhines was executive vice president in represent a niche for tool use and component access or whether charge of Texas Instruments’ Semiconductor Group. During his engineers will receive great value and develop a high dependence career at TI, Dr. Rhines was responsible for developing products on the web for electronic design. Expert users on this panel such as TI’s first speech synthesis devices (used in "Speak and discuss the value that they are experiencing, or would expect to Spell") and the TMS 320 family of digital signal processors. receive, from web-based services. Suppliers of web-based services discuss the benefits that they see the web bringing to the design community and how the services can best be deployed. Wednesday, January 31 • 12:00 pm – 1:00 pm C HAIRPERSON Wednesday Keynote Presentation Jack Shandle, Chief Editor, eChips, has worked for daily Charles Fox, President and Chief Executive newspapers and electronics OEM trade magazines, freelanced for national publications, and authored a novel. He has also Officer, Chameleon Systems, has 20 years of worked for four national and statewide political campaigns as experience in microprocessor, FPGA and ASIC an advance man and media coordinator. In 1986, he joined products in both marketing and general Electronics magazine. From Electronics, Mr. Shandle moved to management. He was most recently vice president Electronic Design magazine where he became chief editor in 1994. and general manager of the ASIC business unit at PANELISTS Xilinx. Previously he was vice president of worldwide marketing. David Burow, Senior Vice President, Internet Design and Prior to Xilinx, Mr. Fox spent nine years in marketing manage- Services Group, Synopsys, joined Synopsys in connection with ment within Intel's microprocessor, peripheral, and ASIC groups. the company's merger with Viewlogic in December 1997. He was with Viewlogic from August of 1995 as vice president of the high-level design group after serving in a number of key Tuesday, January 30, 6:30 pm – 8:00 pm management positions at Silicon Architects, which was acquired by Synopsys in May 1995. Special Evening Reception and Speaker Judy M. Owen, Founder, President, and Chief Executive Officer, Join us for a relaxing evening with Robert A. SiliconX, started her career at Intel, developing memory chips Pease, Staff Scientist-Circuit Design, National and then microprocessor chips. In 1981 she was appointed to Semiconductor. A well-recognized speaker, Mr. manage a select group within Intel to develop proprietary CAD Pease will enlighten attendees with trends in software tools to protect Intel’s intellectual property and circuit design and the Semiconductor Industry, shorten the chip design cycle. Prior to starting SiliconX, Ms. Owen founded Wireless Access in 1991, serving as its president and chief and entertain everyone with his humor, wit and executive officer. insight into industry snafus, and successes! Mr. Pease obtained his BSEE from Massachusetts Institute of Technology and is a Mark Ross, Director, Engineering, Cisco Systems, began his noted columnist with Electronic Design Magazine. career developing full custom CMOS chips at Weitek, where he was an early customer of what eventually became Cadence. In 1989, Mr. Ross joined NeXT and led the development of a RISC workstation. At NeXT he was an early customer of Synopsys and specified numerous internal development tools. His next job was at Sun, where he led the development of the Ultrasparc workstations. Contents PAGE Plenary Panels .................................................................................. 3–5 Harry Baeverstad, Manager, Research and Development, Conference Overviews ........................................................................6–7 Hewlett-Packard, is currently leading a new initiative at Executive Forum Workshops .................................................................. 8 Hewlett-Packard to deliver "always-on" Internet-based technical DesignCon Exhibits..........................................................................10–13 computing solutions for engineers and scientists. The first Planning Guides/Topical Index........................................................15-20 product produced from this initiative is "e-utilica," a scalable, TecForums .................................................................................... 21–25 secure, Internet-enabled computer farm providing computer Session Descriptions ...................................................................... 26–41 capacity-on-demand solutions for service providers.
Recommended publications
  • Organising Committees
    DATE 2005 Executive Committee GENERAL CHAIR PROGRAMME CHAIR Nobert Wehn Luca Benini Kaiserslautern U, DE DEIS – Bologna U, IT VICE CHAIR & PAST PROG. CHAIR VICE PROGRAMME CHAIR Georges Gielen Donatella Sciuto KU Leuven, BE Politecnico di Milano, IT FINANCE CHAIR PAST GENERAL CHAIR Rudy Lauwereins Joan Figueras IMEC, Leuven, BE UP Catalunya, Barcelona, ES DESIGNERS’ FORUM DESIGNERS’ FORUM Menno Lindwer Christoph Heer Philips, Eindhoven, NL Infineon, Munich, DE SPECIAL SESSIONS & DATE REP AT DAC FRIDAY WORKSHOPS Ahmed Jerraya Bashir Al-Hashimi TIMA, Grenoble, FR Southampton U, UK INTERACTIVE PRESENTATIONS ELECTRONIC REVIEW Eugenio Villar Wolfgang Mueller Cantabria U, ES Paderborn U, DE WEB MASTER AUDIO VISUAL Udo Kebschull Jaume Segura Heidelberg U, DE Illes Baleares U, ES TUTORIALS & MASTER COURSES FRINGE MEETINGS Enrico Macii Michel Renovell Politecnico di Torino, IT LIRMM, Montpellier, FR AUTOMOTIVE DAY BIOCHIPS DAY Juergen Bortolazzi Christian Paulus DaimlerChrysler, DE Infineon, Munich, DE PROCEEDINGS EXHIBITION PROGRAMME Christophe Bobda Juergen Haase Erlangen U, DE edacentrum, Hannover, DE UNIVERSITY BOOTH UNIVERSITY BOOTH & ICCAD Volker Schoeber REPRESENTATIVE edacentrum, Hannover, DE Wolfgang Rosenstiel Tuebingen U/FZI, DE AWARDS & DATE REP. AT ASPDAC PCB SYMPOSIUM Peter Marwedel Rainer Asfalg Dortmund U, DE Mentor Graphics, DE TRAVEL GRANTS COMMUNICATIONS Marta Rencz Bernard Courtois TU Budapest, HU TIMA, Grenoble, FR LOCAL ARRANGEMENTS PRESS LIASON Volker Dueppe Fred Santamaria Siemens, DE Infotest, Paris, FR ESF CHAIR & EDAA
    [Show full text]
  • Important Notice Dear Customer, on 7 February 2017 The
    Important notice Dear Customer, On 7 February 2017 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS semiconductors with its focus on the automotive, industrial, computing, consumer and wearable application markets In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below. Instead of http://www.nxp.com, http://www.philips.com/ or http://www.semiconductors.philips.com/, use http://www.nexperia.com Instead of [email protected] or [email protected], use [email protected] (email) Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on the version, as shown below: - © NXP N.V. (year). All rights reserved or © Koninklijke Philips Electronics N.V. (year). All rights reserved Should be replaced with: - © Nexperia B.V. (year). All rights reserved. If you have any questions related to the data sheet, please contact our nearest sales office via e-mail or telephone (details via [email protected]). Thank you for your cooperation and understanding, Kind regards, Team Nexperia PMN27XPE 20 V, single P-channel Trench MOSFET 20 September 2012 Product data sheet 1. Product profile 1.1 General description P-channel enhancement mode Field-Effect Transistor (FET) in a small SOT457 (SC-74) Surface-Mounted Device (SMD) plastic package using Trench MOSFET technology. 1.2 Features and benefits • Fast switching • Trench MOSFET technology • 2 kV ESD protection 1.3 Applications • Relay driver • High-speed line driver • High-side loadswitch • Switching circuits 1.4 Quick reference data Table 1.
    [Show full text]
  • Exhibition Report
    Exhibition Report Japan Electronics and Information Technology Industries Association (JEITA) Contents Exhibition Outline 1 Exhibition Configuration 2 1. Scope of Exhibits 2 2. Conference 2 3. Number of Exhibitors and Booths 2 4. Suite Exhibits 2 5. Exhibitors 3 Conference Activities 4 1. Exhibitor Seminars 4 2. Keynote Speech 4 3. Special Event Stage 4 4. The 13th FPGA/PLD Design Conference 4 5. FPGA/PLD Design Conference User’s Presentations 4 6. IP(Intellectual Property) Flea Market in EDSFair 4 7. System Design Forum 2006 Conference 4 Other Events and Special Projects 5 1. Opening Ceremony 5 2. University Plaza 5 3. Venture Conpany Pavilion 5 4. EDAC Reception 5 5. Press 5 Number of Visitors 6 Results of Visitor Questionnaire 6-7 Exhibition Outline Name . Electronic Design and Solution Fair 2006 (EDSFair2006) Duration . Thursday, January 26 and Friday, January 27, 2006 (2 days) 10:00 a.m. to 6:00 p.m. Location . Pacifico Yokohama (Halls C-D hall and Annex Hall) 1-1-1 Minato Mirai, Nishi-ku, Yokohama 220-0012, Japan Admission. Exhibition: Free (registration required at show entrance) Conference: Fees charged for some sessions Sponsorship . Japan Electronics and Information Technology Industries Association (JEITA) Cooperation . Electronic Design Automation Consortium (EDAC) Support . Ministry of the Economy, Trade and Industry, Japan (METI) Embassy of the United States of America in Japan Distributors Association of Foreign Semiconductors (DAFS) City of Yokohama Assistance . Institute of Electronics, Information and Communication Engineers (IEICE) Information Processing Society of Japan (IPSJ) Japan Printed Circuit Association (JPCA) Spacial Assistance. Hewlett-Packard Japan, Ltd. Sun Microsystems K.K Management .
    [Show full text]
  • Table of Contents 2006 IEEE Symposium on VLSI Technology
    13eds02.qxd 3/6/06 8:36 AM Page 1 IEEE E D S ELECTRONELECTRON DEVICESDEVICES SOCIETYSOCIETY Newsletter APRIL 2006 Vol. 13, No. 2 ISSN:1074 1879 Editor-in-Chief: Ninoslav D. Stojadinovic 2006 IEEE Symposium Table of Contents on VLSI Technology Upcoming Technical Meetings .......................1 • 2006 VLSI • 2006 ASMC • 2006 IITC • 2006 UGIM Outgoing Message from the 2004-5 EDS President...................................3 Society News.........................................................9 • December 2005 AdCom Meeting Summary • Message from the EDS Newsletter Editor-in-Chief • EDS Educational Activities Committee Report • EDS Nanotechnology Committee Report • EDS Photovoltaic Devices Committee Report • 2005 EDS J.J. Ebers Award Winner • 2006 EDS J.J. Ebers Award Call for Nominations • 2005 EDS Distinguished Service Award Winner • 2006 Charles Stark Draper Prize Hilton Hawaiian Village, Honolulu, Hawaii • 23 EDS Members Elected to the IEEE The 26th Annual IEEE Symposium on VLSI Technology will Grade of Fellow be held June 13-15, 2006, at the Hilton Hawaiian Village in • 2005 Class of EDS Fellows Honored at IEDM Honolulu, Hawaii. The VLSI Technology Symposium is joint- ly sponsored by the IEEE Electron Devices Society (EDS) and • EDS Members Named Winners of the Japan Society of Applied Physics (JSAP). 2006 IEEE Technical Field Awards The VLSI Symposium is well recognized as one of the • EDS Regions 1-3 & 7 Chapters Meeting Summary premiere conferences on semiconductor technology, and research results presented at the conference represent a • 2005 EDS Chapter of the Year Award broad spectrum of VLSI technology topics, including: • EDS Members Recently Elected • New concepts and breakthroughs in VLSI devices and to IEEE Senior Member Grade processes.
    [Show full text]
  • 6800/68000 Cmos
    Click Here to Request a Large Quantity Quote 6800/68000 CMOS Jameco Manufacturer Manufacturer Description Package Product Type Organization Family Application Price 1 Part # Part # 130366 Major Brands 00130366 420 PIECE DIODE REFILL PACKAGE $29.95 130374 Major Brands 00130374 560 Piece Transistor Kit Refill Package $54.95 130391 Major Brands 00130391 420 Piece 74LS Logic Series Refill Package $214.95 130403 Major Brands 00130403 300 PIECE CD4000 SERIES REFILL PACKAGE $74.95 130411 Major Brands 00130411 480 PIECE LINEAR SERIES REFILL PACKAGE $164.95 1542961 Vishay 1.5KE16CA TVS Diode 22.5V Clamp 66.7A Ipp Through Hole 1500W DO-201 $0.49 1.5KE 2303247 Major Brands 1.5KE8.2C TVS Diode 12.1V Clamp 125.6A Ipp DO-201 DO-201 $0.59 35924 Major Brands 1N1188 Diode 1N1188 400 VOLT 35 AMP SILICON RECTIFIER DO-5 Stud Rectifier $3.95 2197610 Kest Parts 1N1190A Diode 1N1190A Power Silicon Rectifier 40 Amp 600V DO-5 DO-5 Stud Rectifier $4.95 2197628 Kest Parts 1N1190RA Diode 1N1190RA 40A 600V Power Silicon Rectifier DO-5 Stud Rectifier $4.95 2287679 Major Brands 1N1202A 200V 12A Rectifier Stud Mount DO-203 DO-203 Stud Rectifier $1.95 35941 Major Brands 1N270 Diode 1N270 Germanium 1 Volt @ 200Ma DO-7 General $1.19 Purpose 2220533 Major Brands 1N34A Diode 1N34A General Purpose Germanium DO-7 General $1.95 Purpose 35975 Major Brands 1N4001 Diode 1N4001 50 Volt 1 Amp General Purpose Rectifier DO-41 Standard $0.09 76961 Major Brands 1N4002 Diode 1N4002 100 Volt 1A DO-41 package DO-41 Standard $0.09 76970 Major Brands 1N4003 Diode 1N4003 Rectifier 200 Volt
    [Show full text]
  • 152F580552eb358625881dd680
    Products Catalog Index PART NO. MANUFACTURER DESCRIPTION URL PRICE Q65112A2615 OSRAM OPTO Q65112A2615 http://www.searchdatasheet.com/Q65112A2615-datasheet.html QUOTE SEMICONDUCTORS XR33053ID-F EXAR Transceiver 1Mbps 3.3V/5V http://www.searchdatasheet.com/XR33053ID-F-datasheet.html QUOTE 14-Pin SOIC N Tube Q65111A7362 OSRAM OPTO LED Uni-Color White 2-Pin http://www.searchdatasheet.com/Q65111A7362-datasheet.html QUOTE SEMICONDUCTORS SMD T/R EL-17-21UYC/S530-A2/TR8 EVERLIGHT EL-17-21UYC/S530-A2/TR8 http://www.searchdatasheet.com/EL-17-21UYC%2FS530-A2%2FTR8-datasheet.html QUOTE ELECTRONICS Q65112A2616 OSRAM OPTO Q65112A2616 http://www.searchdatasheet.com/Q65112A2616-datasheet.html QUOTE SEMICONDUCTORS Q65111A9950 OSRAM OPTO Q65111A9950 http://www.searchdatasheet.com/Q65111A9950-datasheet.html QUOTE SEMICONDUCTORS Q65112A2629 OSRAM OPTO Q65112A2629 http://www.searchdatasheet.com/Q65112A2629-datasheet.html QUOTE SEMICONDUCTORS Q65112A0819 OSRAM OPTO LED Uni-Color White 2-Pin http://www.searchdatasheet.com/Q65112A0819-datasheet.html QUOTE SEMICONDUCTORS CSMD EP Q65111A9208 OSRAM OPTO Q65111A9208 http://www.searchdatasheet.com/Q65111A9208-datasheet.html QUOTE SEMICONDUCTORS Q65111A8966 OSRAM OPTO Q65111A8966 http://www.searchdatasheet.com/Q65111A8966-datasheet.html QUOTE SEMICONDUCTORS RLR20C1201GMRE6 VISHAY Res Metal Film 1.2K Ohm http://www.searchdatasheet.com/RLR20C1201GMRE6-datasheet.html QUOTE 2% 0.5W(1/2W) ±100ppm/C 1% Epoxy AXL T/R EVMB Connect One Evaluation Master Kit with http://www.searchdatasheet.com/EVMB-datasheet.html QUOTE Semiconductors
    [Show full text]
  • Computer Architectures an Overview
    Computer Architectures An Overview PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Sat, 25 Feb 2012 22:35:32 UTC Contents Articles Microarchitecture 1 x86 7 PowerPC 23 IBM POWER 33 MIPS architecture 39 SPARC 57 ARM architecture 65 DEC Alpha 80 AlphaStation 92 AlphaServer 95 Very long instruction word 103 Instruction-level parallelism 107 Explicitly parallel instruction computing 108 References Article Sources and Contributors 111 Image Sources, Licenses and Contributors 113 Article Licenses License 114 Microarchitecture 1 Microarchitecture In computer engineering, microarchitecture (sometimes abbreviated to µarch or uarch), also called computer organization, is the way a given instruction set architecture (ISA) is implemented on a processor. A given ISA may be implemented with different microarchitectures.[1] Implementations might vary due to different goals of a given design or due to shifts in technology.[2] Computer architecture is the combination of microarchitecture and instruction set design. Relation to instruction set architecture The ISA is roughly the same as the programming model of a processor as seen by an assembly language programmer or compiler writer. The ISA includes the execution model, processor registers, address and data formats among other things. The Intel Core microarchitecture microarchitecture includes the constituent parts of the processor and how these interconnect and interoperate to implement the ISA. The microarchitecture of a machine is usually represented as (more or less detailed) diagrams that describe the interconnections of the various microarchitectural elements of the machine, which may be everything from single gates and registers, to complete arithmetic logic units (ALU)s and even larger elements.
    [Show full text]
  • 28Th IEEE VLSI Test Symposium (VTS 2010) Santa Cruz, CA, April 19-21, 2010
    28th IEEE VLSI Test Symposium (VTS 2010) Santa Cruz, CA, April 19-21, 2010 Preliminary Program (as of 3/25/10) Monday, 4/19/10 Plenary Session (9:00 – 11:00) Break (11:00 – 11:15) Sessions 1 (11:15 – 12:15) Session 1A: Delay & Performance Test 1 Moderator: M. Batek - Broadcom Fast Path Selection for Testing of Small Delay Defects Considering Path Correlations Z. He, T. Lv - Institute of Computing Technology, H. Li, X. Li - Chinese Academy of Sciences Identification of Critical Primitive Path Delay Faults without any Path Enumeration K. Christou, M. Michael, S. Neophytou - University of Cyprus Path Clustering for Adaptive Test T. Uezono, T. Takahashi - Tokyo Institute of Technology, M. Shintani , K. Hatayama - Semiconductor Technology Academic Research Center, K. Masu - Tokyo Institute of Technology, H. Ochi, T. Sato - Kyoto University Session 1B: Memory Test & Repair Moderator: P. Prinetto - Politecnico di Torino Automatic Generation of Memory Built-In Self-Repair Circuits in SOCs for Minimizing Test Time and Area Cost T. Tseng, C. Hou, J. Li - National Central University Bit Line Coupling Memory Tests for Single Cell Fails in SRAMs S. Irobi, Z. Al-ars, S. Hamdioui - Delft University of Technology Reducing Test Time and Area Overhead of an Embedded Memory Array Built-In Repair Analyzer with Optimal Repair Rate J. Chung, J. Park - The University of Texas at Austin, E. Byun, C. Woo - Samsung Electronics, J. Abraham - The University of Texas at Austin IP Session 1C: Innovative Practices in RF Test Organizer: R. Parekhji - Texas Instruments Moderator: TBA Test Time Reduction Using Parallel RF Test Techniques R.
    [Show full text]
  • PLM Industry Summary Editor: Christine Bennett Vol
    PLM Industry Summary Editor: Christine Bennett Vol. 11 No. 4 Friday 23 January 2009 Contents Acquisitions _______________________________________________________________________ 2 Autodesk Completes Acquisition of ALGOR, Inc. _____________________________________________2 Mentor Graphics Extends High Level Synthesis Leadership with Acquisition of Agility Design Solutions Inc. C Synthesis Suite ____________________________________________________________________3 Company News _____________________________________________________________________ 3 Anark Names Chris Garcia Senior Vice President, Business Development ___________________________3 Autodesk Manufacturing Community to Select 2008 Inventor of the Year Award Winner ______________4 Delcam Offers Free ArtCAM Demo Software for Artistic Users __________________________________5 DP signs Agreement with Italian Lathe Manufacturer GRAZIANO Tortona S.r.l. _____________________6 DP Technology Moves its Midwest Team to a Larger, New and Improved Site _______________________6 DP Technology Signs Agreement with Italian Machine-Tool Builder Salvadeo S.r.l. __________________7 Kalypso and Endeca Announce Partnership in Support of Engineering and PLM-Related Information Visibility Solutions ______________________________________________________________________7 New WorkXPlore 3D Website Allows Engineers to Download High Speed Collaborative CAD Viewer Free _____________________________________________________________________________________8 Si2’s Open Modeling Coalition Releases Document on Statistical
    [Show full text]
  • Case M.8125 - JAC / NEXPERIA
    EUROPEAN COMMISSION DG Competition Case M.8125 - JAC / NEXPERIA Only the English text is available and authentic. REGULATION (EC) No 139/2004 MERGER PROCEDURE Article 6(1)(b) NON-OPPOSITION Date: 12/10/2016 In electronic form on the EUR-Lex website under document number 32016M8125 EUROPEAN COMMISSION Brussels, 12.10.2016 C(2016) 6677 final PUBLIC VERSION SIMPLIFIED MERGER PROCEDURE To the notifying parties Dear Sirs, Subject: Case M.8125 - JAC / NEXPERIA Commission decision pursuant to Article 6(1)(b) of Council Regulation (EC) No 139/20041 and Article 57 of the Agreement on the European Economic Area2 1. On 13 September 2016, the European Commission received notification of a proposed concentration pursuant to Article 4 of the Merger Regulation by which the undertaking Beijing Jianguang Asset Management Co., Ltd. ("JAC", People's Republic of China), controlled by the China Investment Corporation (“CIC”, People's Republic of China), acquires within the meaning of Article 3(1)(b) of the Merger Regulation control of the standard products business unit (“Nexperia”) of NXP Semiconductors NV (“NXP”, the Netherlands) by way of purchase of shares.3 2. The business activities of the undertakings concerned are: − JAC is an investment management company which focuses its investments on mergers and acquisitions in the semiconductor industry. It is active in developing, manufacturing, and selling RF power transistors and bipolar based (power) diodes, thyristors and transistors. Its parent company, CIC, is a sovereign wealth fund of the People’s Republic of China, specialized in foreign exchange holdings. − Nexperia is active in the manufacturing and sale of semiconductors, in particular several types of logic integrated circuits ("ICs"), small signal transistors and diodes.
    [Show full text]
  • General Specification
    Crane Aerospace: 48.00.20,D,1: Production: Released: 07/26/2017: dtrivett mboulang scaswell REVISIONS APPLICATION REV DESCRIPTION REVIEWED DATE - Initial Revision D. TRIVETT 15/01/12 A Added paragraph to end of 3.4 D. TRIVETT 16/9/29 Added paragraph 3.10 B Added to paragraph 3.1, including NOTE D. TRIVETT 16/11/30 Added Section 3.1.2 Added to paragraph 3.3 Added Section 3.11 C Added paragraph 3.12 D. TRIVETT 17/06/22 D Revised paragragh 3.12 D. TRIVETT 17/07/24 GENERAL SPECIFICATION CONTRACT NUMBER REVISION STATUS N/A Active sheets: 1 through 6 All sheets are at revision D This document is computer-controlled by the TOLERANCES ARE: TITLE ELDEC Business System. Approval names for the LINEAR .XX = current revision are electronically printed on this .XXX = ENGINEERING DRAWING REQUIREMENTS, page. Original signatures for manually-controlled revisions are available upon request. ANGULAR = INTERPRETATION AND CLARIFICATION OF SIZE SCALE CAGE DRAWING NO. SHEET REV. A None 08748 48.00.20 1 of 10 D 2017/07/26 This document contains Technology controlled by the EAR. Diversion or use contrary to U.S. law is prohibited. ECCN: EAR99 Crane Aerospace: 48.00.20,D,1: Production: Released: 07/26/2017: dtrivett mboulang scaswell 1 SCOPE This specification establishes general and specific guidelines to aid in the interpretation and application of engineering drawings defining components, materials, or assemblies, whether purchased from suppliers or fabricated at Crane Aerospace & Electronics facilities. 1.1 Applicability This document applies to engineering drawings controlled by the Lynnwood site of Crane Aerospace & Electronics (CRANE), also referred to as ELDEC Corporation.
    [Show full text]
  • Selective GUIDE to LITERATURE CAN INTEGRATED CIRCUITS
    Engineering Literature Guides, Number 18 SELEcTivE GUIDE To LITERATURE CAN INTEGRATED CIRCUITS Compiled 1~y: Nestor L. 0sorio Northern Illinois University Libraries American Society for Engineering Education 1818 N Street, NW, Suite 600 Washington, DC 20036 Copyright (c) 1994 by American Society for Engineering Education 1818 N. Street, N.W., Suite 600 Washington, DC 20036-2479 International Standard Book Number: 0-87823-122-6 Library of Congress Catalog Card Number: Manufactured in the United States of America Beth L. Brin, Series Co-editor Science-Engineering Library University of Arizona Tucson, AZ 85721-001 Godlind Johnson, Series Co-editor Engineering Library SUNY-Stony Brook Stony Brook, NY 11794-2225 ASEE is not responsible for statements made or opinions expressed in this publication. TABLE OF CONTENTS Introduction... ....................................... ..................... .. ..... ............................ .. .. ......1 Bibliographies and Literature Guides . .. .. .. .2 Printed and Electronic Indexes and Abstracts . .3 Encyclopedias. : . .. ..6 Dictionaries . .. .. .. .7 Handbooks and Tables . .. .. .. .. .. .. .8 Directories: Product Information, Trade Catalogs . .. .. .. .10 Standards and Specifications . .. .13 Major Periodicals . .. .. .. .14 Major Proceedings . .. .. : . .. .. 17 Important Books . .. .. .19 Major. Integrated Circuit Manufacturers . .. .. ..20 Appendix: Selected Information Services . .. .. .. ..23 ~I INTRODUCTION ver the last 25 years significant changes have been 0 generated in industry by the
    [Show full text]