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PSMN3R7-30YLC N-Channel 30 V 3.95Mω Logic Level MOSFET in LFPAK Using Nextpower

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PSMN3R7-30YLC N-Channel 30 V 3.95Mω Logic Level MOSFET in LFPAK Using Nextpower Important notice Dear Customer, On 7 February 2017 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS semiconductors with its focus on the automotive, industrial, computing, consumer and wearable application markets In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below. Instead of http://www.nxp.com, http://www.philips.com/ or http://www.semiconductors.philips.com/, use http://www.nexperia.com Instead of [email protected] or [email protected], use [email protected] (email) Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on the version, as shown below: - © NXP N.V. (year). All rights reserved or © Koninklijke Philips Electronics N.V. (year). All rights reserved Should be replaced with: - © Nexperia B.V. (year). All rights reserved. If you have any questions related to the data sheet, please contact our nearest sales office via e-mail or telephone (details via [email protected]). Thank you for your cooperation and understanding, Kind regards, Team Nexperia PSMN3R7-30YLC LFPAK N-channel 30 V 3.95mΩ logic level MOSFET in LFPAK using NextPower technology Rev. 01 — 2 May 2011 Product data sheet 1. Product profile 1.1 General description Logic level enhancement mode N-channel MOSFET in LFPAK package. This product is designed and qualified for use in a wide range of industrial, communications and domestic equipment. 1.2 Features and benefits High reliability Power SO8 package, Optimised for 4.5V Gate drive utilising qualified to 175°C NextPower Superjunction technology Low parasitic inductance and Ultra low QG, QGD, and QOSS for resistance high system efficiencies at low and high loads 1.3 Applications DC-to-DC converters Server power supplies Load switching Sync rectifier Power OR-ing 1.4 Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage 25 °C ≤ Tj ≤ 175 °C - - 30 V ID drain current Tmb =25°C; VGS =10V; --100A see Figure 1 Ptot total power dissipation Tmb = 25 °C; see Figure 2 --79W Tj junction temperature -55 - 175 °C Static characteristics RDSon drain-source on-state VGS = 4.5 V; ID =20A; - 4.25 5.15 mΩ resistance Tj = 25 °C; see Figure 12 VGS =10V; ID =20A; - 3.3 3.95 mΩ Tj = 25 °C; see Figure 12 NXP Semiconductors PSMN3R7-30YLC N-channel 30 V 3.95mΩ logic level MOSFET in LFPAK using NextPower Table 1. Quick reference data …continued Symbol Parameter Conditions Min Typ Max Unit Dynamic characteristics QGD gate-drain charge VGS = 4.5 V; ID =20A; -4.2-nC VDS = 15 V; see Figure 14; see Figure 15 QG(tot) total gate charge VGS = 4.5 V; ID =20A; -14-nC VDS = 15 V; see Figure 14; see Figure 15 2. Pinning information Table 2. Pinning information Pin Symbol Description Simplified outline Graphic symbol 1Ssource mb D 2Ssource 3Ssource G 4 G gate mb D mounting base; connected to drain mbb076 S 1234 SOT669 (LFPAK; Power-SO8) 3. Ordering information Table 3. Ordering information Type number Package Name Description Version PSMN3R7-30YLC LFPAK; Power-SO8 plastic single-ended surface-mounted package; 4 leads SOT669 4. Marking Table 4. Marking codes Type number Marking code[1] PSMN3R7-30YLC 3C730L [1] % = placeholder for manufacturing site code PSMN3R7-30YLC All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 01 — 2 May 2011 2 of 15 NXP Semiconductors PSMN3R7-30YLC N-channel 30 V 3.95mΩ logic level MOSFET in LFPAK using NextPower 5. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage 25 °C ≤ Tj ≤ 175 °C - 30 V VDGR drain-gate voltage 25 °C ≤ Tj ≤ 175 °C; RGS =20kΩ -30V VGS gate-source voltage -20 20 V ID drain current VGS =10V; Tmb = 25 °C; see Figure 1 - 100 A VGS =10V; Tmb =100°C; see Figure 1 -74A IDM peak drain current pulsed; tp ≤ 10 µs; Tmb =25°C; - 419 A see Figure 4 Ptot total power dissipation Tmb = 25 °C; see Figure 2 -79W Tstg storage temperature -55 175 °C Tj junction temperature -55 175 °C Tsld(M) peak soldering temperature - 260 °C VESD electrostatic discharge voltage MM (JEDEC JESD22-A115) 350 - V Source-drain diode IS source current Tmb =25°C - 72 A ISM peak source current pulsed; tp ≤ 10 µs; Tmb = 25 °C - 419 A Avalanche ruggedness EDS(AL)S non-repetitive drain-source VGS =10V; Tj(init) =25°C; ID = 100 A; -28mJ avalanche energy Vsup ≤ 30 V; RGS =50Ω; unclamped; see Figure 3 003aaf677 03na19 120 120 ID (A) Pder (1) (%) 90 80 60 40 30 0 0 0 50 100 150 200 050 100 150 200 ° Tmb (°C) Tmb ( C) Fig 1. Continuous drain current as a function of Fig 2. Normalized total power dissipation as a mounting base temperature function of mounting base temperature PSMN3R7-30YLC All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 01 — 2 May 2011 3 of 15 NXP Semiconductors PSMN3R7-30YLC N-channel 30 V 3.95mΩ logic level MOSFET in LFPAK using NextPower 003aaf 691 103 IAL (A) 102 (1) 10 (2) 1 10-1 10-3 10-2 10-1 1 10 tAL (ms ) Fig 3. Single pulse avalanche rating; avalanche current as a function of avalanche time 003aaf678 104 ID (A) 103 Limit RDSon = VDS / ID 102 tp =10 μs 100 μs 10 DC 1 ms 10 ms 1 100 ms 10-1 10-1 1 10 102 VDS (V) Fig 4. Safe operating area; continuous and peak drain currents as a function of drain-source voltage PSMN3R7-30YLC All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 01 — 2 May 2011 4 of 15 NXP Semiconductors PSMN3R7-30YLC N-channel 30 V 3.95mΩ logic level MOSFET in LFPAK using NextPower 6. Thermal characteristics Table 6. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Rth(j-mb) thermal resistance from junction to mounting see Figure 5 - 1.72 1.9 K/W base 003aaf679 10 Zth(j-mb) (K/W) 1 δ = 0.5 0.2 0.1 tp -1 0.05 P δ = 10 T 0.02 single shot tp t T 10-2 1e-6 10-5 10-4 10-3 10-2 10-1 1 tp (s) Fig 5. Transient thermal impedance from junction to mounting base as a function of pulse duration PSMN3R7-30YLC All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 01 — 2 May 2011 5 of 15 NXP Semiconductors PSMN3R7-30YLC N-channel 30 V 3.95mΩ logic level MOSFET in LFPAK using NextPower 7. Characteristics Table 7. Characteristics Symbol Parameter Conditions Min Typ Max Unit Static characteristics V(BR)DSS drain-source breakdown ID = 250 µA; VGS =0V; Tj =25°C30--V voltage ID = 250 µA; VGS =0V; Tj =-55°C27--V VGS(th) gate-source threshold voltage ID =1mA; VDS =VGS; Tj =25°C; 1.05 1.58 1.95 V see Figure 10; see Figure 11 ID =10mA; VDS =VGS; Tj = 150 °C 0.5 - - V ID =1mA; VDS =VGS; Tj =-55°C--2.25V IDSS drain leakage current VDS =30V; VGS =0V; Tj =25°C--1µA VDS =30V; VGS =0V; Tj = 150 °C - - 100 µA IGSS gate leakage current VGS =16V; VDS =0V; Tj = 25 °C - - 100 nA VGS =-16V; VDS =0V; Tj = 25 °C - - 100 nA RDSon drain-source on-state VGS = 4.5 V; ID =20A; Tj =25°C; - 4.25 5.15 mΩ resistance see Figure 12 VGS = 4.5 V; ID =20A; Tj =150°C; --8.5mΩ see Figure 12; see Figure 13 VGS =10V; ID =20A; Tj =25°C; - 3.3 3.95 mΩ see Figure 12 VGS =10V; ID =20A; Tj =150°C; --6.55mΩ see Figure 12; see Figure 13 RG gate resistance f = 1 MHz - 1.6 3.2 Ω Dynamic characteristics QG(tot) total gate charge ID =20A; VDS =15V; VGS =10V; -29-nC see Figure 14; see Figure 15 ID =20A; VDS =15V; VGS =4.5V; -14-nC see Figure 14; see Figure 15 ID =0A; VDS =0V; VGS =10V - 27 - nC QGS gate-source charge ID =20A; VDS =15V; VGS =4.5V; -4.6-nC see Figure 14; see Figure 15 QGS(th) pre-threshold gate-source -2.9-nC charge QGS(th-pl) post-threshold gate-source -1.7-nC charge QGD gate-drain charge - 4.2 - nC VGS(pl) gate-source plateau voltage ID =20A; VDS = 15 V; see Figure 14; -2.8-V see Figure 15 Ciss input capacitance VDS =15V; VGS = 0 V; f = 1 MHz; - 1848 - pF Tj = 25 °C; see Figure 16 Coss output capacitance - 380 - pF Crss reverse transfer capacitance - 132 - pF td(on) turn-on delay time VDS =15V; RL =0.75Ω; VGS =4.5V; -21-ns RG(ext) =4.7Ω tr rise time - 19 - ns td(off) turn-off delay time - 30 - ns tf fall time - 12 - ns PSMN3R7-30YLC All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 01 — 2 May 2011 6 of 15 NXP Semiconductors PSMN3R7-30YLC N-channel 30 V 3.95mΩ logic level MOSFET in LFPAK using NextPower Table 7.
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