BUK9609-55A N-Channel Trenchmos Logic Level FET

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BUK9609-55A D2PAK N-channel TrenchMOS logic level FET Rev. 02 — 3 February 2011 Product data sheet

1. Product profile

1.1 General description Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. This product has been designed and qualified to the appropriate AEC standard for use in automotive critical applications.

1.2 Features and benefits

AEC Q101 compliant Suitable for logic level gate drive Low conduction losses due to low sources on-state resistance Suitable for thermally demanding environments due to 175 °C rating

1.3 Applications

12 V and 24 V loads Motors, lamps and solenoids Automotive and general purpose power switching

1.4 Quick reference data

Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit

VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - - 55 V [1] ID drain current VGS =5V; Tmb =25°C; --75A see Figure 1; see Figure 3

Ptot total power dissipation Tmb = 25 °C; see Figure 2 --211W Static characteristics

RDSon drain-source on-state VGS = 4.5 V; ID =25A; --10mΩ resistance Tj =25°C

VGS =10V; ID =25A; -6.48mΩ Tj =25°C

VGS =5V; ID =25A; -7.69mΩ Tj = 25 °C; see Figure 11; see Figure 12 NXP Semiconductors BUK9609-55A N-channel TrenchMOS logic level FET

Table 1. Quick reference data …continued Symbol Parameter Conditions Min Typ Max Unit Avalanche ruggedness

EDS(AL)S non-repetitive ID =75A; Vsup ≤ 55 V; --400mJ drain-source avalanche RGS =50Ω; VGS =5V; energy Tj(init) = 25 °C; unclamped Dynamic characteristics

QGD gate-drain charge VGS =5V; ID =25A; -29-nC VDS =44V; Tj =25°C; see Figure 13

[1] Continuous current is limited by package.

2. Pinning information

Table 2. Pinning information Pin Symbol Description Simplified outline Graphic symbol 1 G gate mb D 2 D drain[1] 3Ssource G mb D mounting base; connected to drain mbb076 S 2 13 SOT404 (D2PAK)

[1] It is not possible to make a connection to pin 2.

3. Ordering information

Table 3. Ordering information Type number Package Name Description Version BUK9609-55A D2PAK plastic single-ended surface-mounted package (D2PAK); 3 leads SOT404 (one lead cropped)

BUK9609-55A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 02 — 3 February 2011 2 of 14 NXP Semiconductors BUK9609-55A N-channel TrenchMOS logic level FET

4. Limiting values

Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit

VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - 55 V

VDGR drain-gate voltage RGS =20kΩ -55V

VGS gate-source voltage -15 15 V [1] ID drain current Tmb =25°C; VGS =5V; see Figure 1; see Figure 3 - 108 A [2] Tmb =100°C; VGS = 5 V; see Figure 1 -75A [2] Tmb =25°C; VGS =5V; see Figure 1; see Figure 3 -75A

IDM peak drain current Tmb = 25 °C; pulsed; tp ≤ 10 µs; see Figure 3 - 433 A

Ptot total power dissipation Tmb = 25 °C; see Figure 2 -211W

Tstg storage temperature -55 175 °C

Tj junction temperature -55 175 °C Source-drain diode [1] IS source current Tmb =25°C - 108 A [2] -75A

ISM peak source current pulsed; tp ≤ 10 µs; Tmb = 25 °C - 433 A Avalanche ruggedness

EDS(AL)S non-repetitive drain-source ID =75A; Vsup ≤ 55 V; RGS =50Ω; VGS =5V; - 400 mJ avalanche energy Tj(init) = 25 °C; unclamped

[1] Current is limited by power dissipation chip rating. [2] Continuous current is limited by package.

03nh27 03na19 120 120

ID Pder (A) (%)

80 80

40 capped at 75 A due to package 40

0 0 0 50 100 150 200 050 100 150 200 ° Tmb (°C) Tmb ( C)

Fig 1. Continuous drain current as a function of Fig 2. Normalized total power dissipation as a mounting base temperature function of mounting base temperature

BUK9609-55A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 02 — 3 February 2011 3 of 14 NXP Semiconductors BUK9609-55A N-channel TrenchMOS logic level FET

03nh25 103

Limit RDSon = VDS/ID ID (A) tp = 10 μs 102 100 μs

capped at 75 A due to package 1 ms DC 10 10 ms 100 ms

1 1 10 102 VDS (V)

Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage

BUK9609-55A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 02 — 3 February 2011 4 of 14 NXP Semiconductors BUK9609-55A N-channel TrenchMOS logic level FET

5. Thermal characteristics

Table 5. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit

Rth(j-mb) thermal resistance from junction to see Figure 4 --0.71K/W mounting base

Rth(j-a) thermal resistance from junction to mounted on a printed-circuit -50-K/W ambient board ; minimum footprint

03nh26 1

Zth(j-mb) (K/W) d = 0.5

− 0.2 10 1 0.1

0.05

0.02 tp −2 P δ = 10 T

single shot

tp t T 10−3 10−6 10−5 10−4 10−3 10−2 10−1 1 tp (s)

Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration

BUK9609-55A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 02 — 3 February 2011 5 of 14 NXP Semiconductors BUK9609-55A N-channel TrenchMOS logic level FET

6. Characteristics

Table 6. Characteristics Symbol Parameter Conditions Min Typ Max Unit Static characteristics

V(BR)DSS drain-source breakdown ID =0.25mA; VGS =0V; Tj = -55 °C 50 - - V voltage ID =0.25mA; VGS =0V; Tj =25°C55--V

VGS(th) gate-source threshold voltage ID =1mA; VDS =VGS; Tj =-55°C; --2.3V see Figure 10

ID =1mA; VDS =VGS; Tj =25°C; 11.52V see Figure 10

ID =1mA; VDS =VGS; Tj = 175 °C; 0.5--V see Figure 10

IDSS drain leakage current VDS =55V; VGS =0V; Tj = 175 °C - - 500 µA

VDS =55V; VGS =0V; Tj = 25 °C - 0.05 10 µA

IGSS gate leakage current VGS =10V; VDS =0V; Tj = 25 °C - 2 100 nA

VGS =-10V; VDS =0V; Tj = 25 °C - 2 100 nA

RDSon drain-source on-state VGS =4.5V; ID =25A; Tj =25°C--10mΩ resistance VGS =5V; ID =25A; Tj = 175 °C; --18mΩ see Figure 11; see Figure 12

VGS =10V; ID =25A; Tj =25°C - 6.4 8 mΩ

VGS =5V; ID =25A; Tj =25°C; -7.69mΩ see Figure 11; see Figure 12 Dynamic characteristics

QG(tot) total gate charge ID =25A; VDS =44V; VGS =5V; -60-nC Tj =25°C; see Figure 13 QGS gate-source charge - 9 - nC

QGD gate-drain charge - 29 - nC

Ciss input capacitance VGS =0V; VDS =25V; f=1MHz; - 3475 4633 pF Tj =25°C; see Figure 14 Coss output capacitance - 570 682 pF

Crss reverse transfer capacitance - 360 493 pF

td(on) turn-on delay time VDS =30V; RL =1.2Ω; VGS =5V; -33-ns RG(ext) =10Ω; Tj =25°C tr rise time - 149 - ns

td(off) turn-off delay time - 197 - ns

tf fall time - 131 - ns

LD internal drain inductance from drain lead 6 mm from package -4.5-nH to centre of die ; Tj =25°C from upper edge of drain mounting -2.5-nH base to centre of die ; Tj =25°C

LS internal source inductance from source lead to source bond -7.5-nH pad ; Tj =25°C Source-drain diode

VSD source-drain voltage IS =25A; VGS =0V; Tj =25°C; - 0.85 1.2 V see Figure 15

trr reverse recovery time IS =25A; dIS/dt = -100 A/µs; -70-ns VGS =-10V; VDS =25V; Tj =25°C Qr recovered charge - 160 - nC

BUK9609-55A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 02 — 3 February 2011 6 of 14 NXP Semiconductors BUK9609-55A N-channel TrenchMOS logic level FET

03nh64 03nh63 300 11 10 label is VGS (V) 5 I RDSon D 4.8 4.6 (A) (mΩ) 4.4 4.2 200 9 4 3.8 3.6 3.4 100 3.2 7 3 2.8 2.6 2.4 2.2 0 5 0246810 0 5 10 15 VDS (V) VGS (V)

Fig 5. Output characteristics: drain current as a Fig 6. Drain-source on-state resistance as a function function of drain-source voltage; typical values of gate-source voltage; typical values

03aa36 03nh61 10-1 100

ID gfs (A) (S) 10-2 75

10-3 min typ max 50

10-4

25 10-5

10-6 0 0123 0204060 VGS (V) ID (A)

Fig 7. Sub-threshold drain current as a function of Fig 8. Forward transconductance as a function of gate-source voltage drain current; typical values

BUK9609-55A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 02 — 3 February 2011 7 of 14 NXP Semiconductors BUK9609-55A N-channel TrenchMOS logic level FET

03nh62 03aa33 120 2.5

VGS(th) ID (V) (A) 2 max

80 1.5 typ

1 min 40

175 °C Tj = 25 °C 0.5

0 0 01234 -60 0 60 120 180 VGS (V) Tj (°C)

Fig 9. Transfer characteristics: drain current as a Fig 10. Gate-source threshold voltage as a function of function of gate-source voltage; typical values junction temperature

03nh65 03ne89 25 2

RDSon a (mΩ) VGS = 3 V 3.6 V 4 V 20 1.5 3.2 V 3.4 V

5 V 15 1

10 V

10 0.5

5 0 0 100 200 300 -60 0 60 120 180 T (°C) ID (A) j

Fig 11. Drain-source on-state resistance as a function Fig 12. Normalized drain-source on-state resistance of drain current; typical values factor as a function of junction temperature

BUK9609-55A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 02 — 3 February 2011 8 of 14 NXP Semiconductors BUK9609-55A N-channel TrenchMOS logic level FET

03nh60 03nh66 5 9000 VGS (V) C Ciss 4 (pF) Coss

VDD = 14 V 44 V 6000 3 Crss

2 3000

0 0 0204060 10−2 10−1 1 10 102 QG (nC) VDS (V)

Fig 13. Gate-source voltage as a function of turn-on Fig 14. Input, output and reverse transfer capacitances gate charge; typical values as a function of drain-source voltage; typical values

03nh59 100

IS (A)

25 175 °C Tj = 25 °C

0 0.0 0.3 0.6 0.9 1.2 VSD (V)

Fig 15. Reverse diode current as a function of reverse diode voltage; typical values

BUK9609-55A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 02 — 3 February 2011 9 of 14 NXP Semiconductors BUK9609-55A N-channel TrenchMOS logic level FET

7. Package outline

Plastic single-ended surface-mounted package (D2PAK); 3 leads (one lead cropped) SOT404

E A1

mounting D1 base

Lp 13

b c

e e Q

0 2.5 5 mm

scale

DIMENSIONS (mm are the original dimensions) D UNIT A A b c D E eL H Q 1 max. 1 p D

mm 4.50 1.40 0.85 0.64 11 1.60 10.30 2.54 2.90 15.80 2.60 4.10 1.27 0.60 0.46 1.20 9.70 2.10 14.80 2.20

OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 05-02-11 SOT404 06-03-16

Fig 16. Package outline SOT404 (D2PAK)

BUK9609-55A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 02 — 3 February 2011 10 of 14 NXP Semiconductors BUK9609-55A N-channel TrenchMOS logic level FET

8. Revision history

Table 7. Revision history Document ID Release date Data sheet status Change notice Supersedes BUK9609-55A v.2 20110203 Product data sheet - BUK95_9609_55A v.1 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Type number BUK9609-55A separated from data sheet BUK95_9609_55A v.1. BUK95_9609_55A v.1 20020221 Product data - -

BUK9609-55A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 02 — 3 February 2011 11 of 14 NXP Semiconductors BUK9609-55A N-channel TrenchMOS logic level FET

9. Legal information

9.1 Data sheet status

Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

9.2 Definitions Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive Draft — The document is a draft version only. The content is still under applications. The product is not designed, authorized or warranted to be internal review and subject to formal approval, which may result in suitable for use in medical, military, aircraft, space or life support equipment, modifications or additions. NXP Semiconductors does not give any nor in applications where failure or malfunction of an NXP Semiconductors representations or warranties as to the accuracy or completeness of product can reasonably be expected to result in personal injury, death or information included herein and shall have no liability for the consequences of severe property or environmental damage. NXP Semiconductors accepts no use of such information. liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the Short data sheet — A short data sheet is an extract from a full data sheet customer’s own risk. with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and Quick reference data — The Quick reference data is an extract of the full information. For detailed and full information see the relevant full data product data given in the Limiting values and Characteristics sections of this sheet, which is available on request via the local NXP Semiconductors sales document, and as such is not complete, exhaustive or legally binding. office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no Product specification — The information and data provided in a Product representation or warranty that such applications will be suitable for the data sheet shall define the specification of the product as agreed between specified use without further testing or modification. NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, Customers are responsible for the design and operation of their applications shall an agreement be valid in which the NXP Semiconductors product is and products using NXP Semiconductors products, and NXP Semiconductors deemed to offer functions and qualities beyond those described in the accepts no liability for any assistance with applications or customer product Product data sheet. design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of 9.3 Disclaimers customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their Limited warranty and liability — Information in this document is believed to applications and products. be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or NXP Semiconductors does not accept any liability related to any default, completeness of such information and shall have no liability for the damage, costs or problem which is based on any weakness or default in the consequences of use of such information. customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary In no event shall NXP Semiconductors be liable for any indirect, incidental, testing for the customer’s applications and products using NXP punitive, special or consequential damages (including - without limitation - lost Semiconductors products in order to avoid a default of the applications and profits, lost savings, business interruption, costs related to the removal or the products or of the application or use by customer’s third party replacement of any products or rework charges) whether or not such customer(s). NXP does not accept any liability in this respect. damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent Notwithstanding any damages that customer might incur for any reason damage to the device. Limiting values are stress ratings only and (proper) whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards operation of the device at these or any other conditions above those given in customer for the products described herein shall be limited in accordance the Recommended operating conditions section (if present) or the with the Terms and conditions of commercial sale of NXP Semiconductors. Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect Right to make changes — NXP Semiconductors reserves the right to make the quality and reliability of the device. changes to information published in this document, including without limitation specifications and product descriptions, at any time and without Terms and conditions of commercial sale — NXP Semiconductors notice. This document supersedes and replaces all information supplied prior products are sold subject to the general terms and conditions of commercial to the publication hereof. sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual

BUK9609-55A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 02 — 3 February 2011 12 of 14 NXP Semiconductors BUK9609-55A N-channel TrenchMOS logic level FET agreement is concluded only the terms and conditions of the respective 9.4 Trademarks agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the Notice: All referenced brands, product names, service names and trademarks purchase of NXP Semiconductors products by customer. are the property of their respective owners.

No offer to sell or license — Nothing in this document may be interpreted or Adelante, Bitport, Bitsound, CoolFlux, CoReUse, DESFire, EZ-HV, construed as an offer to sell products that is open for acceptance or the grant, FabKey, GreenChip, HiPerSmart, HITAG, I²C-bus logo, ICODE, I-CODE, conveyance or implication of any license under any copyrights, patents or ITEC, Labelution, MIFARE, MIFARE Plus, MIFARE Ultralight, MoReUse, other industrial or intellectual property rights. QLPAK, Silicon Tuner, SiliconMAX, SmartXA, STARplug, TOPFET, TrenchMOS, TriMedia and UCODE — are trademarks of NXP B.V. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior HD Radio and HD Radio logo — are trademarks of iBiquity Digital authorization from national authorities. Corporation.

10. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: [email protected]

BUK9609-55A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 02 — 3 February 2011 13 of 14 NXP Semiconductors BUK9609-55A N-channel TrenchMOS logic level FET

11. Contents

1 Product profile ...... 1 1.1 General description ...... 1 1.2 Features and benefits...... 1 1.3 Applications ...... 1 1.4 Quick reference data ...... 1 2 Pinning information...... 2 3 Ordering information...... 2 4 Limiting values...... 3 5 Thermal characteristics ...... 5 6 Characteristics...... 6 7 Package outline ...... 10 8 Revision history...... 11 9 Legal information...... 12 9.1 Data sheet status ...... 12 9.2 Definitions...... 12 9.3 Disclaimers ...... 12 9.4 Trademarks...... 13 10 Contact information...... 13

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.

© NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 3 February 2011 Document identifier: BUK9609-55A