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BUK9609-55A N-Channel Trenchmos Logic Level FET

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BUK9609-55A N-Channel Trenchmos Logic Level FET Important notice Dear Customer, On 7 February 2017 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS semiconductors with its focus on the automotive, industrial, computing, consumer and wearable application markets In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below. Instead of http://www.nxp.com, http://www.philips.com/ or http://www.semiconductors.philips.com/, use http://www.nexperia.com Instead of [email protected] or [email protected], use [email protected] (email) Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on the version, as shown below: - © NXP N.V. (year). All rights reserved or © Koninklijke Philips Electronics N.V. (year). All rights reserved Should be replaced with: - © Nexperia B.V. (year). All rights reserved. If you have any questions related to the data sheet, please contact our nearest sales office via e-mail or telephone (details via [email protected]). Thank you for your cooperation and understanding, Kind regards, Team Nexperia BUK9609-55A D2PAK N-channel TrenchMOS logic level FET Rev. 02 — 3 February 2011 Product data sheet 1. Product profile 1.1 General description Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. This product has been designed and qualified to the appropriate AEC standard for use in automotive critical applications. 1.2 Features and benefits AEC Q101 compliant Suitable for logic level gate drive Low conduction losses due to low sources on-state resistance Suitable for thermally demanding environments due to 175 °C rating 1.3 Applications 12 V and 24 V loads Motors, lamps and solenoids Automotive and general purpose power switching 1.4 Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - - 55 V [1] ID drain current VGS =5V; Tmb =25°C; --75A see Figure 1; see Figure 3 Ptot total power dissipation Tmb = 25 °C; see Figure 2 --211W Static characteristics RDSon drain-source on-state VGS = 4.5 V; ID =25A; --10mΩ resistance Tj =25°C VGS =10V; ID =25A; -6.48mΩ Tj =25°C VGS =5V; ID =25A; -7.69mΩ Tj = 25 °C; see Figure 11; see Figure 12 NXP Semiconductors BUK9609-55A N-channel TrenchMOS logic level FET Table 1. Quick reference data …continued Symbol Parameter Conditions Min Typ Max Unit Avalanche ruggedness EDS(AL)S non-repetitive ID =75A; Vsup ≤ 55 V; --400mJ drain-source avalanche RGS =50Ω; VGS =5V; energy Tj(init) = 25 °C; unclamped Dynamic characteristics QGD gate-drain charge VGS =5V; ID =25A; -29-nC VDS =44V; Tj =25°C; see Figure 13 [1] Continuous current is limited by package. 2. Pinning information Table 2. Pinning information Pin Symbol Description Simplified outline Graphic symbol 1 G gate mb D 2 D drain[1] 3Ssource G mb D mounting base; connected to drain mbb076 S 2 13 SOT404 (D2PAK) [1] It is not possible to make a connection to pin 2. 3. Ordering information Table 3. Ordering information Type number Package Name Description Version BUK9609-55A D2PAK plastic single-ended surface-mounted package (D2PAK); 3 leads SOT404 (one lead cropped) BUK9609-55A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 02 — 3 February 2011 2 of 14 NXP Semiconductors BUK9609-55A N-channel TrenchMOS logic level FET 4. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - 55 V VDGR drain-gate voltage RGS =20kΩ -55V VGS gate-source voltage -15 15 V [1] ID drain current Tmb =25°C; VGS =5V; see Figure 1; see Figure 3 - 108 A [2] Tmb =100°C; VGS = 5 V; see Figure 1 -75A [2] Tmb =25°C; VGS =5V; see Figure 1; see Figure 3 -75A IDM peak drain current Tmb = 25 °C; pulsed; tp ≤ 10 µs; see Figure 3 - 433 A Ptot total power dissipation Tmb = 25 °C; see Figure 2 -211W Tstg storage temperature -55 175 °C Tj junction temperature -55 175 °C Source-drain diode [1] IS source current Tmb =25°C - 108 A [2] -75A ISM peak source current pulsed; tp ≤ 10 µs; Tmb = 25 °C - 433 A Avalanche ruggedness EDS(AL)S non-repetitive drain-source ID =75A; Vsup ≤ 55 V; RGS =50Ω; VGS =5V; - 400 mJ avalanche energy Tj(init) = 25 °C; unclamped [1] Current is limited by power dissipation chip rating. [2] Continuous current is limited by package. 03nh27 03na19 120 120 ID Pder (A) (%) 80 80 40 capped at 75 A due to package 40 0 0 0 50 100 150 200 050 100 150 200 ° Tmb (°C) Tmb ( C) Fig 1. Continuous drain current as a function of Fig 2. Normalized total power dissipation as a mounting base temperature function of mounting base temperature BUK9609-55A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 02 — 3 February 2011 3 of 14 NXP Semiconductors BUK9609-55A N-channel TrenchMOS logic level FET 03nh25 103 Limit RDSon = VDS/ID ID (A) tp = 10 μs 102 100 μs capped at 75 A due to package 1 ms DC 10 10 ms 100 ms 1 1 10 102 VDS (V) Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage BUK9609-55A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 02 — 3 February 2011 4 of 14 NXP Semiconductors BUK9609-55A N-channel TrenchMOS logic level FET 5. Thermal characteristics Table 5. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Rth(j-mb) thermal resistance from junction to see Figure 4 --0.71K/W mounting base Rth(j-a) thermal resistance from junction to mounted on a printed-circuit -50-K/W ambient board ; minimum footprint 03nh26 1 Zth(j-mb) (K/W) d = 0.5 − 0.2 10 1 0.1 0.05 0.02 tp −2 P δ = 10 T single shot tp t T 10−3 10−6 10−5 10−4 10−3 10−2 10−1 1 tp (s) Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration BUK9609-55A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 02 — 3 February 2011 5 of 14 NXP Semiconductors BUK9609-55A N-channel TrenchMOS logic level FET 6. Characteristics Table 6. Characteristics Symbol Parameter Conditions Min Typ Max Unit Static characteristics V(BR)DSS drain-source breakdown ID =0.25mA; VGS =0V; Tj = -55 °C 50 - - V voltage ID =0.25mA; VGS =0V; Tj =25°C55--V VGS(th) gate-source threshold voltage ID =1mA; VDS =VGS; Tj =-55°C; --2.3V see Figure 10 ID =1mA; VDS =VGS; Tj =25°C; 11.52V see Figure 10 ID =1mA; VDS =VGS; Tj = 175 °C; 0.5--V see Figure 10 IDSS drain leakage current VDS =55V; VGS =0V; Tj = 175 °C - - 500 µA VDS =55V; VGS =0V; Tj = 25 °C - 0.05 10 µA IGSS gate leakage current VGS =10V; VDS =0V; Tj = 25 °C - 2 100 nA VGS =-10V; VDS =0V; Tj = 25 °C - 2 100 nA RDSon drain-source on-state VGS =4.5V; ID =25A; Tj =25°C--10mΩ resistance VGS =5V; ID =25A; Tj = 175 °C; --18mΩ see Figure 11; see Figure 12 VGS =10V; ID =25A; Tj =25°C - 6.4 8 mΩ VGS =5V; ID =25A; Tj =25°C; -7.69mΩ see Figure 11; see Figure 12 Dynamic characteristics QG(tot) total gate charge ID =25A; VDS =44V; VGS =5V; -60-nC Tj =25°C; see Figure 13 QGS gate-source charge - 9 - nC QGD gate-drain charge - 29 - nC Ciss input capacitance VGS =0V; VDS =25V; f=1MHz; - 3475 4633 pF Tj =25°C; see Figure 14 Coss output capacitance - 570 682 pF Crss reverse transfer capacitance - 360 493 pF td(on) turn-on delay time VDS =30V; RL =1.2Ω; VGS =5V; -33-ns RG(ext) =10Ω; Tj =25°C tr rise time - 149 - ns td(off) turn-off delay time - 197 - ns tf fall time - 131 - ns LD internal drain inductance from drain lead 6 mm from package -4.5-nH to centre of die ; Tj =25°C from upper edge of drain mounting -2.5-nH base to centre of die ; Tj =25°C LS internal source inductance from source lead to source bond -7.5-nH pad ; Tj =25°C Source-drain diode VSD source-drain voltage IS =25A; VGS =0V; Tj =25°C; - 0.85 1.2 V see Figure 15 trr reverse recovery time IS =25A; dIS/dt = -100 A/µs; -70-ns VGS =-10V; VDS =25V; Tj =25°C Qr recovered charge - 160 - nC BUK9609-55A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 02 — 3 February 2011 6 of 14 NXP Semiconductors BUK9609-55A N-channel TrenchMOS logic level FET 03nh64 03nh63 300 11 10 label is VGS (V) 5 I RDSon D 4.8 4.6 (A) (mΩ) 4.4 4.2 200 9 4 3.8 3.6 3.4 100 3.2 7 3 2.8 2.6 2.4 2.2 0 5 0246810 0 5 10 15 VDS (V) VGS (V) Fig 5.
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