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PSMN8R0-30YL N-Channel 8.3 Mω 30 V Trenchmos Logic Level FET in LFPAK

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PSMN8R0-30YL N-Channel 8.3 Mω 30 V Trenchmos Logic Level FET in LFPAK Important notice Dear Customer, On 7 February 2017 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS semiconductors with its focus on the automotive, industrial, computing, consumer and wearable application markets In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below. Instead of http://www.nxp.com, http://www.philips.com/ or http://www.semiconductors.philips.com/, use http://www.nexperia.com Instead of [email protected] or [email protected], use [email protected] (email) Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on the version, as shown below: - © NXP N.V. (year). All rights reserved or © Koninklijke Philips Electronics N.V. (year). All rights reserved Should be replaced with: - © Nexperia B.V. (year). All rights reserved. If you have any questions related to the data sheet, please contact our nearest sales office via e-mail or telephone (details via [email protected]). Thank you for your cooperation and understanding, Kind regards, Team Nexperia PSMN8R0-30YL LFPAK N-channel 8.3 mΩ 30 V TrenchMOS logic level FET in LFPAK Rev. 2 — 16 May 2011 Product data sheet 1. Product profile 1.1 General description Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. This product is designed and qualified for use in industrial and communications applications. 1.2 Features and benefits High efficiency due to low switching Suitable for logic level gate drive and conduction losses sources 1.3 Applications Class-D amplifiers Motor control DC-to-DC converters Server power supplies 1.4 Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VDS drain-source Tj ≥ 25 °C; Tj ≤ 175°C --30V voltage ID drain current Tmb =25°C; VGS =10V; --62A see Figure 1 Ptot total power Tmb = 25 °C; see Figure 2 --56W dissipation Static characteristics RDSon drain-source VGS =10V; ID =15A; Tj =25°C - 6.9 8.3 mΩ on-state resistance Dynamic characteristics QGD gate-drain charge VGS =10V; ID =45A; VDS =15V; -4-nC see Figure 14; see Figure 15 QG(tot) total gate charge VGS =4.5V; ID =45A; VDS =15V; -9-nC see Figure 14; see Figure 15 Avalanche ruggedness EDS(AL)S non-repetitive VGS =10V; Tj(init) =25°C; --21mJ drain-source ID =62A; Vsup ≤ 30 V; RGS =50Ω; avalanche energy unclamped NXP Semiconductors PSMN8R0-30YL N-channel 8.3 mΩ 30 V TrenchMOS logic level FET in LFPAK 2. Pinning information Table 2. Pinning information Pin Symbol Description Simplified outline Graphic symbol 1Ssource mb D 2Ssource 3Ssource G 4 G gate mb D mounting base; connected to drain mbb076 S 1234 SOT669 (LFPAK; Power-SO8) 3. Ordering information Table 3. Ordering information Type number Package Name Description Version PSMN8R0-30YL LFPAK; Power-SO8 plastic single-ended surface-mounted package; 4 leads SOT669 4. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - 30 V VDSM peak drain-source voltage tp ≤ 25 ns; f ≤ 500 kHz; EDS(AL) ≤ 70 nJ; pulsed - 35 V VDGR drain-gate voltage Tj ≥ 25 °C; Tj ≤ 175 °C; RGS =20kΩ -30V VGS gate-source voltage -20 20 V ID drain current VGS =10V; Tmb = 100 °C; see Figure 1 -44A VGS =10V; Tmb =25°C; see Figure 1 -62A IDM peak drain current pulsed; tp ≤ 10 µs; Tmb =25°C; see Figure 3 - 247 A Ptot total power dissipation Tmb =25°C; see Figure 2 -56W Tstg storage temperature -55 175 °C Tj junction temperature -55 175 °C Source-drain diode IS source current Tmb =25°C - 62 A ISM peak source current pulsed; tp ≤ 10 µs; Tmb = 25 °C - 247 A Avalanche ruggedness EDS(AL)S non-repetitive drain-source VGS =10V; Tj(init) =25°C; ID =62A; -21mJ avalanche energy Vsup ≤ 30 V; RGS =50Ω; unclamped PSMN8R0-30YL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 16 May 2011 2 of 14 NXP Semiconductors PSMN8R0-30YL N-channel 8.3 mΩ 30 V TrenchMOS logic level FET in LFPAK 003aaf418 03aa16 80 120 ID (A) Pder (%) 60 80 40 40 20 0 0 0 50 100 150 200 050 100 150 200 ° Tmb ( C) Tmb (°C) Fig 1. Continuous drain current as a function of Fig 2. Normalized total power dissipation as a mounting base temperature function of mounting base temperature 003aaf419 103 ID (A) Limit RDSon = VDS / ID 102 μ tp =10 s 100 μs 10 1 ms DC 10 ms 1 100 ms 10-1 10-1 1 10 102 V DS (V) Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage PSMN8R0-30YL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 16 May 2011 3 of 14 NXP Semiconductors PSMN8R0-30YL N-channel 8.3 mΩ 30 V TrenchMOS logic level FET in LFPAK 5. Thermal characteristics Table 5. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Rth(j-mb) thermal resistance from junction to mounting base see Figure 4 - 1.35 2.7 K/W 003aaf420 10 Zth(j-mb) (K/W) 1 δ = 0.5 0.2 0.1 P δ = tp 10-1 0.05 T 0.02 single shot tp t T 10-2 10-6 10-5 10-4 10-3 10-2 10-1 1 tp (s) Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration PSMN8R0-30YL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 16 May 2011 4 of 14 NXP Semiconductors PSMN8R0-30YL N-channel 8.3 mΩ 30 V TrenchMOS logic level FET in LFPAK 6. Characteristics Table 6. Characteristics Tested to JEDEC standards where applicable. Symbol Parameter Conditions Min Typ Max Unit Static characteristics V(BR)DSS drain-source breakdown ID = 250 µA; VGS =0V; Tj =25°C30--V voltage ID = 250 µA; VGS =0V; Tj = -55 °C 27 - - V VGS(th) gate-source threshold voltage ID =1mA; VDS =VGS; Tj =25°C; 1.3 1.7 2.15 V see Figure 11; see Figure 12 ID =1mA; VDS =VGS; Tj =150°C; 0.5--V see Figure 12 ID =1mA; VDS =VGS; Tj =-55°C; --2.55V see Figure 12 IDSS drain leakage current VDS =30V; VGS =0V; Tj = 25 °C - 0.02 1 µA VDS =30V; VGS =0V; Tj = 150 °C - - 100 µA IGSS gate leakage current VGS =16V; VDS =0V; Tj = 25 °C - 10 100 nA VGS =-16V; VDS =0V; Tj = 25 °C - 10 100 nA RDSon drain-source on-state VGS =4.5V; ID =15A; Tj = 25 °C - 10.4 12.2 mΩ resistance VGS =10V; ID =15A; Tj =150°C; --15mΩ see Figure 13 VGS =10V; ID =15A; Tj =25°C - 6.9 8.3 mΩ RG gate resistance f = 1 MHz - 2.03 - Ω Dynamic characteristics QG(tot) total gate charge ID =45A; VDS =15V; VGS =4.5V; -9-nC see Figure 14; see Figure 15 ID =45A; VDS =15V; VGS =10V; - 18.3 - nC see Figure 14; see Figure 15 ID =0A; VDS =0V; VGS = 10 V - 16.1 - nC QGS gate-source charge ID =45A; VDS =15V; VGS =10V; -2.7-nC see Figure 14; see Figure 15 QGS(th) pre-threshold gate-source -1.5-nC charge QGS(th-pl) post-threshold gate-source -1.2-nC charge QGD gate-drain charge - 4 - nC VGS(pl) gate-source plateau voltage VDS = 15 V; see Figure 14; -3.2-V see Figure 15 Ciss input capacitance VDS =15V; VGS =0V; f=1MHz; - 1005 - pF Tj =25°C; see Figure 17 Coss output capacitance - 200 - pF Crss reverse transfer capacitance - 102 - pF td(on) turn-on delay time VDS =15V; RL =0.5Ω; VGS =4.5V; -15-ns RG(ext) =4.7Ω tr rise time - 29 - ns td(off) turn-off delay time - 21 - ns tf fall time VDS =15V; RL =0.5Ω; VGS =4.5V; -8-ns RG(ext) =4.7Ω PSMN8R0-30YL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 16 May 2011 5 of 14 NXP Semiconductors PSMN8R0-30YL N-channel 8.3 mΩ 30 V TrenchMOS logic level FET in LFPAK Table 6. Characteristics …continued Tested to JEDEC standards where applicable. Symbol Parameter Conditions Min Typ Max Unit Source-drain diode VSD source-drain voltage IS =25A; VGS =0V; Tj =25°C; -0.91.2V see Figure 16 trr reverse recovery time IS =15A; dIS/dt = -100 A/µs; -34-ns VGS =0V; VDS =15V Qr recovered charge - 30 - nC 003aaf421 003aaf422 80 60 VGS (V) = 10 4.5 ID ID (A) (A) 60 3.5 45 40 30 3.0 ° ° Tj = 150 C Tj = 25 C 2.8 20 15 2.6 2.4 0 0 0 0.5 1 1.5 2 012345 V (V) DS VGS (V) Fig 5. Output characteristics: drain current as a Fig 6. Transfer characteristics: drain current as a function of drain-source voltage; typical values function of gate-source voltage; typical values 003aaf423 003aaf424 60 2000 gfs C (S) (pF) Ciss 45 1500 Crss 30 1000 15 500 0 0 015304560 036912 I (A) D VGS (V) Fig 7.
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