PSMN8R0-30YL N-Channel 8.3 Mω 30 V Trenchmos Logic Level FET in LFPAK

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PSMN8R0-30YL

LFPAK N-channel 8.3 mΩ 30 V TrenchMOS logic level FET in LFPAK Rev. 2 — 16 May 2011 Product data sheet

1. Product profile

1.1 General description Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. This product is designed and qualified for use in industrial and communications applications.

1.2 Features and benefits

High efficiency due to low switching Suitable for logic level gate drive and conduction losses sources

1.3 Applications

Class-D amplifiers Motor control DC-to-DC converters Server power supplies

1.4 Quick reference data

Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit

VDS drain-source Tj ≥ 25 °C; Tj ≤ 175°C --30V voltage

ID drain current Tmb =25°C; VGS =10V; --62A see Figure 1

Ptot total power Tmb = 25 °C; see Figure 2 --56W dissipation Static characteristics

RDSon drain-source VGS =10V; ID =15A; Tj =25°C - 6.9 8.3 mΩ on-state resistance Dynamic characteristics

QGD gate-drain charge VGS =10V; ID =45A; VDS =15V; -4-nC see Figure 14; see Figure 15

QG(tot) total gate charge VGS =4.5V; ID =45A; VDS =15V; -9-nC see Figure 14; see Figure 15 Avalanche ruggedness

EDS(AL)S non-repetitive VGS =10V; Tj(init) =25°C; --21mJ drain-source ID =62A; Vsup ≤ 30 V; RGS =50Ω; avalanche energy unclamped NXP Semiconductors PSMN8R0-30YL N-channel 8.3 mΩ 30 V TrenchMOS logic level FET in LFPAK

2. Pinning information

Table 2. Pinning information Pin Symbol Description Simplified outline Graphic symbol 1Ssource mb D 2Ssource 3Ssource G 4 G gate mb D mounting base; connected to drain mbb076 S 1234 SOT669 (LFPAK; Power-SO8)

3. Ordering information

Table 3. Ordering information Type number Package Name Description Version PSMN8R0-30YL LFPAK; Power-SO8 plastic single-ended surface-mounted package; 4 leads SOT669

4. Limiting values

Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit

VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - 30 V

VDSM peak drain-source voltage tp ≤ 25 ns; f ≤ 500 kHz; EDS(AL) ≤ 70 nJ; pulsed - 35 V

VDGR drain-gate voltage Tj ≥ 25 °C; Tj ≤ 175 °C; RGS =20kΩ -30V

VGS gate-source voltage -20 20 V

ID drain current VGS =10V; Tmb = 100 °C; see Figure 1 -44A

VGS =10V; Tmb =25°C; see Figure 1 -62A

IDM peak drain current pulsed; tp ≤ 10 µs; Tmb =25°C; see Figure 3 - 247 A

Ptot total power dissipation Tmb =25°C; see Figure 2 -56W

Tstg storage temperature -55 175 °C

Tj junction temperature -55 175 °C Source-drain diode

IS source current Tmb =25°C - 62 A

ISM peak source current pulsed; tp ≤ 10 µs; Tmb = 25 °C - 247 A Avalanche ruggedness

EDS(AL)S non-repetitive drain-source VGS =10V; Tj(init) =25°C; ID =62A; -21mJ avalanche energy Vsup ≤ 30 V; RGS =50Ω; unclamped

PSMN8R0-30YL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 16 May 2011 2 of 14 NXP Semiconductors PSMN8R0-30YL N-channel 8.3 mΩ 30 V TrenchMOS logic level FET in LFPAK

003aaf418 03aa16 80 120

ID (A) Pder (%) 60 80

40 20

0 0 0 50 100 150 200 050 100 150 200 ° Tmb ( C) Tmb (°C)

Fig 1. Continuous drain current as a function of Fig 2. Normalized total power dissipation as a mounting base temperature function of mounting base temperature

003aaf419 103

ID (A) Limit RDSon = VDS / ID 102 μ tp =10 s

100 μs 10

1 ms

DC 10 ms 1 100 ms

10-1 10-1 1 10 102 V DS (V)

Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage

PSMN8R0-30YL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 16 May 2011 3 of 14 NXP Semiconductors PSMN8R0-30YL N-channel 8.3 mΩ 30 V TrenchMOS logic level FET in LFPAK

5. Thermal characteristics

Table 5. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit

Rth(j-mb) thermal resistance from junction to mounting base see Figure 4 - 1.35 2.7 K/W

003aaf420 10

Zth(j-mb) (K/W)

1 δ = 0.5

0.2

0.1 P δ = tp 10-1 0.05 T 0.02 single shot tp t T 10-2 10-6 10-5 10-4 10-3 10-2 10-1 1 tp (s)

Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration

PSMN8R0-30YL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 16 May 2011 4 of 14 NXP Semiconductors PSMN8R0-30YL N-channel 8.3 mΩ 30 V TrenchMOS logic level FET in LFPAK

6. Characteristics

Table 6. Characteristics Tested to JEDEC standards where applicable. Symbol Parameter Conditions Min Typ Max Unit Static characteristics

V(BR)DSS drain-source breakdown ID = 250 µA; VGS =0V; Tj =25°C30--V voltage ID = 250 µA; VGS =0V; Tj = -55 °C 27 - - V

VGS(th) gate-source threshold voltage ID =1mA; VDS =VGS; Tj =25°C; 1.3 1.7 2.15 V see Figure 11; see Figure 12

ID =1mA; VDS =VGS; Tj =150°C; 0.5--V see Figure 12

ID =1mA; VDS =VGS; Tj =-55°C; --2.55V see Figure 12

IDSS drain leakage current VDS =30V; VGS =0V; Tj = 25 °C - 0.02 1 µA

VDS =30V; VGS =0V; Tj = 150 °C - - 100 µA

IGSS gate leakage current VGS =16V; VDS =0V; Tj = 25 °C - 10 100 nA

VGS =-16V; VDS =0V; Tj = 25 °C - 10 100 nA

RDSon drain-source on-state VGS =4.5V; ID =15A; Tj = 25 °C - 10.4 12.2 mΩ resistance VGS =10V; ID =15A; Tj =150°C; --15mΩ see Figure 13

VGS =10V; ID =15A; Tj =25°C - 6.9 8.3 mΩ

RG gate resistance f = 1 MHz - 2.03 - Ω Dynamic characteristics

QG(tot) total gate charge ID =45A; VDS =15V; VGS =4.5V; -9-nC see Figure 14; see Figure 15

ID =45A; VDS =15V; VGS =10V; - 18.3 - nC see Figure 14; see Figure 15

ID =0A; VDS =0V; VGS = 10 V - 16.1 - nC

QGS gate-source charge ID =45A; VDS =15V; VGS =10V; -2.7-nC see Figure 14; see Figure 15 QGS(th) pre-threshold gate-source -1.5-nC charge

QGS(th-pl) post-threshold gate-source -1.2-nC charge

QGD gate-drain charge - 4 - nC

VGS(pl) gate-source plateau voltage VDS = 15 V; see Figure 14; -3.2-V see Figure 15

Ciss input capacitance VDS =15V; VGS =0V; f=1MHz; - 1005 - pF Tj =25°C; see Figure 17 Coss output capacitance - 200 - pF

Crss reverse transfer capacitance - 102 - pF

td(on) turn-on delay time VDS =15V; RL =0.5Ω; VGS =4.5V; -15-ns RG(ext) =4.7Ω tr rise time - 29 - ns

td(off) turn-off delay time - 21 - ns

tf fall time VDS =15V; RL =0.5Ω; VGS =4.5V; -8-ns RG(ext) =4.7Ω

PSMN8R0-30YL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 16 May 2011 5 of 14 NXP Semiconductors PSMN8R0-30YL N-channel 8.3 mΩ 30 V TrenchMOS logic level FET in LFPAK

Table 6. Characteristics …continued Tested to JEDEC standards where applicable. Symbol Parameter Conditions Min Typ Max Unit Source-drain diode

VSD source-drain voltage IS =25A; VGS =0V; Tj =25°C; -0.91.2V see Figure 16

trr reverse recovery time IS =15A; dIS/dt = -100 A/µs; -34-ns VGS =0V; VDS =15V Qr recovered charge - 30 - nC

003aaf421 003aaf422 80 60 VGS (V) = 10 4.5 ID ID (A) (A)

60 3.5 45

40 30

3.0 ° ° Tj = 150 C Tj = 25 C 2.8 20 15 2.6 2.4

0 0 0 0.5 1 1.5 2 012345 V (V) DS VGS (V)

Fig 5. Output characteristics: drain current as a Fig 6. Transfer characteristics: drain current as a function of drain-source voltage; typical values function of gate-source voltage; typical values

003aaf423 003aaf424 60 2000

gfs C (S) (pF) Ciss 45 1500

Crss 30 1000

15 500

0 0 015304560 036912 I (A) D VGS (V)

Fig 7. Forward transconductance as a function of Fig 8. Input and reverse transfer capacitances as a drain current; typical values function of gate-source voltage; typical values

PSMN8R0-30YL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 16 May 2011 6 of 14 NXP Semiconductors PSMN8R0-30YL N-channel 8.3 mΩ 30 V TrenchMOS logic level FET in LFPAK

003aaf426 003aaf427 40 50 R R DSon DSon V (V) = 2.8 Ω Ω GS 3.5 (m ) (m ) 3.0 40 30

4.5 10 10 10

0 0 020406080I (A) 048121620 D VGS (V)

Fig 9. Drain-source on-state resistance as a function Fig 10. Drain-source on-state resistance as a function of drain current; typical values of gate-source voltage; typical values

003aab271 003aaf111 10-1 3

(A) VGS(th) 10-2 (V)

max min typ max 2 10-3 typ

10-4 min 1

10-5

-6 10 0 0123VGS (V) -60 0 60 120 180 ° Tj ( C)

Fig 11. Sub-threshold drain current as a function of Fig 12. Gate-source threshold voltage as a function of gate-source voltage junction temperature

PSMN8R0-30YL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 16 May 2011 7 of 14 NXP Semiconductors PSMN8R0-30YL N-channel 8.3 mΩ 30 V TrenchMOS logic level FET in LFPAK

03aa27 2 VDS a

ID 1.5

VGS(pl)

1 VGS(th)

VGS

QGS1 QGS2 0.5 QGS QGD QG(tot)

003aaa508 0 −60 0 60 120 180 Tj (°C)

Fig 13. Normalized drain-source on-state resistance Fig 14. Gate charge waveform definitions factor as a function of junction temperature

003aaf428 003aaf429 10 60 V GS IS (V) (A) 8 24V 45

6V V = 15V 6 DS

4 ° ° Tj = 150 C Tj = 25 C 15 2

0 0 0 5 10 15 20 0 0.3 0.6 0.9 1.2 Q (nC) G VSD (V)

Fig 15. Gate-source voltage as a function of gate Fig 16. Source (diode forward) current as a function of charge; typical values source-drain (diode forward) voltage; typical values

PSMN8R0-30YL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 16 May 2011 8 of 14 NXP Semiconductors PSMN8R0-30YL N-channel 8.3 mΩ 30 V TrenchMOS logic level FET in LFPAK

003aaf425 104

C (pF)

3 10 Ciss

Coss 2 10 Crss

10 10-1 1 10 102 VDS (V)

Fig 17. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values

PSMN8R0-30YL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 16 May 2011 9 of 14 NXP Semiconductors PSMN8R0-30YL N-channel 8.3 mΩ 30 V TrenchMOS logic level FET in LFPAK

7. Package outline

Plastic single-ended surface-mounted package (LFPAK; Power-SO8); 4 leads SOT669

A2 E A C c b2 2 E1

b L1 3 mounting b base 4

H D

L2 1 234 X e b w M A c

1/2 e

A (A 3 ) C A1

L detail X yC

0 2.5 5 mm

scale

DIMENSIONS (mm are the original dimensions) D (1) UNIT A A A A bcb b b c D(1) 1 E(1) E (1) e H L L L wyθ 1 2 3 2 3 4 2 max 1 1 2 1.20 0.15 1.10 0.50 4.41 2.2 0.9 0.25 0.30 4.10 5.0 3.3 6.2 0.85 1.3 1.3 8° mm 0.25 4.20 1.27 0.25 0.1 1.01 0.00 0.95 0.35 3.62 2.0 0.7 0.19 0.24 3.80 4.8 3.1 5.8 0.40 0.8 0.8 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 06-03-16 SOT669 MO-235 11-03-25

Fig 18. Package outline SOT669 (LFPAK; Power-SO8)

PSMN8R0-30YL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 16 May 2011 10 of 14 NXP Semiconductors PSMN8R0-30YL N-channel 8.3 mΩ 30 V TrenchMOS logic level FET in LFPAK

8. Revision history

Table 7. Revision history Document ID Release date Data sheet status Change notice Supersedes PSMN8R0-30YL v.2 20110516 Product data sheet - PSMN8R0-30YL v.1 Modifications: • Various changes to content. PSMN8R0-30YL v.1 20110217 Product data sheet - -

PSMN8R0-30YL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 16 May 2011 11 of 14 NXP Semiconductors PSMN8R0-30YL N-channel 8.3 mΩ 30 V TrenchMOS logic level FET in LFPAK

9. Legal information

9.1 Data sheet status

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[1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

9.2 Definitions Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without Preview — The document is a preview version only. The document is still limitation specifications and product descriptions, at any time and without subject to formal approval, which may result in modifications or additions. notice. This document supersedes and replaces all information supplied prior NXP Semiconductors does not give any representations or warranties as to to the publication hereof. the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or Draft — The document is a draft version only. The content is still under safety-critical systems or equipment, nor in applications where failure or internal review and subject to formal approval, which may result in malfunction of an NXP Semiconductors product can reasonably be expected modifications or additions. NXP Semiconductors does not give any to result in personal injury, death or severe property or environmental representations or warranties as to the accuracy or completeness of damage. NXP Semiconductors accepts no liability for inclusion and/or use of information included herein and shall have no liability for the consequences of NXP Semiconductors products in such equipment or applications and use of such information. therefore such inclusion and/or use is at the customer’s own risk.

Short data sheet — A short data sheet is an extract from a full data sheet Quick reference data — The Quick reference data is an extract of the with the same product type number(s) and title. A short data sheet is intended product data given in the Limiting values and Characteristics sections of this for quick reference only and should not be relied upon to contain detailed and document, and as such is not complete, exhaustive or legally binding. full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales Applications — Applications that are described herein for any of these office. In case of any inconsistency or conflict with the short data sheet, the products are for illustrative purposes only. NXP Semiconductors makes no full data sheet shall prevail. representation or warranty that such applications will be suitable for the specified use without further testing or modification. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between Customers are responsible for the design and operation of their applications NXP Semiconductors and its customer, unless NXP Semiconductors and and products using NXP Semiconductors products, and NXP Semiconductors customer have explicitly agreed otherwise in writing. In no event however, accepts no liability for any assistance with applications or customer product shall an agreement be valid in which the NXP Semiconductors product is design. It is customer’s sole responsibility to determine whether the NXP deemed to offer functions and qualities beyond those described in the Semiconductors product is suitable and fit for the customer’s applications and Product data sheet. products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their 9.3 Disclaimers applications and products.

Limited warranty and liability — Information in this document is believed to NXP Semiconductors does not accept any liability related to any default, be accurate and reliable. However, NXP Semiconductors does not give any damage, costs or problem which is based on any weakness or default in the representations or warranties, expressed or implied, as to the accuracy or customer’s applications or products, or the application or use by customer’s completeness of such information and shall have no liability for the third party customer(s). Customer is responsible for doing all necessary consequences of use of such information. testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and In no event shall NXP Semiconductors be liable for any indirect, incidental, the products or of the application or use by customer’s third party punitive, special or consequential damages (including - without limitation - lost customer(s). NXP does not accept any liability in this respect. profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such Limiting values — Stress above one or more limiting values (as defined in damages are based on tort (including negligence), warranty, breach of the Absolute Maximum Ratings System of IEC 60134) will cause permanent contract or any other legal theory. damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in Notwithstanding any damages that customer might incur for any reason the Recommended operating conditions section (if present) or the whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards Characteristics sections of this document is not warranted. Constant or customer for the products described herein shall be limited in accordance repeated exposure to limiting values will permanently and irreversibly affect with the Terms and conditions of commercial sale of NXP Semiconductors. the quality and reliability of the device.

PSMN8R0-30YL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 16 May 2011 12 of 14 NXP Semiconductors PSMN8R0-30YL N-channel 8.3 mΩ 30 V TrenchMOS logic level FET in LFPAK

Terms and conditions of commercial sale — NXP Semiconductors In the event that customer uses the product for design-in and use in products are sold subject to the general terms and conditions of commercial automotive applications to automotive specifications and standards, customer sale, as published at http://www.nxp.com/profile/terms, unless otherwise (a) shall use the product without NXP Semiconductors’ warranty of the agreed in a valid written individual agreement. In case an individual product for such automotive applications, use and specifications, and (b) agreement is concluded only the terms and conditions of the respective whenever customer uses the product for automotive applications beyond agreement shall apply. NXP Semiconductors hereby expressly objects to NXP Semiconductors’ specifications such use shall be solely at customer’s applying the customer’s general terms and conditions with regard to the own risk, and (c) customer fully indemnifies NXP Semiconductors for any purchase of NXP Semiconductors products by customer. liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ No offer to sell or license — Nothing in this document may be interpreted or standard warranty and NXP Semiconductors’ product specifications. construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 9.4 Trademarks

Export control — This document as well as the item(s) described herein may Notice: All referenced brands, product names, service names and trademarks be subject to export control regulations. Export might require a prior are the property of their respective owners. authorization from national authorities. Adelante, Bitport, Bitsound, CoolFlux, CoReUse, DESFire, EZ-HV, Non-automotive qualified products — Unless this data sheet expressly FabKey, GreenChip, HiPerSmart, HITAG, I²C-bus logo, ICODE, I-CODE, states that this specific NXP Semiconductors product is automotive qualified, ITEC, Labelution, MIFARE, MIFARE Plus, MIFARE Ultralight, MoReUse, the product is not suitable for automotive use. It is neither qualified nor tested QLPAK, Silicon Tuner, SiliconMAX, SmartXA, STARplug, TOPFET, in accordance with automotive testing or application requirements. NXP TrenchMOS, TriMedia and UCODE — are trademarks of NXP B.V. Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. HD Radio and HD Radio logo — are trademarks of iBiquity Digital Corporation.

10. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: [email protected]

PSMN8R0-30YL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 16 May 2011 13 of 14 NXP Semiconductors PSMN8R0-30YL N-channel 8.3 mΩ 30 V TrenchMOS logic level FET in LFPAK

11. Contents

1 Product profile ...... 1 1.1 General description ...... 1 1.2 Features and benefits...... 1 1.3 Applications ...... 1 1.4 Quick reference data ...... 1 2 Pinning information...... 2 3 Ordering information...... 2 4 Limiting values...... 2 5 Thermal characteristics ...... 4 6 Characteristics...... 5 7 Package outline ...... 10 8 Revision history...... 11 9 Legal information...... 12 9.1 Data sheet status ...... 12 9.2 Definitions...... 12 9.3 Disclaimers ...... 12 9.4 Trademarks...... 13 10 Contact information...... 13

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.

© NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 16 May 2011 Document identifier: PSMN8R0-30YL