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Important Notice Dear Customer, on 7 February 2017 The Important notice Dear Customer, On 7 February 2017 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS semiconductors with its focus on the automotive, industrial, computing, consumer and wearable application markets In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below. Instead of http://www.nxp.com, http://www.philips.com/ or http://www.semiconductors.philips.com/, use http://www.nexperia.com Instead of [email protected] or [email protected], use [email protected] (email) Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on the version, as shown below: - © NXP N.V. (year). All rights reserved or © Koninklijke Philips Electronics N.V. (year). All rights reserved Should be replaced with: - © Nexperia B.V. (year). All rights reserved. If you have any questions related to the data sheet, please contact our nearest sales office via e-mail or telephone (details via [email protected]). Thank you for your cooperation and understanding, Kind regards, Team Nexperia BUK954R4-80E N-channel TrenchMOS logic level FET 11 September 2012 Product data sheet 1. Product profile 1.1 General description Logic level N-channel MOSFET in a SOT78 package using TrenchMOS technology. This product has been designed and qualified to AEC Q101 standard for use in high performance automotive applications. 1.2 Features and benefits • AEC Q101 compliant • Repetitive avalanche rated • Suitable for thermally demanding environments due to 175 °C rating • True logic level gate with Vgst(th) rating of greater than 0.5V at 175 °C 1.3 Applications • 12V, 24V and 48V Automotive systems • Motors, lamps and solenoid control • Start-Stop micro-hybrid applications • Transmission control • Ultra high performance power switching 1.4 Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - - 80 V ID drain current VGS = 5 V; Tmb = 25 °C; Fig. 1 [1] - - 120 A Ptot total power dissipation Tmb = 25 °C; Fig. 2 - - 349 W Static characteristics RDSon drain-source on-state VGS = 5 V; ID = 25 A; Tj = 25 °C; Fig. 11 - 3.6 4.4 mΩ resistance Dynamic characteristics QGD gate-drain charge VGS = 5 V; ID = 25 A; VDS = 64 V; - 37.5 - nC Fig. 13; Fig. 14 [1] Continuous current is limited by package. Scan or click this QR code to view the latest information for this product NXP Semiconductors BUK954R4-80E N-channel TrenchMOS logic level FET 2. Pinning information Table 2. Pinning information Pin Symbol Description Simplified outline Graphic symbol 1 G gate mb D 2 D drain G 3 S source mb D mounting base; connected to mbb076 S drain 1 2 3 TO-220AB (SOT78A) 3. Ordering information Table 3. Ordering information Type number Package Name Description Version BUK954R4-80E TO-220AB plastic single-ended package; heatsink mounted; 1 mounting SOT78A hole; 3-lead TO-220AB 4. Marking Table 4. Marking codes Type number Marking code BUK954R4-80E BUK954R4-80E 5. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - 80 V VDGR drain-gate voltage RGS = 20 kΩ - 80 V VGS gate-source voltage Tj ≤ 175 °C; Pulsed [1][2] -15 15 V Tj ≤ 175 °C; DC -10 10 V ID drain current Tmb = 25 °C; VGS = 5 V; Fig. 1 [3] - 120 A Tmb = 100 °C; VGS = 5 V; Fig. 1 [3] - 120 A BUK954R4-80E All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved Product data sheet 11 September 2012 2 / 13 NXP Semiconductors BUK954R4-80E N-channel TrenchMOS logic level FET Symbol Parameter Conditions Min Max Unit IDM peak drain current Tmb = 25 °C; pulsed; tp ≤ 10 µs; Fig. 4 - 715 A Ptot total power dissipation Tmb = 25 °C; Fig. 2 - 349 W Tstg storage temperature -55 175 °C Tj junction temperature -55 175 °C Source-drain diode IS source current Tmb = 25 °C [3] - 120 A ISM peak source current pulsed; tp ≤ 10 µs; Tmb = 25 °C - 715 A Avalanche ruggedness EDS(AL)S non-repetitive drain-source ID = 120 A; Vsup ≤ 80 V; RGS = 50 Ω; [4][5] - 488 mJ avalanche energy VGS = 5 V; Tj(init) = 25 °C; unclamped; Fig. 3 [1] Accumulated pulse duration up to 50 hours delivers zero defect ppm [2] Significantly longer life times are achieved by lowering Tj and or VGS [3] Continuous current is limited by package. [4] Single-pulse avalanche rating limited by maximum junction temperature of 175 °C. [5] Refer to application note AN10273 for further information. 003aai230 03aa16 200 120 ID (A) Pder 160 (%) 80 120 (1) 80 40 40 0 0 0 50 100 150 200 0 50 100 150 200 T (°C) mb Tmb (°C) (1) Capped at 120A due to package Fig. 2. Normalized total power dissipation as a Fig. 1. Continuous drain current as a function of function of mounting base temperature mounting base temperature BUK954R4-80E All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved Product data sheet 11 September 2012 3 / 13 NXP Semiconductors BUK954R4-80E N-channel TrenchMOS logic level FET 003aag367 103 IAL (A) 102 (1) 10 (2) 1 (3) 10-1 10-3 10-2 10-1 1 10 tAL (ms) Fig. 3. Avalanche rating; avalanche current as a function of avalanche time. 003aai217 103 ID (A) Limit RDSon = VDS / ID tp =10 µ s 102 100 µs 10 DC 1 1 ms 10 ms 100 ms 10-1 10-1 1 10 102 103 VDS (V) Fig. 4. Safe operating area; continuous and peak drain currents as a function of drain-source voltage 6. Thermal characteristics Table 6. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Rth(j-mb) thermal resistance Fig. 5 - - 0.43 K/W from junction to mounting base Rth(j-a) thermal resistance vertical in still air - 60 - K/W from junction to ambient BUK954R4-80E All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved Product data sheet 11 September 2012 4 / 13 NXP Semiconductors BUK954R4-80E N-channel TrenchMOS logic level FET 003aaf570 1 Z th(j-mb) = 0.5 (K/W) 0.2 10-1 0.1 0.05 tp -2 P 10 T 0.02 tp t single shot T 10-3 10-6 10-5 10-4 10-3 10-2 10-1 1 tp (s) Fig. 5. Transient thermal impedance from junction to mounting base as a function of pulse duration. 7. Characteristics Table 7. Characteristics Symbol Parameter Conditions Min Typ Max Unit Static characteristics V(BR)DSS drain-source ID = 250 µA; VGS = 0 V; Tj = 25 °C 80 - - V breakdown voltage ID = 250 µA; VGS = 0 V; Tj = -55 °C 72 - - V VGS(th) gate-source threshold ID = 1 mA; VDS = VGS; Tj = 25 °C; 1.4 1.7 2.1 V voltage Fig. 9; Fig. 10 ID = 1 mA; VDS = VGS; Tj = -55 °C; - - 2.45 V Fig. 9 ID = 1 mA; VDS = VGS; Tj = 175 °C; 0.5 - - V Fig. 9 IDSS drain leakage current VDS = 80 V; VGS = 0 V; Tj = 25 °C - 0.08 1 µA VDS = 80 V; VGS = 0 V; Tj = 175 °C - - 500 µA IGSS gate leakage current VGS = 10 V; VDS = 0 V; Tj = 25 °C - 2 100 nA VGS = -10 V; VDS = 0 V; Tj = 25 °C - 2 100 nA RDSon drain-source on-state VGS = 5 V; ID = 25 A; Tj = 25 °C; Fig. 11 - 3.6 4.4 mΩ resistance VGS = 10 V; ID = 25 A; Tj = 25 °C; - 3.4 4.2 mΩ Fig. 11 VGS = 5 V; ID = 25 A; Tj = 175 °C; - - 10.9 mΩ Fig. 12; Fig. 11 Dynamic characteristics QG(tot) total gate charge ID = 25 A; VDS = 64 V; VGS = 5 V; - 123 - nC Fig. 13; Fig. 14 QGS gate-source charge - 26.6 - nC BUK954R4-80E All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved Product data sheet 11 September 2012 5 / 13 NXP Semiconductors BUK954R4-80E N-channel TrenchMOS logic level FET Symbol Parameter Conditions Min Typ Max Unit QGD gate-drain charge - 37.5 - nC Ciss input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz; - 12850 17130 pF Tj = 25 °C; Fig. 15 Coss output capacitance - 850 1020 pF Crss reverse transfer - 420 580 pF capacitance td(on) turn-on delay time VDS = 60 V; RL = 2.4 Ω; VGS = 5 V; - 70 - ns RG(ext) = 5 Ω tr rise time - 109 - ns td(off) turn-off delay time - 203 - ns tf fall time - 115 - ns LD internal drain from upper edge of drain mounting - 2.5 - nH inductance base to center of die from drain lead 6mm from package to - 4.5 - nH centre of die LS internal source from source lead to source bonding - 7.5 - nH inductance pad Source-drain diode VSD source-drain voltage IS = 25 A; VGS = 0 V; Tj = 25 °C; Fig. 16 - 0.77 1.2 V trr reverse recovery time IS = 20 A; dIS/dt = -100 A/µs; VGS = 0 V; - 61 - ns VDS = 25 V Qr recovered charge - 139 - nC 003aai219 003aai220 360 10 VGS(V) = 10 5 R I DSon D (mΩ) (A) 3.5 7.5 240 5 3 120 2.8 2.5 2.6 2.4 0 0 0 0.5 1 1.5 2 0 2.5 5 7.5 10 VDS(V) VGS(V) Tj = 25 °C; tp = 300 μs Fig.
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