Nexperia Pnx8500

Home Entertainment Engine Nexperia pnx8500

Designed for use in mid- to high-end advanced set-top box (ASTB) and digital television (DTV) systems, the Nexperia™ pnx8500 Home Entertainment Engine delivers comprehesive source decoder, interactive TV, Inter- net, telephony, and digital recording functions on a single chip.This highly flexible IC decodes all high-definition (HD) and standard-definition (SD) MPEG-2 source material. Outputting enhanced SD display, the pnx8500 is primarily targeted for STBs driving existing NTSC, PAL, and SECAM television sets as well as digital TVs and projectors.

On a single, flexible IC, the pnx8500 provides a complete, future-proof solution for building tomorrow's advanced STB products. In addition to supporting basic and premium TV services, pnx8500-powered STBs can be easily enhanced to deliver advanced TV services such FEATURES as web-browsing, time-shift record/playback, interactive + Dual-CPU design includes a 200-MHz TriMedia VLIW core and video, streaming video and audio media, video telepho- a 150-MHz MIPS 3940 core ny, games, purchase transaction management, and more. + Demultiplexes, descrambles and PID filters multiple DVB or New standards for DTV, communications, or multime- DSS transport streams dia can be supported through software upgrades.

+ Supports input of two digital video streams (CCIR656, broad- FLEXIBLE, DUAL-CPU ARCHITECTURE cast quality) The pnx8500 dual-CPU architecture combines powerful + Simultaneous MPEG-2 decoding of three SD streams or one MIPS (R3940) and TriMedia (TM32) VLIW processor HD (MP@HL) stream cores that control a range of on-chip hardware components + DVB, MULTI2 and DSS descrambling, and ICAM verification through three system buses. A large number of on-chip + DES ECB copy-protection accelerators, I/O peripherals, and communications interfaces offload the CPUs, enable support for an extensive + Simultaneous decoding of multiple, compressed, multi-channel audio streams, including Dolby Digital®, MP3 and more suite of set-top and DTV applications, and allow pnx8500 to be easily tailored with software for advanced applications. + DirectX® 6.1-compliant 3D graphics rendering engine; high performance 2D drawing engine Programmable CPU cores allow new features, services, or + Dual image composition/screen refresh engines output multi- standards to be supported through software upgrades with- ple channels for watch/record and multi-room modes out changing silicon or set-top boxes installed in the field. Comprehensive standard software development tools sup- + Embedded IEEE 1394 link layer with 5C copy protection port application development in high-level languages. + Softmodem support via synchronous serial interface

+ Core peripherals on-chip (I2C, UARTs, USB, etc.) + Peripheral expansion through Super I/O chip and PCI/XIO + Comprehensive software development and integration tools lmtb TRHD Functional Overview In basic ASTB and DTV systems, the pnx8500 provides decoding, processing, and display functionality for MPEG-2 transport streams. A combination of fixed-function hardware blocks and software modules demultiplex, descramble, program identification (PID) filter and decode the source, generate graphics, and com- posite the final video for display. Audio decoding and processing is performed entirely in software.

TRANSPORT STREAM DECODING MPEG-2 decoding__After transport stream demux, the MPEG-2 Conditional access__The pnx8500 supports on-chip DVB, program stream is decoded by an on-chip hardware accelerator. MULTI2, DES, 3DES, and DSS descrambling, ICAM verifica- The pnx8500 supports all 18 ATSC formats and simultaneous tion, and DES copy protection. Copy protection authentication decode of one HD stream or three SD streams. is handled in software. Audio decoding__All digital audio processing is handled in soft- Depending on system requirements, transport streams may pass ware on the TM32 CPU. Multiple compressed, multi-channel through external Point of Deployment (POD) or Common audio streams such as Dolby Digital, AAC, or MP3 can be Interface (CI) conditional access modules before input. Support processed simultaneously. For product configurations that do not for external CAS modules includes the DVB CI, the OpenCable support multi-channel output, multi-channel audio signals are POD interface, and the National Renewable Security System downmixed into stereo using Dolby Pro Logic® algorithms. (NRSS-B) interface. In addition to audio demuxed from the transport stream, PCM Transport stream & video input__The pnx8500 supports input stereo audio can also be received from other sources, such as a processing of up to two digital video (CCIR656) or two transport VCR. The TM32 CPU processes audio effects and enhancements streams or a combination of both. Both serial and parallel trans- and mixes stereo PCM audio data as needed. port stream formats are supported. Several methods of video/ Graphics processing__The pnx8500 supports hardware-acceler- stream input enable different product configurations and features. ated rendering of 2D and 3D graphics. 2D capabilities fulfill the Demultiplexing/PID Filtering__After transport stream input requirements of standard graphical user interfaces and EPGs. An the pnx8500 performs PID (PES and section) filtering, time- on-chip 3D rendering engine delivers excellent 3D performance stamping, descrambling, and demultiplexing; results are written for set-top applications such as games. to memory. DISPLAY PROCESSING Nexperia Digital Video Platform Picture enhancement, display composition__Once all video The pnx8500 Home Entertainment Engine and graphics data for specific fields or frames has been generated, the video display pipeline processes the images for display. A is the newest IC to comply with the variety of programmable capabilities enable support for a many Nexperia Digital Video Platform (DVP), a different of display systems. Six-tap horizontal/vertical scaling new architectural specification designed for prepares the picture for various display sizes and aspect ratios, including downsampling an HD picture for SD display. Anti- consumer digital video appliances.The flicker filtering can be applied to non-interlaced graphics images. Nexperia DVP architecture enables a family De-interlacing processes an interlaced video signal for display on a progressive scan display device such as a double line-rate TV or of cost-effective, highly programmable, scal- high-resolution PC monitor. Philips-patented Natural Motion™ able devices that maximize hardware and algorithms can improve picture quality through motion estima- software components reuse, reducing devel- tion and compensation. The TM32 CPU can also be programmed to perform additional video enhancements not implemented in opment expense and time to market. hardware. The Nexperia DVP platform defines a bus The pnx8500 supports simultaneous output of two fully indepen- architecture and common bus interfaces. It dent SD video channels, each composited from layers of enhanced video frames, PIPs, menus, cursor, and other graphical informa- seamlessly enables designers to attach one tion. The primary channel is intended for viewing; a secondary or more CPUs, add lower-speed buses for channel can be recorded or viewed in an alternate location. Video peripheral expansion, and connect on-chip is synchronized with audio through timestamping before output for off-chip analog conversion. graphics, communications interfaces, copro-

ADVANCED SERVICES cessing blocks as needed to address specific In addition to support for basic STB and DTV applications, a market or application requirements. Pro- variety of advanced TV features and services can be implemented grammable CPU cores allow easy implemen- by upgrading or adding application modules and board-level components. tation of new capabilities and standards as they become available, without changing the The addition of CD-Recordable or hard-disk drives enables per- sonal video recording or time shifting record/playback. Add a silicon. return channel (cable or PSTN modem, DSL, etc.) and application modules to support interactive services such as Web brows- The Nexperia DVP software architecture ing, shopping, e-mail, TV games, chat rooms, and more. The defines an application layer, middleware such addition of codecs enables IP telephony applications such as as Liberate TV, Microsoft TV, MHP,Media audio and video phones. Highway, and OpenTV, and consistent APIs to shield applications and middleware from media processing and other lower-level services.With this approach, programmers do not need to know whether a media-processing task is implemented in hardware or software. Once developed, application software can be reused with little to no modifications on other Nexperia DVP-compliant ICs. Architectural Overview Comprehensive transport stream decoding, display processing, and a variety of additional functions are supported by two CPU cores and a variety of on-chip hardware accelerators, I/O blocks, and peripherals__all connected through system buses. Compliant with the Philips Nexperia DVP architectural specification, pnx8500 gives set-top and DTV manufacturers the flexibility to reuse pnx8500 hardware designs and software modules.

DUAL BUS DESIGN TM32 supports a library of media processing and communica- The pnx8500 uses a high-speed DVP memory bus and dual PI tions application modules. Application library modules needed buses to connect CPUs and on-chip units with each other and to drive core STB and DTV source decoding functions are with main memory. Both processors can access all units. included in the Nexperia pnx8500 Home Entertainment Engine software suite. Other modules are available from Philips and A 64-bit memory bus ensures high bandwidth and low latency for third-party vendors. A comprehensice software development envi- the MIPS and TM32 CPUs and on-chip blocks requiring high- ronment is included for creating new application libraries for the speed memory access. Two PI buses and a crossover PI-to-PI or TM32 core in C and C++. memory-mapped I/O (MMIO) bridge enable each processor to __ control or observe peripheral block status. On-chip blocks may MIPS processor core The 150-MHz MIPS 3940 RISC proces- also use PI segments as a medium-bandwidth memory access bus sor implements the MIPS-II and MIPS-16 instruction set archi- through DMA gateways. tecture. It has a built-in R4000 TLB-based MMU and split instruction and data cache. The MIPS core fully implements ker- A particular block's memory performance requirements determine nel/user system protection, memory address translation, and to which PI bus its DMA interface connects. Modules processing access control, allowing the pnx8500 to run operating systems audio or video streams or requiring real-time interrupt response with inter-process protection. The MIPS core is integer-only are attached to the TM32 PI bus. using traps and emulation to support floating-point instructions. PROGRAMMABLE CENTRAL PROCESSORS Devices associated with control functions connect to the PI bus TriMedia TM32 core__The 32-bit, 200-MHz processor TM32 close to the MIPS core to ensure low latency. core utilizes a very-long instruction word (VLIW) architecture to The MIPS core is primarily responsible for interactive applica- process up to five instructions per clock cycle. It supports 32-bit tions, control functions, front-end graphics processing, and run- integer and IEEE-compatible 32-bit floating point data formats. ning operating systems such as Windows CE and pSOS. The The instruction set includes a full RISC complement, customized Nexperia Home Entertainment Engine relies on standard tools DSP operations, and an extensive set of single-instruction, multi- for application development on the MIPS core. ple-data (SIMD) operations for handling repetitive multimedia __ functions. The TM32 core is supported by on-chip 16-KB data JTAG development support The MIPS Enhanced JTAG and 32-KB instruction caches that employ a variety of techniques (EJTAG) module acts as companion to the Debug Support Unit to improve cache hit ratios and CPU performance. in the MIPS core. A separate IEEE 1149.1 JTAG module can be used to monitor, communicate with, and debug applications run- The programmable TriMedia TM32 core is primarily responsible ning on the TM32 core. for real-time and media processing functions. Some functions are MEMORY SYSTEM performed entirely in software; for others, the TM32 works in __ tandem with on-chip hardware blocks. Main Memory Interface (MMI) A dedicated, glueless 64-bit MMI unit connects the pnx8500 to up to 64 MB of local In target STB devices, the TM32 CPU is responsible for a diverse SDRAM. The MMI unit provides all control and data signals set of tasks including transport stream creation, audio decode, with sufficient drive capacity for a glueless connection to a 143- controlling the HL MPEG-2 decoder, and communications. 80% MHz memory system of up to four memory chips. percent idle in base STB applications, the TM32 core provides flexible processing power for adding more advanced features and The MMI takes advantage of the on-chip interleaving of SDRAM services. It can decode most SD video compression standards and devices to deliver sustainable, full-bandwidth data transfer. It associated audio at full frame rate or perform all media compres- contains the SDRAM controller, MMIO logic, the memory-high- sion, decompression, and processing necessary for applications way arbiters, and a central arbiter responsible for allocating mem- such as full-duplex IP or video telephony. ory bandwidth to internal resources. The pnx8500 memory arbiter uses a programmable, cyclical list-based arbiter that applications. In 3D operations, the TM32 core performs tri- assigns unused list slots to the CPUs. This guarantees angle setup and controls the hardware 3D engine; the MIPS required latency to all real-time agents while optimizing CPU core performs transformation and lighting. performance. High-level MPEG-2 decoder__A high-level MPEG-2 decoder COPROCESSORS/ACCELLERATORS block performs MPEG-2 program stream decoding below slice The pnx8500 includes on-chip coprocessors for 2D and 3D level. The TM32 core controls the decode process and handles graphics acceleration, MPEG decoding, image scaling and fil- MPEG-2 processing above slice level. BS-D, DVB, and all 18 tering, and display channel composition. All coprocessors read ATSC formats are supported; three SD streams or one HD input and write results to memory. stream can be decoded simultaneously. The MPEG-2 decoder is capable of full-resolution decoding or decoding to a 2X 2D drawing engine__The pnx8500 2D drawing accelerator horizontally compressed image format, saving memory space block performs high-speed graphics operations including fast and bandwidth. area fills, three-operand bitblt, monochrome data expansion, __ and line drawing. Monochrome data can be color-expanded to Memory-based scaler (MBS) The primary function of the any supported pixel format. Anti-aliased lines are supported MBS block is acceleration of scaling operations. It reads input through a 16-level alpha-blend bitblt. A full 256-level alpha from and writes results to memory. Compared to an 'on-the- bitblt supports blending of source and destination images. The fly' approach, this method de-couples the scaling operation 2D engine can also be used as a generic DMA engine to trans- from the display, significantly reducing on-demand memory fer data between memory locations on a byte-aligned basis. bandwidth requirements. Since the MBS block uses memory as a buffer, it can process many images in the same time 3D rendering engine__An on-chip 3D drawing engine accel- required to display a single frame. erates texture-mapped pixel rendering. It implements Microsoft-compatible DirectX 6.1 3D functions, such as bi- In addition to basic scaling capabilities, the MBS performs linear and tri-linear texture filtering. many commonly required image manipulations prior to display including linear and non-linear aspect ratio conversion Rendering speeds up to 60 Mpix/sec for bilinear- and trilin- (including panorama mode), anti-flicker filtering, de-interlac- ear-textured, mip-mapped, z-buffered, blended triangles deliv- ing, and pixel format conversion functions. er excellent 3D graphics quality for ASTB or television

NEXPERIA PNX8500 CONCEPTUAL ARCHITECTURE Advanced image composition processor (AICP)__Two The pnx8500 supports input of two CCIR656 video streams AICP units perform color-space conversion and final image and up to four transport streams. After input, streams are rout- composition and refresh of the primary and secondary display ed to either the video input processor (VIP) blocks or MPEG channels. Compositing is performed in either RGB or YUV system processor (MSP) blocks, depending on stream type. color space, depending on the AICP output mode. Compositing Dual video input processors__Two VIP blocks input digital functionality is highly programmable and includes chroma, video (primarily CCIR656) at pixel rates up to 40 MHz in a alpha or color-key based alpha-blending and pixel selection variety of packed YUV422 memory video formats. To reduce from the previous or current layer or the background color. the amount of memory required to store video data, the VIP Two physical and logically independent AICP units support all blocks can compress video lines horizontally using a 6-tap display modes. The primary AICP composites four layers to polyphase scaler in normal or transposed polyphase modes. produce the primary output channel, intended for display on After input processing, video data is stored in memory. VIPs a TV or monitor. The secondary AICP composites two layers also support a raw data-streaming input mode for message to create the secondary channel, intended for output to a passing and handling future 8-to-10-bit data formats. VCR or other recording device or for viewing on another TV. Transport stream input and routing__Transport stream Each layer has its own pixel clock and frame timing. input is supported from several sources including two trans- All layers in both units are identical, so there are no restrictions port stream input interfaces (TSIN), a 1394 receiver channel, on how each layer can be utilized. Thus the primary display an internal DMA agent dedicated to software-generated trans- can have four layers of video, graphics, or a mix of both. To port streams, and a feedback channel from each of the MPEG support scenarios other than watch/record, one or both AICPs System Processor (MSP) blocks containing PID filtered, can be set to divide their layers over two pixel/timing synchro- optionally de-scrambled data. Each TSIN supports parallel nous multiplexed outputs. This allows refresh of up to four and serial formats and input of up to four serial transport screens with limited compositing capabilities. The output of streams. Serial streams are converted to parallel within the each AICP unit is sent to a digital video output port. TSIN block before further routing. MEMORY-BASED ARCHITECTURE After input, each transport stream is routed to one of several The pnx8500 operates as a memory-based system; memory destinations including an MSP block, a 1394 transmitter serves as the buffer to decouple input and output data streams. channel, or a transport stream output (TSOUT) block. Parallel As pnx8500 decodes input, it stores results in memory. When streams are converted to serial as needed by the TSOUT block. multiple data structures exist in memory for a given input MPEG system processors__Two independent MSP blocks stream, timestamping is used to determine when to display parse DVB and DSS transport streams, perform PID and sec- specific structures. Use of memory as a staging buffer simpli- tion filtering, timestamping, descrambling, and demultiplex- fies synchronization between various on-chip blocks. ing, then write results to memory. Each MSP block handles I/O UNITS one transport stream, thus up to two transport streams can be processed simultaneously. On-chip I/O units receive and/or route input from or transmit output to off-chip devices. Some perform additional Prior to input, transport streams may pass through external stream processing and formatting. POD or CI conditional access modules. Descrambler entitle- ment systems are supported through two independent Smartcard When used for output, this block supports up to eight PCM interfaces. Transport streams input through the 1394 interface audio channels, driving up to four external stereo D/As. It sup- can also be routed to the MSP blocks for processing. ports 16-bit input and up to 32-bit output sample precision.

Video output__After composition by the AICP units, final video All audio units have a programmable 1 Hz to 100 kHz sampling frames are output for analog conversion through two video output rate with internal or external sampling clock sources. Each includes blocks. Each block supports output of a single CCIR656 signal. an independent, programmable clock generator for precise oversampling A/D and D/A system clocks. Audio interface units (AIO)__The pnx8500 uses five I2S blocks to receive and/or transmit audio signals. Audio streams are S/PDIF output (SPDIO)__The SPDIO block enables input or processed as needed (decompressed, downsampled, remixed) in output of datastreams in the Sony/Philips Digital Interface format. software on the TM32 CPU. S/PDIF input is intended primarily for DTV applications where an S/PDIF source is available from an external device, such as a Two audio input blocks supports sample sizes up to 16 bits and DVD player. Audio data can be received in a variety of formats, provide all signals needed to connect to off-chip, high quality, such as stereo PCM data, a 5.1-channel Dolby Digital datastream, low-cost, oversampling A/D converters, other I2S subsystems, or IEC-1937, etc. After stream input, SPDIO timestamps and writes other serial data sources. Two audio output blocks support up to incoming data to memory. Data interpretation and sample rate 32-bit audio samples and provide a DMA-driven serial interface recovery is performed by software on the TM32 core. Software- supporting glueless interfaces to high-quality, low-cost oversam- decoded audio can be mixed with other audio before output. pling stereo D/A converters. The SPDIO block can output either one of the originally The bi-directional audio port can be configured at system initial- received compressed multi-channel audio programs (Dolby ization to perform either stereo input or multi-channel output.

NEXPERIA PNX8500 INPUT/OUTPUT Digital or multi-channel MPEG audio) or stereo PCM samples PCI bus interface unit__A PCI expansion bus interface unit, from an internal audio mix. The transmitted audio stream format PCI-XIO8, allows easy connection of a variety of board-level is constructed in software on the TM32 core. No audio transcod- memory components and peripherals. It allows simultaneous ing is provided in normal system operation. The SPDIO sample access of 32-bit PCI master/slave devices and a glueless inter- rate is fully software controlled enabling perfect synchronization face to eight-bit microprocessor slave peripherals such as stan- to the broadcast audio source. dard or disk-type (NAND) Flash memory, DOCSIS modems, additional UARTs, etc. With the addition of external isolation 1394 interface__The pnx8500 includes a 1394-link FireWire® buffers, a full PIO-mode, DMA IDE hard disk interface with layer controller and provides a PHY-LINK interface for connecting sustained speeds up to 10 MB/sec is provided. Commercially to external 1394- or 1394.a-compliant physical layer devices. The available third-party Super I/O chips can be used to add func- 1394 interface can simultaneously transmit up to two transport tionality such as IEEE-1284 or 10/100 Ethernet or UDMA66 streams while receiving a third. 1394-transmitted streams are IDE controllers. generated by PID filtering of an input stream (in the MSP) or by software on the TM32 core. The PCI-XIO8 unit complies with Revision 2.2 of the PCI bus specification and operates as a 32-bit PCI master/target at Typical uses of the 1394 interface include passthrough of an HD 33 MHz. The pnx8500 can act as a PCI bus arbiter for up to transport stream to an external HDTV set and sending a program three external masters without external logic. The eight-bit, transport stream to or receiving programs from an external digital bi-directional XIO8 interface is master-only and provides video recorder. non-multiplexed address and data lines. The pnx8500 supports 1394 link-layer enhancements required for ON-CHIP PERIPHERALS set-top applications including the IEC61883 International The pnx8500 has all the on-chip peripherals needed to build Standard of Digital Interface and copy protection based on 5C. a baseline digital STB or DTV system including: Copy protection authentication is performed in software on the TM32 core. + one revision 1.1-compliant USB Root Host with two ports, each with individual overcurrent detect and powerdown control

+ two multi-master I2C interfaces

+ five UART interfaces including two SmartCard UARTs, one IrDA data UART, two general purpose UARTs

+ One bus-mastering DMA synchronous serial interface (SSI) to implement softmodem and other serial connections

+ 12 dedicated GPIO pins. 49 other pins can operate in either regular or GPIO mode. GPIO pins are used to implement remote control and IR blaster commands. DEVELOPMENT BOARD The pnx8500 is supported by a complete reference design and production-ready software for set-top and DTV applications. A PCI-based development system is also available to help developers create and test new products. COMPANION IC FOR ANALOG OUTPUT For many set-top and DTV applications, the Philips pnx8510 is an ideal companion IC for pnx8500 configurations, provid- ing analog video and audio conversion before display. Its two integrated digital encoders (DENCs) support NTSC, PAL, or SECAM output; six video DACs support two video output channels. Four audio DACs handle output of two stereo audio channels. Software Architecture & Development Tools Nexperia DVP-compliant products offer a scalable software development platform enabling developers to build STB and DTV products for a variety of consumer markets using readily available software modules.The complete DVP software platform includes application development tools, a standard interface to popular middleware and applications, support for leading operating systems, reference systems for debugging and validation, and optional value-added software modules.

Layered, modular software architecture__The Nexperia Application and device libraries__The pnx8500 includes soft- software architecture enables application portability across all ware modules that perform advanced audio and video processing Nexperia Home Entertainment Engine products. Software lay- for set-top and DTV applications. Optional value-added software ers, including hardware API components, board support libraries are also available from Philips Semiconductors including library components, and device libraries abstract the hardware a 1394 stack with 5C copy protection, a USB stack for USB 2.0, to a standard Nexperia DVP API. Common services such as a fast Java Virtual Machine (JVM), and a software modem. memory management and operating and system abstraction Supports popular operating systems and middleware__The layers are included in the infrastructure component. pnx8500 is designed to support popular operating systems such Each software layer contains multiple components or modules. as pSOS real-time kernels, Windows CE, and Linux plus middle- Software modularity enables easy addition of new features, ware such as Microsoft TV, Liberate TV, Open TV, and DVB- helping to future proof products and facilitate field upgrades. MHP-Java. Because software components can be reused, products benefit Software debugging__JTAG ports and software modules support from faster time-to-market and high levels of software integrity. application debugging. TM32 applications are debugged using an Development tools__The pnx8500 is supported by comprehen- interactive source debugger tool running on a PC through a JTAG sive development tools. The TriMedia software development plug-in board. The PC communicates with the TM32 CPU environment (SDE) includes a complete tool suite for creating, through the pnx8500 JTAG pins and the software debug module. debugging, simulating, and integrating highly optimized appli- A MIPS Enhanced JTAG (EJTAG) module acts as companion to cations for the TM32 core in C and C++. Developers of new the Debug Support Unit in the MIPS core to give a host comput- streaming modules for the TM32 core can take advantage of er total control over the MIPS core for debugging purposes. The the TriMedia Software Streaming Architecture, a set of Philips- EJTAG module supports both PI master and slave functionality designed application-development guidelines that promote and a special operation mode enabling developers to trace modularity, interoperability and component reuse. Metrowerks instruction flow of the CPU. CodeWarrior/pSOS IDE also supports application development for the TriMedia core.

Applications for the MIPS core can be developed using readily available, 3rd-party tools including compilers, linkers, and debuggers from Microsoft and WindRiver (ISI). Microsoft NT or UNIX host-development environments support the TriMedia and MIPS cores with tools such as pSOS PRISM+, WinCE toolset, MSTVPak, and GNU Make.

Common interface and integration tools support application integration across CPU cores ensuring compatibility and proper functionality. The Nexperia DVP porting kit provides hardware APIs containing device libraries for each function on the ASTB reference board.

NEXPERIA LAYERED, MODULAR SOFTWARE ARCHITECTURE Nexperia pnx8500 Specifications

PHYSICAL Sampling Rate programmable 1 Hz to 100 kHz with 0.001 Hz Process 0.18-micron CMOS resolution Packaging 456 BGA Interface I2S Power supply core: 1.8 V; I/O: 3.3 V (5 V tol.) SPDIF IN consumption 2500 mA; 4.5 W Formats 16-24 bit PCM coded or IEC61937 non-PCM Temperature ambient: 0 to 70 oC coded samples TRIMEDIA TM32 CPU SPDIF OUT Clock Speed 200 MHz Formats 2 channel linear PCM, Dolby Digital 5.1-chan- Registers 128 (32-bits) nel embedded as IEC61937, MPEG-1 or MPEG-2 embedded as IEC61937 Issue Slots 5 Samples Size 16-24 bits Functional Units 27 Data Rate Up to 40 Mbits/sec Cache 8-way set associative; 16-KB data, 32-KB instruction PCI/XIO MIPS 3940 CPU Speed 33 MHz Clock Speed 150 MHz Bus Width 32 bits Registers 32 (32-bit) Address Space 4 GB Issue Slots 1 Standard Compliance PCI Spec 2.1 MMU R4000 TLB UART Cache 4-way set associative; 8-KB data, 16-KB Number of Units 3 instruction Signaling receive and transmit pins MEMORY SYSTEM Number of Pins UART1: 2 pins, UART 2 and 3: 4 pins Speed 143 MHz SYNCHRONOUS SERIAL INTERFACE Memory Size 16/32/64 MB Data Formats variable slots/frame Width 64-bit Frame Sync external or internal Supported Types SDRAM (x16, x32) External Interface 6 pins (2 usable for tip and ring) Max Bandwidth 1.14 GB/sec USB Signal Levels 3.3 V LVTTL Host Controller Version 1.1 VIDEO IN Interface Number of Units 3 Ports 2 downstream ports Supported Signals CCIR 656; 8-10 bit YUV422 IEEE 1394 Pixel Frequency 40 MHz Link Layer interface to PHY chip VIDEO OUT Speed 100, 200, 400 Mbits/sec Number of Units 2 Copy Protection 5C Output Modes RGB 444, YUV 444, YUV 422 (CVBS, Y/C) I2C INTERFACE External Interface 10 data pins Number of Units 2 Clock Speed up to 81 MHz Modes multiple master and slave AUDIO IN Speed Up to 400 kHz Number of Units 3 (1 shared with Audio Out) SMARTCARD UART Number of Channels 2 Number of Units 2 Sample Size 8 or 16 bit Standard 7816 Sampling Rate programmable 1 Hz to 100 kHz with 0.001 Hz Protocol asynchronous, synchronous resolution Interface I2S TRANSPORT STREAM INPUT Number of Units 2 AUDIO OUT Modes parallel and serial (up to two serial transport Number of Units 3 (1 shared with Audio In) streams per unit) Number of Channels 2/8 Speed 108 MHz Sample Size 8 or 16 bit TRANSPORT STREAM OUTPUT Modes parallel and serial transport streams Speed 108 MHz MPEG SYSTEM PROCESSOR Number of Units 2 Function descrambling, demultiplexing and PID filtering of transport streams TS Formats DVB and DSS Speed up to 81 Mbits/sec Descrambling DVB, DES, ICAM, MULTI2 Copy protection DES PID up to 64 filters (for PES and Sections) HIGH-LEVEL MPEG DECODER Function slice-level decoder Modes MPEG-1, MPEG-2 Resolution up to MP@HL IMAGE COMPOSITION PROCESSOR Number of Units 2 Number of Layers primary: 4, secondary: 2 Layer Features chroma keying, alpha blending format conversion between 4:4:4 and 4:2:2 Data Formats YUV, RGB, Indexed MEMORY BASED SCALER Filtering 4- and 6-tap 64 polyphase Scaling programmable scale factor for horizontal and vertical scaling Format Conversion between 4:2:0, 4:2:2 and 4:4:4 Video Enhancement de-interlacing and motion compensation Graphics Enhancement anti-flicker filtering

2D DRAWING ENGINE Features 3-operation bitblt, line drawing, polygon filling 3D DRAWING ENGINE Drawing Rate 60 Mpixels/sec Features anti-aliasing Gouraud shading, z -buffer, texture caching, dithering Software Support Direct 3D, OpenGL F O R M O R E I N F O R M A T I O N C O N T A C T :

PHILIPS SEMICONDUCTORS DIGITAL VIDEO INTERACTIVE 811 EAST ARQUES AVENUE SUNNYVALE CA 94088 PH 800-234-7381 WEBSITE www.nexperia.com

Philips Semiconductors - a worldwide company

Argentina: see South America Australia: Tel. +61 2 9805 4455 Fax. +61 2 9805 4466 Austria: Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210 Belarus: Tel. +375 172 20 0733, Fax. +375 172 20 0773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Tel. +359 2 68 9211, Fax. +359 2 68 9102 Canada: Tel. +1 800 234 7381, Fax. +1 800 943 0087 China/Hong Kong: Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Tel. +45 33 29 3333, Fax. +45 33 29 3905 Finland: Tel. +358 9 615 800, Fax. +358 9 6158 0920 France: Tel. +33 1 4099 6161, Fax. +33 1 4099 6427 Germany: Tel. +49 40 2353 60, Fax. +49 40 2353 6300 Hungary: see Austria India: Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080 Ireland: Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: Tel. +9-5 800 234 7381, Fax. +9-5 800 943 0087 Middle East: see Italy Netherlands: Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Tel. +55 11 821 2333, Fax. +55 11 821 2382 Spain: Tel. +34 93 301 6312, Fax. +34 93 301 4107 Sweden: Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Tel. +41 1 488 2741, Fax. +41 1 488 3263 Taiwan: Tel. +886 2 2134 2886, Fax. +886 2 2134 2874 Thailand: Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: Tel. +1 800 234 7381, Fax. +1 800 943 0087 Uruguay: see South America Vietnam: see Singapore Yugoslavia: Tel. +381 11 62 5344, Fax. +381 11 63 5777

Internet: http://www.semiconductors.philips.com

For all other countries apply to: Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825

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Printed in the U.S.A. October 2000 PRELIMINARY lmtb TRHD