Nexperia Pnx8500
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Home Entertainment Engine Nexperia pnx8500 Designed for use in mid- to high-end advanced set-top box (ASTB) and digital television (DTV) systems, the Nexperia™ pnx8500 Home Entertainment Engine deliv- ers comprehesive source decoder, interactive TV, Inter- net, telephony, and digital recording functions on a single chip.This highly flexible IC decodes all high-definition (HD) and standard-definition (SD) MPEG-2 source material. Outputting enhanced SD display, the pnx8500 is primarily targeted for STBs driving existing NTSC, PAL, and SECAM television sets as well as digital TVs and projectors. On a single, flexible IC, the pnx8500 provides a com- plete, future-proof solution for building tomorrow's advanced STB products. In addition to supporting basic and premium TV services, pnx8500-powered STBs can be easily enhanced to deliver advanced TV services such FEATURES as web-browsing, time-shift record/playback, interactive + Dual-CPU design includes a 200-MHz TriMedia VLIW core and video, streaming video and audio media, video telepho- a 150-MHz MIPS 3940 core ny, games, purchase transaction management, and more. + Demultiplexes, descrambles and PID filters multiple DVB or New standards for DTV, communications, or multime- DSS transport streams dia can be supported through software upgrades. + Supports input of two digital video streams (CCIR656, broad- FLEXIBLE, DUAL-CPU ARCHITECTURE cast quality) The pnx8500 dual-CPU architecture combines powerful + Simultaneous MPEG-2 decoding of three SD streams or one MIPS (R3940) and TriMedia (TM32) VLIW processor HD (MP@HL) stream cores that control a range of on-chip hardware components + DVB, MULTI2 and DSS descrambling, and ICAM verification through three system buses. A large number of on-chip + DES ECB copy-protection accelerators, I/O peripherals, and communications inter- faces offload the CPUs, enable support for an extensive + Simultaneous decoding of multiple, compressed, multi-channel audio streams, including Dolby Digital®, MP3 and more suite of set-top and DTV applications, and allow pnx8500 to be easily tailored with software for advanced applications. + DirectX® 6.1-compliant 3D graphics rendering engine; high performance 2D drawing engine Programmable CPU cores allow new features, services, or + Dual image composition/screen refresh engines output multi- standards to be supported through software upgrades with- ple channels for watch/record and multi-room modes out changing silicon or set-top boxes installed in the field. Comprehensive standard software development tools sup- + Embedded IEEE 1394 link layer with 5C copy protection port application development in high-level languages. + Softmodem support via synchronous serial interface + Core peripherals on-chip (I2C, UARTs, USB, etc.) + Peripheral expansion through Super I/O chip and PCI/XIO + Comprehensive software development and integration tools lmtb TRHD Functional Overview In basic ASTB and DTV sys- tems, the pnx8500 provides decoding, processing, and display functionality for MPEG-2 transport streams. A combination of fixed-function hardware blocks and software modules demultiplex, descramble, program identification (PID) filter and decode the source, generate graphics, and com- posite the final video for display. Audio decoding and processing is performed entirely in software. TRANSPORT STREAM DECODING MPEG-2 decoding__After transport stream demux, the MPEG-2 Conditional access__The pnx8500 supports on-chip DVB, program stream is decoded by an on-chip hardware accelerator. MULTI2, DES, 3DES, and DSS descrambling, ICAM verifica- The pnx8500 supports all 18 ATSC formats and simultaneous tion, and DES copy protection. Copy protection authentication decode of one HD stream or three SD streams. is handled in software. Audio decoding__All digital audio processing is handled in soft- Depending on system requirements, transport streams may pass ware on the TM32 CPU. Multiple compressed, multi-channel through external Point of Deployment (POD) or Common audio streams such as Dolby Digital, AAC, or MP3 can be Interface (CI) conditional access modules before input. Support processed simultaneously. For product configurations that do not for external CAS modules includes the DVB CI, the OpenCable support multi-channel output, multi-channel audio signals are POD interface, and the National Renewable Security System downmixed into stereo using Dolby Pro Logic® algorithms. (NRSS-B) interface. In addition to audio demuxed from the transport stream, PCM Transport stream & video input__The pnx8500 supports input stereo audio can also be received from other sources, such as a processing of up to two digital video (CCIR656) or two transport VCR. The TM32 CPU processes audio effects and enhancements streams or a combination of both. Both serial and parallel trans- and mixes stereo PCM audio data as needed. port stream formats are supported. Several methods of video/ Graphics processing__The pnx8500 supports hardware-acceler- stream input enable different product configurations and features. ated rendering of 2D and 3D graphics. 2D capabilities fulfill the Demultiplexing/PID Filtering__After transport stream input requirements of standard graphical user interfaces and EPGs. An the pnx8500 performs PID (PES and section) filtering, time- on-chip 3D rendering engine delivers excellent 3D performance stamping, descrambling, and demultiplexing; results are written for set-top applications such as games. to memory. DISPLAY PROCESSING Nexperia Digital Video Platform Picture enhancement, display composition__Once all video The pnx8500 Home Entertainment Engine and graphics data for specific fields or frames has been generated, the video display pipeline processes the images for display. A is the newest IC to comply with the variety of programmable capabilities enable support for a many Nexperia Digital Video Platform (DVP), a different of display systems. Six-tap horizontal/vertical scaling new architectural specification designed for prepares the picture for various display sizes and aspect ratios, including downsampling an HD picture for SD display. Anti- consumer digital video appliances.The flicker filtering can be applied to non-interlaced graphics images. Nexperia DVP architecture enables a family De-interlacing processes an interlaced video signal for display on a progressive scan display device such as a double line-rate TV or of cost-effective, highly programmable, scal- high-resolution PC monitor. Philips-patented Natural Motion™ able devices that maximize hardware and algorithms can improve picture quality through motion estima- software components reuse, reducing devel- tion and compensation. The TM32 CPU can also be programmed to perform additional video enhancements not implemented in opment expense and time to market. hardware. The Nexperia DVP platform defines a bus The pnx8500 supports simultaneous output of two fully indepen- architecture and common bus interfaces. It dent SD video channels, each composited from layers of enhanced video frames, PIPs, menus, cursor, and other graphical informa- seamlessly enables designers to attach one tion. The primary channel is intended for viewing; a secondary or more CPUs, add lower-speed buses for channel can be recorded or viewed in an alternate location. Video peripheral expansion, and connect on-chip is synchronized with audio through timestamping before output for off-chip analog conversion. graphics, communications interfaces, copro- ADVANCED SERVICES cessing blocks as needed to address specific In addition to support for basic STB and DTV applications, a market or application requirements. Pro- variety of advanced TV features and services can be implemented grammable CPU cores allow easy implemen- by upgrading or adding application modules and board-level components. tation of new capabilities and standards as they become available, without changing the The addition of CD-Recordable or hard-disk drives enables per- sonal video recording or time shifting record/playback. Add a silicon. return channel (cable or PSTN modem, DSL, etc.) and applica- tion modules to support interactive services such as Web brows- The Nexperia DVP software architecture ing, shopping, e-mail, TV games, chat rooms, and more. The defines an application layer, middleware such addition of codecs enables IP telephony applications such as as Liberate TV, Microsoft TV, MHP,Media audio and video phones. Highway, and OpenTV, and consistent APIs to shield applications and middleware from media processing and other lower-level ser- vices.With this approach, programmers do not need to know whether a media-process- ing task is implemented in hardware or soft- ware. Once developed, application software can be reused with little to no modifications on other Nexperia DVP-compliant ICs. Architectural Overview Comprehensive trans- port stream decoding, display processing, and a variety of additional functions are supported by two CPU cores and a variety of on-chip hardware accelerators, I/O blocks, and peripherals__all connected through system buses. Compliant with the Philips Nexperia DVP architectural specification, pnx8500 gives set-top and DTV manufacturers the flexibility to reuse pnx8500 hardware designs and software modules. DUAL BUS DESIGN TM32 supports a library of media processing and communica- The pnx8500 uses a high-speed DVP memory bus and dual PI tions application modules. Application library modules needed buses to connect CPUs and on-chip units with each other and to drive core STB and DTV source