PHU97NQ03LT N-Channel Trenchmos Logic Level FET

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PHU97NQ03LT

IPAK N-channel TrenchMOS logic level FET Rev. 02 — 21 December 2010 Product data sheet

1. Product profile

1.1 General description Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. This product is designed and qualified for use in computing, communications, consumer and industrial applications only.

1.2 Features and benefits

Suitable for high frequency Suitable for logic level gate drive applications due to fast switching sources characteristics

1.3 Applications

Computer motherboards

1.4 Quick reference data

Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit

VDS drain-source voltage 25 °C ≤ Tj ≤ 175 °C - - 25 V

ID drain current Tmb =25°C; VGS =10V; --75A see Figure 1; see Figure 3

Ptot total power dissipation Tmb = 25 °C; see Figure 2 --107W Static characteristics

RDSon drain-source on-state VGS =10V; ID =25A; -5.66.6mΩ resistance Tj = 25 °C; see Figure 9; see Figure 10 Dynamic characteristics

QGD gate-drain charge VGS = 4.5 V; ID =25A; -1.9-nC VDS = 12 V; see Figure 11; see Figure 12 NXP Semiconductors PHU97NQ03LT N-channel TrenchMOS logic level FET

2. Pinning information

Table 2. Pinning information Pin Symbol Description Simplified outline Graphic symbol 1 G gate mb D 2 D drain 3Ssource G mb D mounting base; connected to drain mbb076 S

1 2 3 SOT533 (IPAK)

3. Ordering information

Table 3. Ordering information Type number Package Name Description Version PHU97NQ03LT IPAK plastic single-ended package (IPAK); 3 leads (in-line) SOT533

4. Limiting values

Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit

VDS drain-source voltage 25 °C ≤ Tj ≤ 175 °C - 25 V

VDGR drain-gate voltage 25 °C ≤ Tj ≤ 175 °C; RGS =20kΩ -25V

VGS gate-source voltage -20 20 V

ID drain current VGS =10V; Tmb = 100 °C; see Figure 1 -69A

VGS =10V; Tmb =25°C; see Figure 1; -75A see Figure 3

IDM peak drain current pulsed; tp ≤ 10 µs; Tmb =25°C; - 300 A see Figure 3

Ptot total power dissipation Tmb = 25 °C; see Figure 2 - 107 W

Tstg storage temperature -55 175 °C

Tj junction temperature -55 175 °C Source-drain diode

IS source current Tmb =25°C - 75 A

ISM peak source current pulsed; tp ≤ 10 µs; Tmb = 25 °C - 240 A Avalanche ruggedness

EDS(AL)S non-repetitive drain-source VGS =10V; Tj(init) =25°C; ID =35A; -60mJ avalanche energy Vsup ≤ 25 V; unclamped; tp =0.1ms; RGS =50Ω

PHU97NQ03LT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 21 December 2010 2 of 13 NXP Semiconductors PHU97NQ03LT N-channel TrenchMOS logic level FET

003aab533 003aab844 120 120

Ider Pder (%) (%)

80 80

40 40

0 0 050 100 150 200 050 100 150 200 Tj (°C) Tmb (°C)

Fig 1. Normalized continuous drain current as a Fig 2. Normalized total power dissipation as a function of mounting base temperature function of mounting base temperature

003aab556 103

ID (A) RDSon = VDS / ID tp = 10 μs

102

100 μs

DC 10 1 ms

10 ms

1 10−1 1 10 102 VDS (V)

Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage

PHU97NQ03LT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 21 December 2010 3 of 13 NXP Semiconductors PHU97NQ03LT N-channel TrenchMOS logic level FET

5. Thermal characteristics

Table 5. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit

Rth(j-mb) thermal resistance from junction see Figure 4 --1.4K/W to mounting base

Rth(j-a) thermal resistance from junction vertical in still air; SOT533 -70-K/W to ambient package

003aab535 10

Zth(j-mb) (K/W)

1 δ = 0.5

0.2 0.1 tp -1 P δ = 10 0.05 T 0.02 single pulse

tp t T 10-2 10-5 10-4 10-3 10-2 10-1 1 10 tp (s)

Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration

PHU97NQ03LT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 21 December 2010 4 of 13 NXP Semiconductors PHU97NQ03LT N-channel TrenchMOS logic level FET

6. Characteristics

Table 6. Characteristics Symbol Parameter Conditions Min Typ Max Unit Static characteristics

V(BR)DSS drain-source breakdown ID = 250 µA; VGS =0V; Tj =-55°C22--V voltage ID = 250 µA; VGS =0V; Tj =25°C25--V

VGS(th) gate-source threshold voltage ID =1mA; VDS =VGS; Tj =175°C; 0.7--V see Figure 7; see Figure 8

ID =1mA; VDS =VGS; Tj =-55°C; --2.6V see Figure 7; see Figure 8

ID =1mA; VDS =VGS; Tj =25°C; 1.3 1.7 2.15 V see Figure 7; see Figure 8

IDSS drain leakage current VDS =25V; VGS =0V; Tj =25°C--1µA

VDS =25V; VGS =0V; Tj = 175 °C - - 100 µA

IGSS gate leakage current VGS =-16V; VDS =0V; Tj = 25 °C - - 100 nA

VGS =16V; VDS =0V; Tj = 25 °C - - 100 nA

RDSon drain-source on-state VGS =10V; ID =25A; Tj =175°C; - 10.4 12.3 mΩ resistance see Figure 9; see Figure 10

VGS = 4.5 V; ID =25A; Tj =25°C; - 8.3 10.9 mΩ see Figure 9; see Figure 10

VGS =10V; ID =25A; Tj =25°C; -5.66.6mΩ see Figure 9; see Figure 10

RG internal gate resistance (AC) f = 1 MHz - 1.5 - Ω Dynamic characteristics

QG(tot) total gate charge ID =25A; VDS =12V; VGS =4.5V; - 11.7 - nC see Figure 11; see Figure 12

ID =0A; VDS =0V; VGS = 4.5 V - 10.2 - nC

QGS gate-source charge ID =25A; VDS =12V; VGS =4.5V; -6.2-nC see Figure 11; see Figure 12 QGS1 pre-threshold gate-source -3.4-nC charge

QGS2 post-threshold gate-source -2.8-nC charge

QGD gate-drain charge - 1.9 - nC

VGS(pl) gate-source plateau voltage ID =25A; VDS = 12 V; see Figure 11; -3.1-V see Figure 12

Ciss input capacitance VDS =12V; VGS = 0 V; f = 1 MHz; - 1570 - pF Tj = 25 °C; see Figure 13

VDS =0V; VGS =0V; f=1MHz; - 1800 - pF Tj =25°C

Coss output capacitance VDS =12V; VGS = 0 V; f = 1 MHz; - 380 - pF Tj = 25 °C; see Figure 13 Crss reverse transfer capacitance - 160 - pF

td(on) turn-on delay time VDS =12V; RL =0.5Ω; VGS =4.5V; -18-ns RG(ext) =5.6Ω tr rise time - 33 - ns

td(off) turn-off delay time - 20 - ns

tf fall time - 12 - ns

PHU97NQ03LT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 21 December 2010 5 of 13 NXP Semiconductors PHU97NQ03LT N-channel TrenchMOS logic level FET

Table 6. Characteristics …continued Symbol Parameter Conditions Min Typ Max Unit Source-drain diode

VSD source-drain voltage IS =25A; VGS =0V; Tj =25°C; - 0.87 1.2 V see Figure 14

trr reverse recovery time IS =20A; dIS/dt = -100 A/µs; VGS =0V; -38-ns VDS =25V

Qr recovered charge IS =20A; dIS/dt = -100 A/µs; VGS =0V - 14 - nC

003aab536 003aac094 80 80 10 6 5 4.5 4.1 ID ID (A) 3.7 (A) 60 60

3.3 40 40

20 2.9 20 Tj = 175 °C 25 °C

VGS (V) = 2.5 0 0 0 0.2 0.4 0.6 0.8 1 04123 VDS (V) VGS (V)

Fig 5. Output characteristics: drain current as a Fig 6. Transfer characteristics: drain current as a function of drain-source voltage; typical values function of gate-source voltage; typical values

003aab986 003aab938 2.5 10−1

VGS(th) ID (V) (A) 2.0 10−2 max

1.5 10−3 typ min typ max

1.0 min 10−4

0.5 10−5

0.0 10−6 −60060120 180 031 2 Tj (°C) VGS (V)

Fig 7. Gate-source threshold voltage as a function of Fig 8. Sub-threshold drain current as a function of junction temperature gate-source voltage

PHU97NQ03LT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 21 December 2010 6 of 13 NXP Semiconductors PHU97NQ03LT N-channel TrenchMOS logic level FET

003aab467 003aab537 2 25 RDSon a V (V) = 3.3 (mΩ) GS 1.6 20

1.2 15 3.7

0.8 10 4.1 4.5 5 6 0.4 5 10

0 0 −60060120 180 0 20406080 I (A) Tj (°C) D

Fig 9. Normalized drain-source on-state resistance Fig 10. Drain-source on-state resistance as a function factor as a function of junction temperature of drain current; typical values

003aab539 10 V I = 25 A DS VGS D ° (V) Tj = 25 C ID 8

VGS(pl) 6 12 V VDS = 19 V VGS(th)

VGS 4

QGS1 QGS2 Q Q GS GD 2 QG(tot)

003aaa508 0 0102030 QG (nC)

Fig 11. Gate charge waveform definitions Fig 12. Gate-source voltage as a function of gate charge; typical values

PHU97NQ03LT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 21 December 2010 7 of 13 NXP Semiconductors PHU97NQ03LT N-channel TrenchMOS logic level FET

003aab542 003aab541 104 80

IS C (A) (pF) 60

Ciss 103 40

175 °C Tj = 25 °C 20 Coss

Crss 102 0 10-1 1 10 102 0 0.4 0.8 1.2 VDS (V) VSD (V)

Fig 13. Input, output and reverse transfer capacitances Fig 14. Source current as a function of source-drain as a function of drain-source voltage; typical voltage; typical values values

PHU97NQ03LT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 21 December 2010 8 of 13 NXP Semiconductors PHU97NQ03LT N-channel TrenchMOS logic level FET

7. Package outline

Plastic single-ended package (IPAK); 3 leads (in-line) SOT533

E A

E1 A1

mounting base

123

e1 b w M c

0 2.5 5 mm scale

DIMENSIONS (mm are the original dimensions) (2) UNIT A A b cDD E E e e LwL1 Q 1 1 2 1 1 max 2.38 0.93 0.89 0.56 1.10 6.22 6.73 5.21 4.57 2.285 9.6 1.1 mm 2.7 0.3 2.22 0.46 0.71 0.46 0.96 5.98 6.47 5.00 BSC(1) BSC(1) 9.2 1.0

Notes 1. Basic spacing between centers. 2. Terminal dimensions are uncontrolled within zone L1.

OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 05-02-11 SOT533 TO-251 06-02-14

Fig 15. Package outline SOT533 (IPAK)

PHU97NQ03LT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 21 December 2010 9 of 13 NXP Semiconductors PHU97NQ03LT N-channel TrenchMOS logic level FET

8. Revision history

Table 7. Revision history Document ID Release date Data sheet status Change notice Supersedes PHU97NQ03LT v.2 20101221 Product data sheet - PHU97NQ03LT v.1 Modifications: • Various changes to content. PHU97NQ03LT v.1 20080225 Product data sheet - -

PHU97NQ03LT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 21 December 2010 10 of 13 NXP Semiconductors PHU97NQ03LT N-channel TrenchMOS logic level FET

9. Legal information

9.1 Data sheet status

Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

9.2 Definitions Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or Draft — The document is a draft version only. The content is still under safety-critical systems or equipment, nor in applications where failure or internal review and subject to formal approval, which may result in malfunction of an NXP Semiconductors product can reasonably be expected modifications or additions. NXP Semiconductors does not give any to result in personal injury, death or severe property or environmental representations or warranties as to the accuracy or completeness of damage. NXP Semiconductors accepts no liability for inclusion and/or use of information included herein and shall have no liability for the consequences of NXP Semiconductors products in such equipment or applications and use of such information. therefore such inclusion and/or use is at the customer’s own risk.

Short data sheet — A short data sheet is an extract from a full data sheet Quick reference data — The Quick reference data is an extract of the with the same product type number(s) and title. A short data sheet is intended product data given in the Limiting values and Characteristics sections of this for quick reference only and should not be relied upon to contain detailed and document, and as such is not complete, exhaustive or legally binding. full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales Applications — Applications that are described herein for any of these office. In case of any inconsistency or conflict with the short data sheet, the products are for illustrative purposes only. NXP Semiconductors makes no full data sheet shall prevail. representation or warranty that such applications will be suitable for the specified use without further testing or modification. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between Customers are responsible for the design and operation of their applications NXP Semiconductors and its customer, unless NXP Semiconductors and and products using NXP Semiconductors products, and NXP Semiconductors customer have explicitly agreed otherwise in writing. In no event however, accepts no liability for any assistance with applications or customer product shall an agreement be valid in which the NXP Semiconductors product is design. It is customer’s sole responsibility to determine whether the NXP deemed to offer functions and qualities beyond those described in the Semiconductors product is suitable and fit for the customer’s applications and Product data sheet. products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their 9.3 Disclaimers applications and products.

Limited warranty and liability — Information in this document is believed to NXP Semiconductors does not accept any liability related to any default, be accurate and reliable. However, NXP Semiconductors does not give any damage, costs or problem which is based on any weakness or default in the representations or warranties, expressed or implied, as to the accuracy or customer’s applications or products, or the application or use by customer’s completeness of such information and shall have no liability for the third party customer(s). Customer is responsible for doing all necessary consequences of use of such information. testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and In no event shall NXP Semiconductors be liable for any indirect, incidental, the products or of the application or use by customer’s third party punitive, special or consequential damages (including - without limitation - lost customer(s). NXP does not accept any liability in this respect. profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such Limiting values — Stress above one or more limiting values (as defined in damages are based on tort (including negligence), warranty, breach of the Absolute Maximum Ratings System of IEC 60134) will cause permanent contract or any other legal theory. damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in Notwithstanding any damages that customer might incur for any reason the Recommended operating conditions section (if present) or the whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards Characteristics sections of this document is not warranted. Constant or customer for the products described herein shall be limited in accordance repeated exposure to limiting values will permanently and irreversibly affect with the Terms and conditions of commercial sale of NXP Semiconductors. the quality and reliability of the device.

Right to make changes — NXP Semiconductors reserves the right to make Terms and conditions of commercial sale — NXP Semiconductors changes to information published in this document, including without products are sold subject to the general terms and conditions of commercial limitation specifications and product descriptions, at any time and without sale, as published at http://www.nxp.com/profile/terms, unless otherwise notice. This document supersedes and replaces all information supplied prior agreed in a valid written individual agreement. In case an individual to the publication hereof. agreement is concluded only the terms and conditions of the respective

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agreement shall apply. NXP Semiconductors hereby expressly objects to product for such automotive applications, use and specifications, and (b) applying the customer’s general terms and conditions with regard to the whenever customer uses the product for automotive applications beyond purchase of NXP Semiconductors products by customer. NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any No offer to sell or license — Nothing in this document may be interpreted or liability, damages or failed product claims resulting from customer design and construed as an offer to sell products that is open for acceptance or the grant, use of the product for automotive applications beyond NXP Semiconductors’ conveyance or implication of any license under any copyrights, patents or standard warranty and NXP Semiconductors’ product specifications. other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein may 9.4 Trademarks be subject to export control regulations. Export might require a prior authorization from national authorities. Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, Adelante, Bitport, Bitsound, CoolFlux, CoReUse, DESFire, EZ-HV, the product is not suitable for automotive use. It is neither qualified nor tested FabKey, GreenChip, HiPerSmart, HITAG, I²C-bus logo, ICODE, I-CODE, in accordance with automotive testing or application requirements. NXP ITEC, Labelution, MIFARE, MIFARE Plus, MIFARE Ultralight, MoReUse, Semiconductors accepts no liability for inclusion and/or use of QLPAK, Silicon Tuner, SiliconMAX, SmartXA, STARplug, TOPFET, non-automotive qualified products in automotive equipment or applications. TrenchMOS, TriMedia and UCODE — are trademarks of NXP B.V.

In the event that customer uses the product for design-in and use in HD Radio and HD Radio logo — are trademarks of iBiquity Digital automotive applications to automotive specifications and standards, customer Corporation. (a) shall use the product without NXP Semiconductors’ warranty of the

10. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: [email protected]

PHU97NQ03LT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 21 December 2010 12 of 13 NXP Semiconductors PHU97NQ03LT N-channel TrenchMOS logic level FET

11. Contents

1 Product profile ...... 1 1.1 General description ...... 1 1.2 Features and benefits...... 1 1.3 Applications ...... 1 1.4 Quick reference data ...... 1 2 Pinning information...... 2 3 Ordering information...... 2 4 Limiting values...... 2 5 Thermal characteristics ...... 4 6 Characteristics...... 5 7 Package outline ...... 9 8 Revision history...... 10 9 Legal information...... 11 9.1 Data sheet status ...... 11 9.2 Definitions...... 11 9.3 Disclaimers ...... 11 9.4 Trademarks...... 12 10 Contact information...... 12

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.

© NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 21 December 2010 Document identifier: PHU97NQ03LT