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PHU97NQ03LT N-Channel Trenchmos Logic Level FET

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PHU97NQ03LT N-Channel Trenchmos Logic Level FET Important notice Dear Customer, On 7 February 2017 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS semiconductors with its focus on the automotive, industrial, computing, consumer and wearable application markets In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below. Instead of http://www.nxp.com, http://www.philips.com/ or http://www.semiconductors.philips.com/, use http://www.nexperia.com Instead of [email protected] or [email protected], use [email protected] (email) Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on the version, as shown below: - © NXP N.V. (year). All rights reserved or © Koninklijke Philips Electronics N.V. (year). All rights reserved Should be replaced with: - © Nexperia B.V. (year). All rights reserved. If you have any questions related to the data sheet, please contact our nearest sales office via e-mail or telephone (details via [email protected]). Thank you for your cooperation and understanding, Kind regards, Team Nexperia PHU97NQ03LT IPAK N-channel TrenchMOS logic level FET Rev. 02 — 21 December 2010 Product data sheet 1. Product profile 1.1 General description Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. This product is designed and qualified for use in computing, communications, consumer and industrial applications only. 1.2 Features and benefits Suitable for high frequency Suitable for logic level gate drive applications due to fast switching sources characteristics 1.3 Applications Computer motherboards 1.4 Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage 25 °C ≤ Tj ≤ 175 °C - - 25 V ID drain current Tmb =25°C; VGS =10V; --75A see Figure 1; see Figure 3 Ptot total power dissipation Tmb = 25 °C; see Figure 2 --107W Static characteristics RDSon drain-source on-state VGS =10V; ID =25A; -5.66.6mΩ resistance Tj = 25 °C; see Figure 9; see Figure 10 Dynamic characteristics QGD gate-drain charge VGS = 4.5 V; ID =25A; -1.9-nC VDS = 12 V; see Figure 11; see Figure 12 NXP Semiconductors PHU97NQ03LT N-channel TrenchMOS logic level FET 2. Pinning information Table 2. Pinning information Pin Symbol Description Simplified outline Graphic symbol 1 G gate mb D 2 D drain 3Ssource G mb D mounting base; connected to drain mbb076 S 1 2 3 SOT533 (IPAK) 3. Ordering information Table 3. Ordering information Type number Package Name Description Version PHU97NQ03LT IPAK plastic single-ended package (IPAK); 3 leads (in-line) SOT533 4. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage 25 °C ≤ Tj ≤ 175 °C - 25 V VDGR drain-gate voltage 25 °C ≤ Tj ≤ 175 °C; RGS =20kΩ -25V VGS gate-source voltage -20 20 V ID drain current VGS =10V; Tmb = 100 °C; see Figure 1 -69A VGS =10V; Tmb =25°C; see Figure 1; -75A see Figure 3 IDM peak drain current pulsed; tp ≤ 10 µs; Tmb =25°C; - 300 A see Figure 3 Ptot total power dissipation Tmb = 25 °C; see Figure 2 - 107 W Tstg storage temperature -55 175 °C Tj junction temperature -55 175 °C Source-drain diode IS source current Tmb =25°C - 75 A ISM peak source current pulsed; tp ≤ 10 µs; Tmb = 25 °C - 240 A Avalanche ruggedness EDS(AL)S non-repetitive drain-source VGS =10V; Tj(init) =25°C; ID =35A; -60mJ avalanche energy Vsup ≤ 25 V; unclamped; tp =0.1ms; RGS =50Ω PHU97NQ03LT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 21 December 2010 2 of 13 NXP Semiconductors PHU97NQ03LT N-channel TrenchMOS logic level FET 003aab533 003aab844 120 120 Ider Pder (%) (%) 80 80 40 40 0 0 050 100 150 200 050 100 150 200 Tj (°C) Tmb (°C) Fig 1. Normalized continuous drain current as a Fig 2. Normalized total power dissipation as a function of mounting base temperature function of mounting base temperature 003aab556 103 ID (A) RDSon = VDS / ID tp = 10 μs 102 100 μs DC 10 1 ms 10 ms 1 10−1 1 10 102 VDS (V) Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage PHU97NQ03LT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 21 December 2010 3 of 13 NXP Semiconductors PHU97NQ03LT N-channel TrenchMOS logic level FET 5. Thermal characteristics Table 5. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Rth(j-mb) thermal resistance from junction see Figure 4 --1.4K/W to mounting base Rth(j-a) thermal resistance from junction vertical in still air; SOT533 -70-K/W to ambient package 003aab535 10 Zth(j-mb) (K/W) 1 δ = 0.5 0.2 0.1 tp -1 P δ = 10 0.05 T 0.02 single pulse tp t T 10-2 10-5 10-4 10-3 10-2 10-1 1 10 tp (s) Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration PHU97NQ03LT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 21 December 2010 4 of 13 NXP Semiconductors PHU97NQ03LT N-channel TrenchMOS logic level FET 6. Characteristics Table 6. Characteristics Symbol Parameter Conditions Min Typ Max Unit Static characteristics V(BR)DSS drain-source breakdown ID = 250 µA; VGS =0V; Tj =-55°C22--V voltage ID = 250 µA; VGS =0V; Tj =25°C25--V VGS(th) gate-source threshold voltage ID =1mA; VDS =VGS; Tj =175°C; 0.7--V see Figure 7; see Figure 8 ID =1mA; VDS =VGS; Tj =-55°C; --2.6V see Figure 7; see Figure 8 ID =1mA; VDS =VGS; Tj =25°C; 1.3 1.7 2.15 V see Figure 7; see Figure 8 IDSS drain leakage current VDS =25V; VGS =0V; Tj =25°C--1µA VDS =25V; VGS =0V; Tj = 175 °C - - 100 µA IGSS gate leakage current VGS =-16V; VDS =0V; Tj = 25 °C - - 100 nA VGS =16V; VDS =0V; Tj = 25 °C - - 100 nA RDSon drain-source on-state VGS =10V; ID =25A; Tj =175°C; - 10.4 12.3 mΩ resistance see Figure 9; see Figure 10 VGS = 4.5 V; ID =25A; Tj =25°C; - 8.3 10.9 mΩ see Figure 9; see Figure 10 VGS =10V; ID =25A; Tj =25°C; -5.66.6mΩ see Figure 9; see Figure 10 RG internal gate resistance (AC) f = 1 MHz - 1.5 - Ω Dynamic characteristics QG(tot) total gate charge ID =25A; VDS =12V; VGS =4.5V; - 11.7 - nC see Figure 11; see Figure 12 ID =0A; VDS =0V; VGS = 4.5 V - 10.2 - nC QGS gate-source charge ID =25A; VDS =12V; VGS =4.5V; -6.2-nC see Figure 11; see Figure 12 QGS1 pre-threshold gate-source -3.4-nC charge QGS2 post-threshold gate-source -2.8-nC charge QGD gate-drain charge - 1.9 - nC VGS(pl) gate-source plateau voltage ID =25A; VDS = 12 V; see Figure 11; -3.1-V see Figure 12 Ciss input capacitance VDS =12V; VGS = 0 V; f = 1 MHz; - 1570 - pF Tj = 25 °C; see Figure 13 VDS =0V; VGS =0V; f=1MHz; - 1800 - pF Tj =25°C Coss output capacitance VDS =12V; VGS = 0 V; f = 1 MHz; - 380 - pF Tj = 25 °C; see Figure 13 Crss reverse transfer capacitance - 160 - pF td(on) turn-on delay time VDS =12V; RL =0.5Ω; VGS =4.5V; -18-ns RG(ext) =5.6Ω tr rise time - 33 - ns td(off) turn-off delay time - 20 - ns tf fall time - 12 - ns PHU97NQ03LT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 21 December 2010 5 of 13 NXP Semiconductors PHU97NQ03LT N-channel TrenchMOS logic level FET Table 6. Characteristics …continued Symbol Parameter Conditions Min Typ Max Unit Source-drain diode VSD source-drain voltage IS =25A; VGS =0V; Tj =25°C; - 0.87 1.2 V see Figure 14 trr reverse recovery time IS =20A; dIS/dt = -100 A/µs; VGS =0V; -38-ns VDS =25V Qr recovered charge IS =20A; dIS/dt = -100 A/µs; VGS =0V - 14 - nC 003aab536 003aac094 80 80 10 6 5 4.5 4.1 ID ID (A) 3.7 (A) 60 60 3.3 40 40 20 2.9 20 Tj = 175 °C 25 °C VGS (V) = 2.5 0 0 0 0.2 0.4 0.6 0.8 1 04123 VDS (V) VGS (V) Fig 5. Output characteristics: drain current as a Fig 6. Transfer characteristics: drain current as a function of drain-source voltage; typical values function of gate-source voltage; typical values 003aab986 003aab938 2.5 10−1 VGS(th) ID (V) (A) 2.0 10−2 max 1.5 10−3 typ min typ max 1.0 min 10−4 0.5 10−5 0.0 10−6 −60060120 180 031 2 Tj (°C) VGS (V) Fig 7. Gate-source threshold voltage as a function of Fig 8. Sub-threshold drain current as a function of junction temperature gate-source voltage PHU97NQ03LT All information provided in this document is subject to legal disclaimers.
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