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Qoriq LS1043A, LS1023A Data Sheet

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Qoriq LS1043A, LS1023A Data Sheet NXP Semiconductors Document Number LS1043A Data Sheet: Technical Data Rev. 4.1, 08/2019 LS1043A QorIQ LS1043A, LS1023A Data Sheet Features • Four SerDes lanes for high-speed peripheral interfaces – Three PCI Express 2.0 controllers supporting x4 • LS1043A contains 32-bit /64-bit Arm® Cortex®-A53 operation MPCore Processor with the following capabilities: – One Serial ATA (SATA 3.0) controller – Speed up to 1.6 GHz – Up to four SGMII supporting 1000 Mbit/s – 32 KB L1 Instruction Cache w/parity – Up to two SGMII supporting 2500 Mbit/s – 32 KB L1 Data Cache w/ECC – Up to one XFI (10 GbE) interface – Neon SIMD Co-processor – Up to one QSGMII – Arm v8 Cryptography Extensions – Supports 1000Base-KX • 1 MB unified I/D L2 Cache w/ECC • Additional peripheral interfaces • Hierarchical interconnect fabric – One Quad Serial Peripheral Interface (QSPI) – Hardware Managed Data coherency controller, one Deserial Serial Peripheral Interface – Up to 400 MHz operation (DSPI) controller – Integrated Flash Controller (IFC) supporting NAND • One 32-bit DDR3L/DDR4 SDRAM memory controller and NOR flash with 28-bit addressing and 16-bit – ECC and interleaving support data – Up to 1.6 GT/s – Three USB 3.0 controllers with integrated PHY • Data Path Acceleration Architecture (DPAA) – Enhanced Secure Digital Host Controller (eSDHC) incorporating acceleration for the following functions: supporting SD 3.0, eMMC 4.4, and eMMC 4.5 – Packet parsing, classification, and distribution modes (FMan) – uQE supporting TDM/HDLC – Queue management for scheduling, packet – Four I2C controllers sequencing, and congestion management (QMan) – Two 16550 compliant DUARTs and six low-power – Hardware buffer management for buffer allocation UARTs (LPUARTs) and de-allocation (BMan) – General Purpose IO (GPIO), eight Flextimers, five – Cryptography acceleration (SEC) Watchdog timer, four independent PWM/counters/ timer • Parallel Ethernet interfaces – Trust Architecture – Up to two RGMII interfaces – Debug supporting run control, data acquisition, – IEEE 1588 support high-speed trace, and performance/event monitoring NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products. Table of Contents 1 Introduction.......................................................................................... 3 3.17 Flextimer interface.....................................................................181 2 Pin assignments....................................................................................4 3.18 SPI interface.............................................................................. 184 2.1 621 ball layout diagrams........................................................... 4 3.19 QuadSPI interface......................................................................187 2.2 Pinout list (21x21)..................................................................... 10 3.20 Enhanced secure digital host controller (eSDHC).....................189 2.3 780 ball layout diagrams........................................................... 48 3.21 JTAG controller.........................................................................198 2.4 Pinout list...................................................................................54 3.22 I2C interface.............................................................................. 201 3 Electrical characteristics.......................................................................96 3.23 GPIO interface...........................................................................204 3.1 Overall DC electrical characteristics.........................................96 3.24 GIC interface............................................................................. 208 3.2 Power sequencing......................................................................104 3.25 High-speed serial interfaces (HSSI).......................................... 210 3.3 Power down requirements......................................................... 106 4 Hardware design considerations...........................................................232 3.4 Power characteristics.................................................................107 4.1 System clocking........................................................................ 232 3.5 Low power mode saving estimation..........................................110 4.2 Connection recommendations................................................... 242 3.6 I/O power dissipation................................................................ 111 5 Thermal................................................................................................ 247 3.7 Power-on ramp rate................................................................... 113 5.1 Recommended thermal model...................................................249 3.8 Input clocks............................................................................... 114 5.2 Temperature diode.....................................................................249 3.9 RESET initialization..................................................................121 5.3 Thermal management information............................................ 249 3.10 DDR4 and DDR3L SDRAM controller.................................... 121 6 Package information.............................................................................252 3.11 Ethernet interface, Ethernet management interface, IEEE Std 6.1 Package parameters for the FC-PBGA......................................252 1588........................................................................................... 128 6.2 Mechanical dimensions of the FC-PBGA................................. 252 3.12 QUICC engine specifications....................................................152 7 Security fuse processor.........................................................................255 3.13 USB 3.0 interface...................................................................... 157 8 Ordering information............................................................................255 3.14 Integrated Flash Controller........................................................161 8.1 Part numbering nomenclature....................................................255 3.15 LPUART interface.....................................................................178 8.2 Part marking ............................................................................. 256 3.16 DUART interface...................................................................... 180 9 Revision history....................................................................................257 QorIQ LS1043A, LS1023A Data Sheet, Rev. 4.1, 08/2019 2 NXP Semiconductors Introduction 1 Introduction LS1043A is a cost-effective, power-efficient, and highly integrated system-on-chip (SoC) design that extends the reach of the NXP value-performance line of QorIQ communications processors. Featuring extremely power-efficient 64-bit Arm® Cortex®- A53 cores with ECC-protected L1 and L2 cache memories for high reliability, running up to 1.6 GHz. This chip can be used for networking and wireless access points, industrial gateways, industrial automation, M2M for enterprise, consumer networking and router applications. The figure shown below represents the block diagram of the LS1043A chip. ® ® Arm CortexARM Cortex--A53 64-bitARM Core Cortex- A53 64b Cores A53 ARM64b Cores Cortex- A53ARM 64b Cortex- Cores 32 KB 32 KB 32 KB A53 64b32 Cores KB D-Cache32 KB I-Cache32 KB D-Cache I-Cache D-Cache32 KB I-Cache32 KB 32-bit D-Cache I-Cache DDR3L/4 Memory Controller 1 MB L2 - Cache Secure Boot Trust Zone CCI-400™ Coherency Fabric Power Management SMMUs IFC, QuadSPI, SPI Security Real Time Debug SD/SDIO/eMMC Queue Frame Manager Engine Manager DMA (SEC) Parse, classify, Watchpoint Cross 2x DUART distribute Trigger 4x I2C, 4x GPIO 3.0 SATA QUICC Engine QUICC Perf PCI Express 2.0 PCI Express PCI Express 2.0 PCI Express PCI Express 2.0 PCI Express Trace Buffer 1G 1G 1G 1/2.5G Monitor 8x FlexTimer Manager 1G 1G 1/2.5/10G 3x USB3.0 w/PHY DPAA Hardware 6x LPUART 4-Lane, 10 GHz SerDes Core Complex Accelerators and Memory Control Basic Peripherals, Interconnect and Debug Networking Elements Figure 1. LS1043A Block Diagram The figure shown below represents the block diagram of the LS1023A chip. QorIQ LS1043A, LS1023A Data Sheet, Rev. 4.1, 08/2019 NXP Semiconductors 3 Pin assignments ® ® Arm ARMCortex Cortex--A53 64-bitARM Core Cortex- A53 64b Cores A53 ARM64b Cores Cortex- A53ARM 64b Cortex- Cores 32 KB 32 KB 32 KB A53 64b32 Cores KB D-Cache3232 KBKB I-Cache3232 KBKB D-Cache I-Cache 32-bit D-CacheD-Cache I-CacheI-Cache DDR3L/4 Memory Controller 1 MB L2 - Cache Secure Boot Trust Zone CCI-400™ Coherency Fabric Power Management SMMUs IFC, QuadSPI, SPI Security Real Time Debug SD/SDIO/eMMC Queue Frame Manager Engine Manager DMA (SEC) Parse, classify, Watchpoint Cross 2x DUART distribute Trigger PCI Express 2.0 PCI Express PCI Express 2.0 PCI Express PCI Express 2.0 PCI Express 4x I2C, 4x GPIO 3.0 SATA QUICC Engine QUICC Perf Trace Buffer 1G 1G 1G 1/2.5G Monitor 8x FlexTimer Manager 1G 1G 1/2.5/10G 3x USB3.0 w/PHY DPAA Hardware 6x LPUART 4-Lane 10 GHz SerDes Core Complex Accelerators and Memory Control Basic Peripherals, Interconnect and Debug Networking Elements Figure 2. LS1023A Block Diagram 2 Pin assignments This section describes the ball map diagram and pin list table for both 21x21 and 23x23 packages of LS1043A. 2.1 621 ball layout
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