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Die Virtuelle Plattform: Der Einsatz Von Zynq Fuer Die Verifikation Und Das Debugging Von Konfigurierbaren Systemen
Die virtuelle Plattform: Der Einsatz von Zynq fuer die Verifikation und das Debugging von konfigurierbaren Systemen Dr. Endric Schubert Missing Link Electronics Marlene-Dietrich-Straße 5 89231 Neu-Ulm www.missinglinkelectronics.com Tel: +49 (731) 141-149-0 Courtesy Xilinx 1 Challenges of Debugging Your Own ASSP © Missing Link Electronics 12. Juli 2012 2 Another Challenge When Building Your Own ASSP: Making Hardware and Software Work Together. © Missing Link Electronics 12. Juli 2012 3 ASSP System-on-Chip Design – An Embedded Designers Life © Missing Link Electronics 12. Juli 2012 4 What is a Virtual Platform? © Missing Link Electronics 12. Juli 2012 5 Virtual Platform Methodology © Missing Link Electronics 12. Juli 2012 6 Virtual Platforms Can Run Software Fast (Sometimes Faster Than Real) © Missing Link Electronics 12. Juli 2012 7 What is SystemC? Open Source Library managed by Open SystemC Initiative (OSCI) Extension to ISO C++ www.systemc.org Means to express concurrency Communication mechanisms Reactivity Concept of Time Current members: ARM Ltd. Cadence Design Systems, Inc. CoWare, Inc. Forte Design Systems Intel Event driven simulation kernel Corporation Mentor Graphics Corporation NXP Semiconductors STMicroelectronics Synopsys, Inc. Actis Design, LLC Atrenta, Inc. Bluespec, Inc. Broadcom - A modeling methodology Corporation Calypto Design Systems, Inc. Canon Inc. Carbon Design Systems Celoxica Ltd. ChipVision Design Systems AG Denali Software Inc. Doulos Ltd. ESLX, Inc. Fraunhofer Institute for Integrated Circuits Freescale Semiconductor Inc. GreenSocs Ltd. Industrial Technology Research Institute (ITRI) JEDA Technologies Inc. Infineon Technologies AG NEC Corporation Semiconductor Technology Academic Research Center (STARC) SpringSoft, Inc. Synfora Inc. Tenison EDA VaST Systems Technology Corporation © Missing Link Electronics 12. -
Oriented Conferences Four Solutions
Delivering Solutions and Technology to the World’s Design Engineering Community Four Solutions- Oriented Conferences • System-on-Chip Design Conference • IP World Forum • High-Performance System Design Conference • Wireless and Optical Broadband Design Conference Special Technology Focus Areas January 29 – February 1, 2001 • Internet and Information Exhibits: January 30–31, 2001 Appliance Design Santa Clara Convention Center • Embedded Design Santa Clara, California • RF, Optical, and Analog Design NEW! • IEC Executive Forum International Engineering Register by January 5 and Consortium save $100 – and be entered to win www.iec.org a Palm Pilot! Practical Design Solutions Practical design-engineering solutions presented by practicing engineers—The DesignCon reputation of excellence has been built largely by the practical nature of its sessions. Design engineers hand selected by our team of professionals provide you with the best electronic design and silicon-solutions information available in the industry. DesignCon provides attendees with DesignCon has an established reputation for the high design solutions from peers and professionals. quality of its papers and its expert-level speakers from Silicon Valley and around the world. Each year more than 100 industry pioneers bring to light the design-engineering solutions that are on the leading edge of technology. This elite group of design engineers presents unique case studies, technology innovations, practical techniques, design tips, and application overviews. Who Should Attend Any professionals who need to stay on top of current information regarding design-engineering theories, The most complete educational experience techniques, and application strategies should attend this in the industry conference. DesignCon attracts engineers and allied The four conference options of DesignCon 2001 provide a professionals from all levels and disciplines. -
Download the Compiled Program File Onto the Chip
International Journal of Computer Science & Information Technology (IJCSIT) Vol 4, No 2, April 2012 MPP SOCGEN: A FRAMEWORK FOR AUTOMATIC GENERATION OF MPP SOC ARCHITECTURE Emna Kallel, Yassine Aoudni, Mouna Baklouti and Mohamed Abid Electrical department, Computer Embedded System Laboratory, ENIS School, Sfax, Tunisia ABSTRACT Automatic code generation is a standard method in software engineering since it improves the code consistency and reduces the overall development time. In this context, this paper presents a design flow for automatic VHDL code generation of mppSoC (massively parallel processing System-on-Chip) configuration. Indeed, depending on the application requirements, a framework of Netbeans Platform Software Tool named MppSoCGEN was developed in order to accelerate the design process of complex mppSoC. Starting from an architecture parameters design, VHDL code will be automatically generated using parsing method. Configuration rules are proposed to have a correct and valid VHDL syntax configuration. Finally, an automatic generation of Processor Elements and network topologies models of mppSoC architecture will be done for Stratix II device family. Our framework improves its flexibility on Netbeans 5.5 version and centrino duo Core 2GHz with 22 Kbytes and 3 seconds average runtime. Experimental results for reduction algorithm validate our MppSoCGEN design flow and demonstrate the efficiency of generated architectures. KEYWORD MppSoC, Automatic code generation; mppSoC configuration;parsing ; MppSoCGEN; 1. INTRODUCTION Parallel machines are most often used in many modern applications that need regular parallel algorithms and high computing resources, such as image processing and signal processing. Massively parallel architectures, in particular Single Instruction Multiple Data (SIMD) systems, have shown to be powerful executers for data-intensive applications [1]. -
ECD.June.2013.Pdf
-community Post Joining the embedded conversation -community Post Joining the embedded conversation ON THE COVER Embedded Computing Design editors have been on the lookout for this year’s Top Embedded Innovators, and – for the first time this year -– thecommunity Most Influential Women in Post Embedded. Our two contests pulled in many inspirational, www.embedded-computing.com highly qualified candidatesJoining who are theforging embedded new ideas conversation and making a difference in the embedded industry. Read June 2013 | Volume 11 • Number 4 about the winners in this edition’s exclusive Q&As, and check out the nominees for Most Innovative Product, winners to be announced in our August edition. 7 Tracking Trends in Embedded Technology 54 -community Post Top Innovators streamline embedded technology Joining the embedded conversation By Warren Webb By Sharon Hess Silicon Software Strategies Multicore processors Finding an operating system Small form factors 8 24 31 Moving target: EEMBC evolves ▲ Choose the right ▲ VPX helps programmable 28 its benchmark suites to keep pace embedded operating system field of dreams become reality with the multicore revolution By Warren Webb By Kevin Roth, Alpha Data Q&A with Markus Levy, Founder and President of EEMBC Case study: 31 Challenges in incarnating a ARM’s big.LITTLE 11 EXPERT PANEL: 14 credit card sized SBC architecture aims to satisfy the Is EDA as easy as By Pete Lomas, Raspberry Pi hunger for power 1, 2, 3 these days? Q&A with John Goodacre, Director, Roundtable discussion with Wally Rhines, Chairman Technology and Systems, ARM Processor Division and CEO, Mentor Graphics; Brett Cline, Vice President, Forte Design Systems; Marc Serughetti, Business Development Director, Synopsys; Michał Siwinski,´ Director of Product Marketing at Cadence; Bill Neifert, 52 Cofounder and CTO, Carbon Design Systems Editor’s Choice By Sharon Hess Top Embedded Innovators Josh Lee, Cofounder, President, and CEO at Uniquify 34 Darren Humphrey, Sr. -
Inside Chips
InsideChips.VenturesTM Tracking Fabless, IP & Design-House Startups Volume 6, Number 7 July 2005 Business Microscope 3-D Chip Trends … For more than 30 years, the yearly conference explores market and technology chipmakers have been riding the Moore’s Law speed opportunities in the 3-D space. and performance wave. Without fail, they have been Universities, institutes/consortia, IDMs and a able to rely on reductions in transistor size used in ICs handful of startups are conducting 3-D research to achieve predicted increases in speed and around the world. Table 1 (page 2) highlights the performance. Moore’s Law, which states that chip notable players. DARPA funds most of the university performance doubles approximately every two years, programs in the U.S. held true because the RC delay has been negligible in comparison with signal propagation delay. For Initial 3-D efforts involved package stacking or submicron technology, however, RC delay becomes chip stacking in a single package with wire bond a dominant factor. As the industry moves to submicron feature interconnects. Amkor is a good illustration of this approach. sizes, shrinking two-dimensional chips will become problematic. Begun in 1998, the technology was primarily used for memory stacks. One emerging solution is 3-D integration. The technology is not new but it is becoming increasingly important as researchers One of the early pioneers of 3-D, Irvine Sensors, developed look for solutions beyond the perceived limits of today’s two- stacked chips in which the connections are made over the edge of dimensional devices. the die. One limitation, however, is that all die must be the same size. -
An Introduction to High-Level Synthesis
High-Level Synthesis An Introduction to High-Level Synthesis Philippe Coussy Michael Meredith Universite´ de Bretagne-Sud, Lab-STICC Forte Design Systems Daniel D. Gajski Andres Takach University of California, Irvine Mentor Graphics today would even think of program- Editor’s note: ming a complex software application High-level synthesis raises the design abstraction level and allows rapid gener- solely by using an assembly language. ation of optimized RTL hardware for performance, area, and power require- In the hardware domain, specification ments. This article gives an overview of state-of-the-art HLS techniques and languages and design methodologies tools. 1,2 ÀÀTim Cheng, Editor in Chief have evolved similarly. For this reason, until the late 1960s, ICs were designed, optimized, and laid out by hand. Simula- THE GROWING CAPABILITIES of silicon technology tion at the gate level appeared in the early 1970s, and and the increasing complexity of applications in re- cycle-based simulation became available by 1979. Tech- cent decades have forced design methodologies niques introduced during the 1980s included place-and- and tools to move to higher abstraction levels. Raising route, schematic circuit capture, formal verification, the abstraction levels and accelerating automation of and static timing analysis. Hardware description lan- both the synthesis and the verification processes have guages (HDLs), such as Verilog (1986) and VHDL for this reason always been key factors in the evolu- (1987), have enabled wide adoption of simulation tion of the design process, which in turn has allowed tools. These HDLs have also served as inputs to logic designers to explore the design space efficiently and synthesis tools leading to the definition of their synthe- rapidly. -
Organising Committees
DATE 2005 Executive Committee GENERAL CHAIR PROGRAMME CHAIR Nobert Wehn Luca Benini Kaiserslautern U, DE DEIS – Bologna U, IT VICE CHAIR & PAST PROG. CHAIR VICE PROGRAMME CHAIR Georges Gielen Donatella Sciuto KU Leuven, BE Politecnico di Milano, IT FINANCE CHAIR PAST GENERAL CHAIR Rudy Lauwereins Joan Figueras IMEC, Leuven, BE UP Catalunya, Barcelona, ES DESIGNERS’ FORUM DESIGNERS’ FORUM Menno Lindwer Christoph Heer Philips, Eindhoven, NL Infineon, Munich, DE SPECIAL SESSIONS & DATE REP AT DAC FRIDAY WORKSHOPS Ahmed Jerraya Bashir Al-Hashimi TIMA, Grenoble, FR Southampton U, UK INTERACTIVE PRESENTATIONS ELECTRONIC REVIEW Eugenio Villar Wolfgang Mueller Cantabria U, ES Paderborn U, DE WEB MASTER AUDIO VISUAL Udo Kebschull Jaume Segura Heidelberg U, DE Illes Baleares U, ES TUTORIALS & MASTER COURSES FRINGE MEETINGS Enrico Macii Michel Renovell Politecnico di Torino, IT LIRMM, Montpellier, FR AUTOMOTIVE DAY BIOCHIPS DAY Juergen Bortolazzi Christian Paulus DaimlerChrysler, DE Infineon, Munich, DE PROCEEDINGS EXHIBITION PROGRAMME Christophe Bobda Juergen Haase Erlangen U, DE edacentrum, Hannover, DE UNIVERSITY BOOTH UNIVERSITY BOOTH & ICCAD Volker Schoeber REPRESENTATIVE edacentrum, Hannover, DE Wolfgang Rosenstiel Tuebingen U/FZI, DE AWARDS & DATE REP. AT ASPDAC PCB SYMPOSIUM Peter Marwedel Rainer Asfalg Dortmund U, DE Mentor Graphics, DE TRAVEL GRANTS COMMUNICATIONS Marta Rencz Bernard Courtois TU Budapest, HU TIMA, Grenoble, FR LOCAL ARRANGEMENTS PRESS LIASON Volker Dueppe Fred Santamaria Siemens, DE Infotest, Paris, FR ESF CHAIR & EDAA -
Xcell Journal Issue 50, Fall 2004
ISSUE 50, FALL 2004ISSUE 50, FALL XCELL JOURNAL XILINX, INC. Issue 50 Fall 2004 XcellXcelljournaljournal THETHE AUTHORITATIVEAUTHORITATIVE JOURNALJOURNAL FORFOR PROGRAMMABLEPROGRAMMABLE LOGICLOGIC USERSUSERS MEMORYMEMORY DESIGNDESIGN Streaming Data at 10 Gbps Control Your QDR Designs PARTNERSHIP 20 Years of Partnership Author! Author! Programmable WorldWorld 20042004 SOFTWARE Algorithmic C Synthesis The Need for Speed MANUFACTURING Lower PCB Mfg. Costs Optimize PCB Routability R COVER STORY FPGAs on Mars The New SPARTAN™-3 Make It You r ASIC The world’s lowest-cost FPGAs Spartan-3 Platform FPGAs deliver everything you need at the price you want. Leading the way in 90nm process technology, the new Spartan-3 devices are driving down costs in a huge range of high-capability, cost-sensitive applications. With the industry’s widest density range in its class — 50K to 5 Million gates — the Spartan-3 family gives you unbeatable value and flexibility. Lots of features … without compromising on price Check it out. You get 18x18 embedded multipliers for XtremeDSP™ processing in a low-cost FPGA. Our unique staggered pad technology delivers a ton of I/Os for total connectivity solutions. Plus our XCITE technology improves signal integrity, while eliminating hundreds of resistors to simplify board layout and reduce your bill of materials. With the lowest cost per I/O and lowest cost per logic cell, Spartan-3 Platform FPGAs are the perfect fit for any design … and any budget. MAKE IT YOUR ASIC The Programmable Logic CompanySM For more information visit www.xilinx.com/spartan3 Pb-free devices available now ©2004 Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124. -
Using Systemc for High-Level Synthesis and Integration with TLM
Using SystemC for high-level synthesis and integration with TLM Presented at India SystemC User Group (ISCUG) http://www.iscug.in April 14, 2013 Mike Meredith – VP Strategic Marketing Forte Design Systems © 2013 Forte Design Systems Agenda • High-level synthesis • Keys to raising abstraction level – A brief history of high-level – Implicit state machine synthesis vs explicit state machine – What is HLS? – Design exploration – HLS Basics – HLS and Arrays • Synthesizability – HLS and I/O protocols – Introduction to the • Integrating synthesizable code synthesizable subset standard in TLM models draft • User Experience – Recommendations and extensions © 2013 Forte Design Systems 2 A Brief History Of High-level Synthesis © 2013 Forte Design Systems 3 What’s In A Name? Algorithmic Behavioral Synthesis Synthesis ESL Synthesis High-level Synthesis © 2013 Forte Design Systems 4 Synthesizing Hardware From A High-level Description -- Not a New Idea! Generation 0 Generation 1 Generation 2 Research First Industrial Tools C-based Tools 1970’s 1980’s 1990’s 2000’s Today • Generation 0 - Research – 1970’s - 1990 – First mention (that I can find) - 1974 • CMU: Barbacci, Siewiorek “Some aspects of the symbolic manipulation of computer descriptions” – A sampling of key researchers: • Thomas, Paulin, Gajski, Wakabayashi, DeMann – Academic implementations • 1979 CMU - CMU-DA • 1988 Stanford Hercules – Most research focused on scheduling and allocation for datapath-dominated designs © 2013 Forte Design Systems 5 Generation 1 - 1990’s Generation 0 Generation -
28Th IEEE VLSI Test Symposium (VTS 2010) Santa Cruz, CA, April 19-21, 2010
28th IEEE VLSI Test Symposium (VTS 2010) Santa Cruz, CA, April 19-21, 2010 Preliminary Program (as of 3/25/10) Monday, 4/19/10 Plenary Session (9:00 – 11:00) Break (11:00 – 11:15) Sessions 1 (11:15 – 12:15) Session 1A: Delay & Performance Test 1 Moderator: M. Batek - Broadcom Fast Path Selection for Testing of Small Delay Defects Considering Path Correlations Z. He, T. Lv - Institute of Computing Technology, H. Li, X. Li - Chinese Academy of Sciences Identification of Critical Primitive Path Delay Faults without any Path Enumeration K. Christou, M. Michael, S. Neophytou - University of Cyprus Path Clustering for Adaptive Test T. Uezono, T. Takahashi - Tokyo Institute of Technology, M. Shintani , K. Hatayama - Semiconductor Technology Academic Research Center, K. Masu - Tokyo Institute of Technology, H. Ochi, T. Sato - Kyoto University Session 1B: Memory Test & Repair Moderator: P. Prinetto - Politecnico di Torino Automatic Generation of Memory Built-In Self-Repair Circuits in SOCs for Minimizing Test Time and Area Cost T. Tseng, C. Hou, J. Li - National Central University Bit Line Coupling Memory Tests for Single Cell Fails in SRAMs S. Irobi, Z. Al-ars, S. Hamdioui - Delft University of Technology Reducing Test Time and Area Overhead of an Embedded Memory Array Built-In Repair Analyzer with Optimal Repair Rate J. Chung, J. Park - The University of Texas at Austin, E. Byun, C. Woo - Samsung Electronics, J. Abraham - The University of Texas at Austin IP Session 1C: Innovative Practices in RF Test Organizer: R. Parekhji - Texas Instruments Moderator: TBA Test Time Reduction Using Parallel RF Test Techniques R. -
PLM Industry Summary Editor: Christine Bennett Vol
PLM Industry Summary Editor: Christine Bennett Vol. 11 No. 4 Friday 23 January 2009 Contents Acquisitions _______________________________________________________________________ 2 Autodesk Completes Acquisition of ALGOR, Inc. _____________________________________________2 Mentor Graphics Extends High Level Synthesis Leadership with Acquisition of Agility Design Solutions Inc. C Synthesis Suite ____________________________________________________________________3 Company News _____________________________________________________________________ 3 Anark Names Chris Garcia Senior Vice President, Business Development ___________________________3 Autodesk Manufacturing Community to Select 2008 Inventor of the Year Award Winner ______________4 Delcam Offers Free ArtCAM Demo Software for Artistic Users __________________________________5 DP signs Agreement with Italian Lathe Manufacturer GRAZIANO Tortona S.r.l. _____________________6 DP Technology Moves its Midwest Team to a Larger, New and Improved Site _______________________6 DP Technology Signs Agreement with Italian Machine-Tool Builder Salvadeo S.r.l. __________________7 Kalypso and Endeca Announce Partnership in Support of Engineering and PLM-Related Information Visibility Solutions ______________________________________________________________________7 New WorkXPlore 3D Website Allows Engineers to Download High Speed Collaborative CAD Viewer Free _____________________________________________________________________________________8 Si2’s Open Modeling Coalition Releases Document on Statistical -
When Innovation Is Hard
WhenWhen InnovationInnovation isis HardHard Does the Open Source Development Model Work in Hardware? ilkka.tuomi meaningprocessing.com © I. Tuomi 2 Oct. 2008 page: 1 ThesesTheses • 1. Software and hardware are epistemologically different artifacts • This leads to different innovation and conflict models in software and hardware projects • The success of the open distributed approach in ”close-to-hardware” software development (e.g. Linux kernel) is partly explained by this epistemological difference • 2. Close-to-hardware software, social software, and hardware are different • Close-to-hardware software development is easy to distribute because the developer community consists of a homogenous network of people and tools • There exists a ”phenomenological bottleneck:” Real hardware can only be approximated using digital representations; distributed hardware projects can therefore be really hard • There also exists a ”political bottleneck:” Social software can be hard as there are multiple interpretations and systems of meaning © I. Tuomi 2 Oct. 2008 page: 2 DifferentDifferent TypesTypes ofof AnimalsAnimals RequireRequire DifferentDifferent StylesStyles ofof BreedingBreeding • Close-to-hardware SW • HW • In a given HW environment: • The context is the open world: SW is both the description and the Unmodeled features matter implementation Systems wear, tear and break down Mapping between software and the Although dominant voices are loudest, functionality of the system is one-to-one evaluation criteria have to be negotiated Technical functionality can be empirically from multiple perspectives tested • A homogenous developer community, • A homogenous developer community, rooted in its own ”objective reality.” rooted in its own ”professional reality.” or: • A network of interacting communities, each with their own stocks of knowledge.