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Inside Chips InsideChips.VenturesTM Tracking Fabless, IP & Design-House Startups Volume 6, Number 7 July 2005 Business Microscope 3-D Chip Trends … For more than 30 years, the yearly conference explores market and technology chipmakers have been riding the Moore’s Law speed opportunities in the 3-D space. and performance wave. Without fail, they have been Universities, institutes/consortia, IDMs and a able to rely on reductions in transistor size used in ICs handful of startups are conducting 3-D research to achieve predicted increases in speed and around the world. Table 1 (page 2) highlights the performance. Moore’s Law, which states that chip notable players. DARPA funds most of the university performance doubles approximately every two years, programs in the U.S. held true because the RC delay has been negligible in comparison with signal propagation delay. For Initial 3-D efforts involved package stacking or submicron technology, however, RC delay becomes chip stacking in a single package with wire bond a dominant factor. As the industry moves to submicron feature interconnects. Amkor is a good illustration of this approach. sizes, shrinking two-dimensional chips will become problematic. Begun in 1998, the technology was primarily used for memory stacks. One emerging solution is 3-D integration. The technology is not new but it is becoming increasingly important as researchers One of the early pioneers of 3-D, Irvine Sensors, developed look for solutions beyond the perceived limits of today’s two- stacked chips in which the connections are made over the edge of dimensional devices. the die. One limitation, however, is that all die must be the same size. If a die shrink is implemented, the process requires InsideChips’ Steve Szirom co-chaired the 3-D Architectures considerable retooling. for Semiconductor Integration and Packaging Conference in Tempe, Ariz., held June 13-15. Organized by RTI International, Ziptronix uses a patented ZiROC and ZiCON bonding process : Business Microscope ..................................................................................... 1 e Bits and Bytes ............................................................................................... 3 u Semiconductor Stock Index ............................................................................ 3 s Stock Market Scan......................................................................................... 4 s Finance: News, Funding and Acquisitions ........................................................ 5 i Analyzing the Analysts .................................................................................. 10 s Emerging Ventures ....................................................................................... 11 i Agreements and Marketing Alliances ............................................................. 19 h t ASICs, IP and Design Services ...................................................................... 21 The Fast Track ... People & Organizations ..................................................... 22 n Companies Mentioned in This Issue ............................................................... 24 i COPYRIGHT 2005 by HTE Research, Inc. All rights reserved. Photocopying is a federal offense. No part of this report may be reproduced or distributed, in any form or by any means electronic or mechanical, without written permission from HTE Research, Inc. InsideChips.Ventures is published 12 times a year by HTE Research, Inc., PO Box 32237, Bellingham, WA 98228-4237. Telephone 360 676-2260. Web: www.insidechips.com, E-mail: [email protected]. Executive Editor: Steve Szirom; Associate Editor: Greg Friedman. Subscription rates and a sample issue are available upon request. A sample issue and brochure IC may also be downloaded from InsideChips.com's website. InsideChips.Ventures that enables analog, memory and logic die —designed Worldwide High-Density NOR Flash Memory and produced in their optimum technologies — to be Revenue ($ Billions) integrated as true chip-scale SOCs. This approach eliminates future scaling issues, and designers no longer 10 need to compromise embedded memory or analog circuit 9 functions. 8 (See our profile of Ziptronix in the Aug. 2003 issue of 7 InsideChips.Ventures.) 6 Tezzaron Semiconductor (formerly Tachyon 5 Semiconductor), which started out as design house, has 4 moved into the 3-D arena and is developing its FaStack 3 wafer-stacking technology. We believe the firm uses its 2 own proprietary IP, licensed stacking technology and 1 wafer-bonding technology co-developed with IME. 0 Tezzaron’s 3-D wafer-stacking technique is best suited 2005 2006 2007 2008 2009 for memory (DRAM, PCRAM, FeRAM, and MRAM) Source: iSuppli and FPGAs. Figure 1 Continued on page 20 Worldwide Digital Audio Chip Sales ($ Millions) Table 1 -- Companies and organizations in the 3-D semiconductor space 350 Institutes/Consortia 300 ASET (1999-2001) Japan Fraunhofer Germany 250 IMEC Belgium 200 RTI U.S. 150 Universities Albany Nanocenter U.S. 100 Arkansas U.S. 50 Delft Netherlands Lincoln Labs U.S. 0 MIT U.S. 2005 2006 2007 2008 2009 2010 RPI U.S. Source: In-Stat Tohoku Univ. Japan Figure 2 IDMs IBM U.S. 2004 Automotive Semiconductor Vendor Market Shares Amkor U.S. Fujitsu Japan Freescale Infineon Germany 12% Infineon Intel U.S. 9% Micron U.S. Toshiba Japan STM 8% Startups Contour Semiconductor U.S. Others Renesas Matrix Semiconductor U.S. 58% 7% Irvine Sensors U.S. NEC Tezzaron Semiconductor U.S. 6% Vertical Circuits U.S. Ziptronix U.S. Source: Strategy Analytics ZyCube Japan Figure 3 July 2005 Page 2 InsideChips.Ventures Bits and Bytes Cree to Close Silicon the company’s Cree Microwave segment • Disengage from certain activities. for financial reporting purposes. Although Microwave Business STMicroelectronics said it will attempt this segment will no longer be used for to minimize the social impact of this Cree has revealed plans to close the financial reporting purposes, Cree’s wide- reorganization by putting in place, whenever silicon RF and microwave semiconductor bandgap RF and microwave products based possible, measures that favor voluntary business of its wholly owned subsidiary, on SiC and GaN technology will continue to redundancy (early retirement measures, job Cree Microwave, located in Sunnyvale, be marketed under the Cree Microwave creation schemes, individual projects, Calif. This business manufactures silicon- brand. based laterally diffused metal oxide transition to part-time work). semiconductor (LDMOS) and bipolar STMicroelectronics Sheds More Lattice Places Two products. Light on European Restructuring Top Execs on Leave Cree said it closed the business to focus STMicroelectronics has specified the on wide-bandgap RF and microwave Lattice Semiconductor has placed CEO restructuring efforts the company announced products based on its silicon carbide (SiC) Cyrus Tsui and Rodney Sloss, VP of finance, on May 16. The company presented and gallium nitride (GaN) technology. The on paid leave of absence pending completion principles of the initiatives, which will bring company also considered the financial of an independent examination being the cumulative reduction of its workforce in outlook for the silicon RF and microwave undertaken by the company’s audit Europe — out of a total of 3,000 outside semiconductor operations. For the nine committee. Lattice named Stephen Skaggs Asia — to 2,300 jobs by mid-2006, including months ended March 27, 2005, Cree acting CEO and Patrick Jones acting the non-renewal of some temporary incurred net operating pre-tax losses of chairman of the board. positions. $9.2 million related to this segment of its The audit committee is examining issues business. The following are some of the company primarily associated with executive plans to reorganize its European activities: Cree Microwave will accept last time compensation and several related items buy orders for its silicon LDMOS products • Convert 6-inch production tools pertaining to the company’s internal through June 2005, and plans to wind down to 8 inches, in pursuit of the program already controls. Lattice said it is not aware of any the operations of this business by December undertaken; required adjustments to its historical 2005. The company estimates that it will financial results in connection with these incur a total of approximately $13 million • Optimize its EWS activities (wafer matters. The company has furnished to $15 million in pre-tax expenses to close test) on a global scale; information regarding the matters under the Sunnyvale facility. • Harmonize its support functions, examination to the Securities and Exchange The silicon RF business operated at the reduce its costs and rationalize its activities Commission, which is conducting an Sunnyvale facility has been referred to as (outside of manufacturing); and Continued on page 21 Semiconductor Stock Index Short Term Long Term InsideChips.Ventures reports on and analyzes the semiconductor industry based on information obtained from sources generally available to the public, and from industry contacts. Although these sources are considered reliable, we cannot guarantee their accuracy. The opinions and views expressed herein reflect the judgment of HTE Research, Inc., and are subject to change. We welcome the views of subscribers on the content and analyses found in this report. HTE Research, Inc., and its editor(s) do not have any equity positions in the companies profiled in InsideChips.Ventures unless specially noted at the end of the profile. July 2005
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