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The COMPLEX Reference Framework for HW/SW Co-Design and Power Man‐ Agement Supporting Platform-Based Design-Space Exploration

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The COMPLEX Reference Framework for HW/SW Co-Design and Power Man‐ Agement Supporting Platform-Based Design-Space Exploration Accepted Manuscript The COMPLEX reference framework for HW/SW Co-Design and Power Man‐ agement Supporting Platform-Based Design-Space Exploration Kim Grüttner, Philipp A. Hartmann, Kai Hylla, Sven Rosinger, Wolfgang Nebel, Fernando Herrera, Eugenio Villar, Carlo Brandolese, William Fornaciari, Gianluca Palermo, Chantal Ykman-Couvreur, Davide Quaglia, Francisco Ferrero, Raúl Valencia PII: S0141-9331(13)00122-1 DOI: http://dx.doi.org/10.1016/j.micpro.2013.09.001 Reference: MICPRO 2072 To appear in: Microprocessors and Microsystems Please cite this article as: K. Grüttner, P.A. Hartmann, K. Hylla, S. Rosinger, W. Nebel, F. Herrera, E. Villar, C. Brandolese, W. Fornaciari, G. Palermo, C. Ykman-Couvreur, D. Quaglia, F. Ferrero, R. Valencia, The COMPLEX reference framework for HW/SW Co-Design and Power Management Supporting Platform-Based Design-Space Exploration, Microprocessors and Microsystems (2013), doi: http://dx.doi.org/10.1016/j.micpro.2013.09.001 This is a PDF file of an unedited manuscript that has been accepted for publication. As a service to our customers we are providing this early version of the manuscript. The manuscript will undergo copyediting, typesetting, and review of the resulting proof before it is published in its final form. Please note that during the production process errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal pertain. The COMPLEX reference framework for HW/SW Co-Design and Power Management Supporting Platform-Based Design-Space Exploration Kim Gruttner¨ a, Philipp A. Hartmanna, Kai Hyllaa, Sven Rosingera, Wolfgang Nebelb, Fernando Herrerac, Eugenio Villarc, Carlo Brandolesed, William Fornaciarid, Gianluca Palermod, Chantal Ykman-Couvreure, Davide Quagliaf, Francisco Ferrerog, Raul´ Valenciag aOFFIS – Institute for Information Technology, Oldenburg, Germany bCarl von Ossietzky University Oldenburg, Germany cUniversidad de Cantabria, Santander, Cantabria, Spain dPolitecnico di Milano, Italy eIMEC, Belgium fEDALab s.r.l. - Networked Embedded Systems, Verona, Italy gGMV Aerospace and Defence S.A.U - Madrid, Spain Abstract The consideration of an embedded device’s power consumption and its management is increasingly important nowa- days. Currently, it is not easily possible to integrate power information already during the platform exploration phase. In this paper, we discuss the design challenges of today’s heterogeneous HW/SW systems regarding power and com- plexity, both for platform vendors as well as system integrators. As a result, we propose a reference framework and design flow concept that combines system-level power op- timization techniques with platform-based rapid prototyping. Virtual executable prototypes are generated from MARTE/UML and functional C/C++ descriptions, which then allows to study different platforms, mapping alter- natives, and power management strategies. Our proposed flow combines system-level timing and power estimation techniques available in commercial tools with platform-based rapid prototyping. We propose an efficient code annotation technique for timing and power properties enabling fast host execution as well as adaptive collection of power traces. Combined with a flexible design-space exploration (DSE) approach our flow allows a trade-off analysis between different platforms, mapping alternatives, and optimization techniques, based on domain-specific workload scenarios. The proposed framework and design flow has been implemented in the COMPLEX FP7 European integrated project. Keywords: HW/SW Timing and Power Estimation, Virtual Prototyping, Design-Space Exploration, Power Management 1. Introduction as System-on-a-Chip (SoC), can be implemented on a single chip. In the past a lot of effort has been spent Increasing computing power and shrinking sizes of on characterizing and estimating hard- as well as soft- processing elements allow more and more functional- ware parts of the SoC [1, 2]. For both of them relatively ity to be realized within embedded systems. In earlier good techniques and tools exist, hence their properties times embedded systems have only implemented sim- and characteristics are well known and well understood. ple functions, but today complete systems, also known In large and complex SoCs, components of the sys- tem, such as hardware, software, memory, and inter- Email addresses: [email protected] (Kim Gruttner),¨ connect, cannot be considered separately. They must [email protected] (Wolfgang Nebel), be considered together while interacting to capture the [email protected] (Eugenio Villar), entire system behavior [3, 4, 5]. For analysis of the dy- [email protected] (William Fornaciari), namic behavior this implies a behavioral simulation of [email protected] (Chantal Ykman-Couvreur), [email protected] (Davide Quaglia), all system components and their interaction, also with [email protected] (Francisco Ferrero) their environment. This is essential for power and tim- Preprint submitted to Microprocessors and Microsystems August 27, 2013 ing estimations. For specific platforms, proprietary sim- and accurate model of the future system and workload ulation environments are available for both timing and scenario, prior to heavy investments in HW and SW power models (see Section 2). But a common and open development is necessary. In our approach we focus framework, suitable for a large range of platforms and on the enrichment of virtual execution platforms with designs is still missing. Such a framework would allow extra-functional properties. In the proposed approach, comparing different platform characteristics and thus we do not address an automated path to implementation rapid prototyping and design space exploration. Per- or automatic synthesis of physical platforms, yet. formance bottlenecks and power peaks within the entire Today’s virtual prototyping platforms are provided system could be identified in early design phases, where for early software development and functional test- modifications of the system are easier and more afford- ing. These platforms are often built using SystemC able than in later phases. TLM-2.0 interfaces at AT (Approximately Timed) or LT In this paper we present a new design flow con- (Loosely Timed) abstraction. Today these platforms are cept and propose a framework that combines system- used for functional software development and software level power optimization techniques with platform- stack configuration. Most virtual platforms are target- based rapid prototyping. For the proposed approach we ing mainly functional and loose timing aspects in early focus on the derivation of an executable virtual proto- software development. Power dissipation or the func- type of an embedded HW/SW systems right after func- tional effects of dynamic power management strategies tional specification, partitioning, and mapping to an im- cannot be taken into consideration, and thus cannot be plementation platform. Execution or simulations of this explored at early design stages. prototype allow decisions concerning architecture, per- Code generation in Model-Driven Engineering formance, power, and price, early in the development (MDE), high-level synthesis techniques for custom HW, process. The challenges we need to face in today’s Elec- and abstraction of existing components to system-level tronic System Level (ESL) design-flow, including ex- descriptions are key enablers for unified system-level isting point tools that are able to address single design simulation approaches [7] and need to be urgently com- issues, are presented in Section 2. The proposed frame- bined with the virtual prototyping platform approach work, that is the result of the COMPLEX European as mentioned above. We want to consider functional, project [6], follows a unified system-level specification power and timing behavior on system-level under ex- for HW and SW, but utilizes different estimation tech- plicit partitioning and mapping to a specific implemen- niques for custom HW and SW, as well as pre-defined tation platform (R1). This requires: IP components. Since good stand-alone solutions for each of these parts exist, Section 3 presents our con- 1. a formal system-level specification to be linked cept that unifies state-of-the-art tools and techniques in with functional and extra-functional requirements a common design-flow. Section 4 presents different in- to be checked during the entire design process, dustrial use-case aware customizations of the proposed 2. an executable model that can be derived automat- design-flow. Conclusions are drawn in Section 5, which ically from the formal specification model, which sums up our concept and points out following work. is capable to simulate large sequences of domain- specific workloads in an acceptable time, 2. Requirements, existing tools & related work 3. the representation and annotation of extra- This section aims at defining requirements (high- functional information (timing and power) in the lighted as R1-8) for early system specification, model- executable specification. ing, and simulation at ESL. In this sense, we are giving a brief overview of commercial tools and related work. For today’s embedded HW/SW systems this cannot Generally, embedded system design is a sequence of be done on RT-level anymore, due to high simulation design decisions that finally leads to an implementation. complexity. The requirements of the proposed frame- These decisions are made with regard to the functional work [8], along with point-tools (as described in [9]) and
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