48Th DAC Final Program
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EP Activity Report 2014
EUROPRACTICE IC SERVICE THE RIGHT COCKTAIL OF ASIC SERVICES EUROPRACTICE IC SERVICE OFFERS YOU A PROVEN ROUTE TO ASICS THAT FEATURES: • Low-cost ASIC prototyping • Flexible access to silicon capacity for small and medium volume production quantities • Partnerships with leading world-class foundries, assembly and testhouses • Wide choice of IC technologies • Distribution and full support of high-quality cell libraries and design kits for the most popular CAD tools • RTL-to-Layout service for deep-submicron technologies • Front-end ASIC design through Alliance Partners Industry is rapidly discovering the benefits of using the EUROPRACTICE IC service to help bring new product designs to market quickly and cost-effectively. The EUROPRACTICE ASIC route supports especially those companies who don’t need always the full range of services or high production volumes. Those companies will gain from the flexible access to silicon prototype and production capacity at leading foundries, design services, high quality support and manufacturing expertise that includes IC manufacturing, packaging and test. This you can get all from EUROPRACTICE IC service, a service that is already established for 20 years in the market. THE EUROPRACTICE IC SERVICES ARE OFFERED BY THE FOLLOWING CENTERS: • imec, Leuven (Belgium) • Fraunhofer-Institut fuer Integrierte Schaltungen (Fraunhofer IIS), Erlangen (Germany) This project has received funding from the European Union’s Seventh Programme for research, technological development and demonstration under grant agreement N° 610018. This funding is exclusively used to support European universities and research laboratories. By courtesy of imec FOREWORD Dear EUROPRACTICE customers, Time goes on. A year passes very quickly and when we look around us we see a tremendous rapidly changing world. -
Die Virtuelle Plattform: Der Einsatz Von Zynq Fuer Die Verifikation Und Das Debugging Von Konfigurierbaren Systemen
Die virtuelle Plattform: Der Einsatz von Zynq fuer die Verifikation und das Debugging von konfigurierbaren Systemen Dr. Endric Schubert Missing Link Electronics Marlene-Dietrich-Straße 5 89231 Neu-Ulm www.missinglinkelectronics.com Tel: +49 (731) 141-149-0 Courtesy Xilinx 1 Challenges of Debugging Your Own ASSP © Missing Link Electronics 12. Juli 2012 2 Another Challenge When Building Your Own ASSP: Making Hardware and Software Work Together. © Missing Link Electronics 12. Juli 2012 3 ASSP System-on-Chip Design – An Embedded Designers Life © Missing Link Electronics 12. Juli 2012 4 What is a Virtual Platform? © Missing Link Electronics 12. Juli 2012 5 Virtual Platform Methodology © Missing Link Electronics 12. Juli 2012 6 Virtual Platforms Can Run Software Fast (Sometimes Faster Than Real) © Missing Link Electronics 12. Juli 2012 7 What is SystemC? Open Source Library managed by Open SystemC Initiative (OSCI) Extension to ISO C++ www.systemc.org Means to express concurrency Communication mechanisms Reactivity Concept of Time Current members: ARM Ltd. Cadence Design Systems, Inc. CoWare, Inc. Forte Design Systems Intel Event driven simulation kernel Corporation Mentor Graphics Corporation NXP Semiconductors STMicroelectronics Synopsys, Inc. Actis Design, LLC Atrenta, Inc. Bluespec, Inc. Broadcom - A modeling methodology Corporation Calypto Design Systems, Inc. Canon Inc. Carbon Design Systems Celoxica Ltd. ChipVision Design Systems AG Denali Software Inc. Doulos Ltd. ESLX, Inc. Fraunhofer Institute for Integrated Circuits Freescale Semiconductor Inc. GreenSocs Ltd. Industrial Technology Research Institute (ITRI) JEDA Technologies Inc. Infineon Technologies AG NEC Corporation Semiconductor Technology Academic Research Center (STARC) SpringSoft, Inc. Synfora Inc. Tenison EDA VaST Systems Technology Corporation © Missing Link Electronics 12. -
Co-Emulation of Scan-Chain Based Designs Utilizing SCE-MI Infrastructure
UNLV Theses, Dissertations, Professional Papers, and Capstones 5-1-2014 Co-Emulation of Scan-Chain Based Designs Utilizing SCE-MI Infrastructure Bill Jason Pidlaoan Tomas University of Nevada, Las Vegas Follow this and additional works at: https://digitalscholarship.unlv.edu/thesesdissertations Part of the Computer Engineering Commons, Computer Sciences Commons, and the Electrical and Computer Engineering Commons Repository Citation Tomas, Bill Jason Pidlaoan, "Co-Emulation of Scan-Chain Based Designs Utilizing SCE-MI Infrastructure" (2014). UNLV Theses, Dissertations, Professional Papers, and Capstones. 2152. http://dx.doi.org/10.34917/5836171 This Thesis is protected by copyright and/or related rights. It has been brought to you by Digital Scholarship@UNLV with permission from the rights-holder(s). You are free to use this Thesis in any way that is permitted by the copyright and related rights legislation that applies to your use. For other uses you need to obtain permission from the rights-holder(s) directly, unless additional rights are indicated by a Creative Commons license in the record and/ or on the work itself. This Thesis has been accepted for inclusion in UNLV Theses, Dissertations, Professional Papers, and Capstones by an authorized administrator of Digital Scholarship@UNLV. For more information, please contact [email protected]. CO-EMULATION OF SCAN-CHAIN BASED DESIGNS UTILIZING SCE-MI INFRASTRUCTURE By: Bill Jason Pidlaoan Tomas Bachelor‟s Degree of Electrical Engineering Auburn University 2011 A thesis submitted -
Download the Compiled Program File Onto the Chip
International Journal of Computer Science & Information Technology (IJCSIT) Vol 4, No 2, April 2012 MPP SOCGEN: A FRAMEWORK FOR AUTOMATIC GENERATION OF MPP SOC ARCHITECTURE Emna Kallel, Yassine Aoudni, Mouna Baklouti and Mohamed Abid Electrical department, Computer Embedded System Laboratory, ENIS School, Sfax, Tunisia ABSTRACT Automatic code generation is a standard method in software engineering since it improves the code consistency and reduces the overall development time. In this context, this paper presents a design flow for automatic VHDL code generation of mppSoC (massively parallel processing System-on-Chip) configuration. Indeed, depending on the application requirements, a framework of Netbeans Platform Software Tool named MppSoCGEN was developed in order to accelerate the design process of complex mppSoC. Starting from an architecture parameters design, VHDL code will be automatically generated using parsing method. Configuration rules are proposed to have a correct and valid VHDL syntax configuration. Finally, an automatic generation of Processor Elements and network topologies models of mppSoC architecture will be done for Stratix II device family. Our framework improves its flexibility on Netbeans 5.5 version and centrino duo Core 2GHz with 22 Kbytes and 3 seconds average runtime. Experimental results for reduction algorithm validate our MppSoCGEN design flow and demonstrate the efficiency of generated architectures. KEYWORD MppSoC, Automatic code generation; mppSoC configuration;parsing ; MppSoCGEN; 1. INTRODUCTION Parallel machines are most often used in many modern applications that need regular parallel algorithms and high computing resources, such as image processing and signal processing. Massively parallel architectures, in particular Single Instruction Multiple Data (SIMD) systems, have shown to be powerful executers for data-intensive applications [1]. -
ECD.June.2013.Pdf
-community Post Joining the embedded conversation -community Post Joining the embedded conversation ON THE COVER Embedded Computing Design editors have been on the lookout for this year’s Top Embedded Innovators, and – for the first time this year -– thecommunity Most Influential Women in Post Embedded. Our two contests pulled in many inspirational, www.embedded-computing.com highly qualified candidatesJoining who are theforging embedded new ideas conversation and making a difference in the embedded industry. Read June 2013 | Volume 11 • Number 4 about the winners in this edition’s exclusive Q&As, and check out the nominees for Most Innovative Product, winners to be announced in our August edition. 7 Tracking Trends in Embedded Technology 54 -community Post Top Innovators streamline embedded technology Joining the embedded conversation By Warren Webb By Sharon Hess Silicon Software Strategies Multicore processors Finding an operating system Small form factors 8 24 31 Moving target: EEMBC evolves ▲ Choose the right ▲ VPX helps programmable 28 its benchmark suites to keep pace embedded operating system field of dreams become reality with the multicore revolution By Warren Webb By Kevin Roth, Alpha Data Q&A with Markus Levy, Founder and President of EEMBC Case study: 31 Challenges in incarnating a ARM’s big.LITTLE 11 EXPERT PANEL: 14 credit card sized SBC architecture aims to satisfy the Is EDA as easy as By Pete Lomas, Raspberry Pi hunger for power 1, 2, 3 these days? Q&A with John Goodacre, Director, Roundtable discussion with Wally Rhines, Chairman Technology and Systems, ARM Processor Division and CEO, Mentor Graphics; Brett Cline, Vice President, Forte Design Systems; Marc Serughetti, Business Development Director, Synopsys; Michał Siwinski,´ Director of Product Marketing at Cadence; Bill Neifert, 52 Cofounder and CTO, Carbon Design Systems Editor’s Choice By Sharon Hess Top Embedded Innovators Josh Lee, Cofounder, President, and CEO at Uniquify 34 Darren Humphrey, Sr. -
I/O Design and Core Power Management Issues in Heterogeneous Multi/Many-Core System-On-Chip
UNIVERSITY OF CALIFORNIA, IRVINE I/O Design and Core Power Management Issues in Heterogeneous Multi/Many-Core System-on-Chip DISSERTATION submitted in partial satisfaction of the requirements for the degree of DOCTOR OF PHILOSOPHY in Computer Science by Myoung-Seo Kim Dissertation Committee: Professor Jean-Luc Gaudiot, Chair Professor Alexandru Nicolau, Co-Chair Professor Alexander Veidenbaum 2016 c 2016 Myoung-Seo Kim DEDICATION To my father and mother, Youngkyu Kim and Heesook Park ii TABLE OF CONTENTS Page LIST OF FIGURES vi LIST OF TABLES viii ACKNOWLEDGMENTS ix CURRICULUM VITAE x ABSTRACT OF THE DISSERTATION xv I DESIGN AUTOMATION FOR CONFIGURABLE I/O INTERFACE CONTROL BLOCK 1 1 Introduction 2 2 Related Work 4 3 Structure of Generic Pin Control Block 6 4 Specification with Formalized Text 9 4.1 Formalized Text . 9 4.2 Specific Functional Requirement . 11 4.3 Composition of Registers . 11 5 Experiment Results 18 6 Conclusions 24 II SPEED UP MODEL BY OVERHEAD OF DATA PREPARATION 26 7 Introduction 27 8 Reconsidering Speedup Model by Overhead of Data Preparation (ODP) 29 iii 9 Case Studies of Our Enhanced Amdahl's Law Speedup Model 33 9.1 Homogeneous Symmetric Multicore . 33 9.2 Homogeneous Asymmetric Multicore . 35 9.3 Homogeneous Dynamic Multicore . 36 9.4 Heterogeneous CPU-GPU Multicore . 39 9.5 Heterogeneous Dynamic CPU-GPU Multicore . 41 10 Conclusions 43 III EFFICIENT CORE POWER CONTROL SCHEME 44 11 Introduction 45 12 Related Work 47 13 Architecture 51 13.1 Heterogeneous Many-Core System . 51 13.2 Discrete L2 Cache Memory Model . 52 14 3-Bit Power Control Scheme 55 14.1 Active Status . -
Final Program November 7 - 10, 2011 San Jose, Ca
2011 FINAL PROGRAM NOVEMBER 7 - DESIGN10, TOOLS ASIC 2011 ENGINEERING VERIFICATION STRUCTURE ESDA SAN JOSE,PLANS CA CHIP EFFICIENCY INNOVATION DESIGN SIGNAL MIXED MIXED OPPORTUNITY CAD LOGIC SYNTHESIS COMPLEXITY MANUFACTURING IEEE/ACM TEMPLATES APPLIED SCIENCE PATTERN FPGA EDA AUTOMATION INTERNATIONAL METHODOLOGIES TECHNOLOGY EXHIBITCONFERENCE ON ADVANCEMENT STANDARDS CONCEPTION COMPLIANCE PIONEERING MECHANICS COMPUTER-AIDED CIRCUITS NETWORKING WORKFLOWDESIGN ELECTRONIC DESIGN2011 www.ICCAD.com www.iccad.com 2011 ICCAD continues to be the premier conference devoted to technical innovations in design automation. ICCAD’s program of technical papers, tutorials, panels, and keynote highlight ICCAD continues to host one‑day topical workshops providing focused the most important current and future research challenges. A day of coverage of topics of emerging and current interest. This year, four workshops, workshops on hot topics caps a week of non‑stop technical excitement. And on lithography, variability modeling/characterization, constraints in formal as always, a large number of side meetings and social events provide plenty of verification and adaptive power management will take place on Thursday, opportunities for networking and meeting colleagues and friends. November 10. This year’s CANDE workshop will also be co‑located with ICCAD in San Jose, and held in parallel with ICCAD workshops on Thursday, November 10. This year’s ICCAD starts on Monday, November 7 and continues through Wednesday, November 9. You will find up‑to‑date details on the conference website, http://www.iccad.com. Finally, ICCAD 2011 is privileged to have a keynote address from Dr. Georg Sigl of Technische Univ. München. Prof. Sigl will provide unique insights into the design of secure hardware systems, and asks what role EDA will play in the The core of ICCAD has always been the contributed research paper program. -
CHAPTER 3: Combinational Logic Design with Plds
CHAPTER 3: Combinational Logic Design with PLDs LSI chips that can be programmed to perform a specific function have largely supplanted discrete SSI and MSI chips in board-level designs. A programmable logic device (PLD), is an LSI chip that contains a “regular” circuit structure, but that allows the designer to customize it for a specific application. PLDs sold in the market is not customized with specific functions. Instead, it is programmed by the purchaser to perform a function required by a particular application. PLD-based board-level designs often cost less than SSI/MSI designs for a number of reasons. Since PLDs provide more functionality per chip, the total chip and printed- circuit-board (PCB) area are less. Manufacturing costs are reduced in other ways too. A PLD-based board manufacturer needs to keep samples of few, “generic” PLD types, instead of many different MSI part types. This reduces overall inventory requirements and simplifies handling. PLD-type structures also appear as logic elements embedded in LSI chips, where chip count and board areas are not an issue. Despite the fact that a PLD may “waste” a certain number of gates, a PLD structure can actually reduce circuit cost because its “regular” physical structure may use less chip area than a “random logic” circuit. More importantly, the logic function performed by the PLD structure can often be “tweaked” in successive chip revisions by changing just one or a few metal mask layers that define signal connections in the array, instead of requiring a wholesale addition of gates and gate inputs and subsequent re-layout of a “random logic” design. -
Formal Hardware Specification Languages for Protocol Compliance Verification
Formal Hardware Specification Languages for Protocol Compliance Verification ANNETTE BUNKER and GANESH GOPALAKRISHNAN University of Utah and SALLY A. MCKEE Cornell University The advent of the system-on-chip and intellectual property hardware design paradigms makes pro- tocol compliance verification increasingly important to the success of a project. One of the central tools in any verification project is the modeling language, and we survey the field of candidate languages for protocol compliance verification, limiting our discussion to languages originally in- tended for hardware and software design and verification activities. We frame our comparison by first constructing a taxonomy of these languages, and then by discussing the applicability of each approach to the compliance verification problem. Each discussion includes a summary of the devel- opment of the language, an evaluation of the language’s utility for our problem domain, and, where feasible, an example of how the language might be used to specify hardware protocols. Finally, we make some general observations regarding the languages considered. Categories and Subject Descriptors: B.4.3 [Input/Output and Data Communications]: Inter- connections (Subsystems)—Interfaces; B.4.5 [Input/Output and Data Communications]: Reli- ability, Testing, and Fault-Tolerance—Hardware reliability; B.7.2 [Integrated Circuits]: Design aids—Verification; C.2.2 [Computer-Communication Networks]: Network Protocols—Protocol verification; D.3.3 [Programming Languages]: Language Constructs and Features—Data types -
Technical Portion
50 50 YEARS OF INNOVATION DESIGN AUTOMATION CONFERENCE Celebrating 50 Years of Innovation! www.DAC.com JUNE 2-6, 2013 AUSTIN CONVENTION CENTER - AUSTIN, TX SPONSORED BY: IN TECHNICAL COOPERATION WITH: 1 2 TABLE OF CONTENTS General Chair’s Welcome ....................................................................................................................... 4 Sponsors ................................................................................................................................................. 5 Important Information ............................................................................................................................ 6 Networking Receptions .......................................................................................................................... 7 Keynotes ....................................................................................................................................8,9,13-15 Kickin’ it up in Austin Party .................................................................................................................. 10 Global Forum ........................................................................................................................................ 11 Awards .................................................................................................................................................. 12 Technical Sessions ..........................................................................................................................16-36 -
Simulating Altera Designs
1. Simulating Altera Designs May 2013 QII53025-13.0.0 QII53025-13.0.0 This document describes simulating designs that target Altera® devices. Simulation verifies design behavior before device programming. The Quartus® II software supports RTL and gate level design simulation in third-party EDA simulators. Altera Simulation Overview Simulation involves setting up your simulator working environment, compiling simulation model libraries, and running your simulation. Generate simulation files in an automated or custom flow. Refer to Figure 1–1 and Table 1–3. Figure 1–1. Simulation in Quartus II Design Flow Design Entry (HDL, Qsys, DSP Builder) Altera Simulation RTL Simulation Models Quartus II Design Flow Gate-Level Simulation Post-synthesis functional Post-synthesis Analysis & Synthesis simulation netlist functional simulation EDA Fitter Netlist Post-fit functional Post-fit functional (place-and-route) Writer simulation netlist simulation Post-fit timing TimeQuest Timing Analyzer (Optional)Post-fit timing Post-fit simulation netlist (1) timing simulation simulation (3) Device Programmer (1) Timing simulation is not supported for Arria® V, Cyclone® V, Stratix® V, and newer families. You can use the Quartus II NativeLink feature to automatically generate simulation files and scripts. NativeLink can launch your simulator a from within the Quartus II software. Use a custom flow for more control over all aspects of simulation file generation. © 2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. -
EP Activity Report 2015
EUROPRACTICE IC SERVICE THE RIGHT COCKTAIL OF ASIC SERVICES EUROPRACTICE IC SERVICE OFFERS YOU A PROVEN ROUTE TO ASICS THAT FEATURES: · .QYEQUV#5+%RTQVQV[RKPI · (NGZKDNGCEEGUUVQUKNKEQPECRCEKV[HQTUOCNNCPFOGFKWOXQNWOGRTQFWEVKQPSWCPVKVKGU · 2CTVPGTUJKRUYKVJNGCFKPIYQTNFENCUUHQWPFTKGUCUUGODN[CPFVGUVJQWUGU · 9KFGEJQKEGQH+%VGEJPQNQIKGU · &KUVTKDWVKQPCPFHWNNUWRRQTVQHJKIJSWCNKV[EGNNNKDTCTKGUCPFFGUKIPMKVUHQTVJGOQUVRQRWNCT%#&VQQNU · 46.VQ.C[QWVUGTXKEGHQTFGGRUWDOKETQPVGEJPQNQIKGU · (TQPVGPF#5+%FGUKIPVJTQWIJ#NNKCPEG2CTVPGTU +PFWUVT[KUTCRKFN[FKUEQXGTKPIVJGDGPG«VUQHWUKPIVJG'74124#%6+%'+%UGTXKEGVQJGNRDTKPIPGYRTQFWEVFGUKIPUVQOCTMGV SWKEMN[CPFEQUVGHHGEVKXGN[6JG'74124#%6+%'#5+%TQWVGUWRRQTVUGURGEKCNN[VJQUGEQORCPKGUYJQFQP°VPGGFCNYC[UVJG HWNNTCPIGQHUGTXKEGUQTJKIJRTQFWEVKQPXQNWOGU6JQUGEQORCPKGUYKNNICKPHTQOVJG¬GZKDNGCEEGUUVQUKNKEQPRTQVQV[RGCPF RTQFWEVKQPECRCEKV[CVNGCFKPIHQWPFTKGUFGUKIPUGTXKEGUJKIJSWCNKV[UWRRQTVCPFOCPWHCEVWTKPIGZRGTVKUGVJCVKPENWFGU+% OCPWHCEVWTKPIRCEMCIKPICPFVGUV6JKU[QWECPIGVCNNHTQO'74124#%6+%'+%UGTXKEGCUGTXKEGVJCVKUCNTGCF[GUVCDNKUJGF HQT[GCTUKPVJGOCTMGV THE EUROPRACTICE IC SERVICES ARE OFFERED BY THE FOLLOWING CENTERS: · KOGE.GWXGP $GNIKWO · (TCWPJQHGT+PUVKVWVHWGT+PVGITKGTVG5EJCNVWPIGP (TCWPJQHGT++5 'TNCPIGP )GTOCP[ This project has received funding from the European Union’s Seventh Programme for research, technological development and demonstration under grant agreement N° 610018. This funding is exclusively used to support European universities and research laboratories. © imec FOREWORD Dear EUROPRACTICE customers, We are at the start of the