Issue 25 Second Quarter 1997 THE QUARTERLYX JOURNALCELL FOR XILINX PROGRAMMABLE LOGIC USERS
R PRODUCT INFORMATION
The Programmable Xilinx Delivers Next Logic CompanySM Generation Platform Inside This Issue: The new XACTstep version M1 release enables GENERAL The Fawcett - FPGAs, Power users to increase design performance while & Packages ...... 2 leveraging high-level design methodologies ... Guest Editorial: See pages 12 & 19 HardWire and PCI LogiCOREs ...... 3 Customer Success Story ...... 5 WebLINX Enhancements ...... 6 XC4000 Series: The World’s “Power of Innovation” Seminars ...... 7 Technical Training Update ...... 7 Upcoming Events ...... 8 Largest and Fastest FPGAs New Product Literature ...... 8 The world’s highest-capacity FPGA, the XC4085XL, Financial Results ...... 8 begins sampling as the world’s highest-performance PRODUCTS FPGAs, the XC4000E-1 family, move into production ... XC4000E-1 Speed Grade ...... 9 See Pages 9 & 11 XC95288 CPLD in Production ...... 10 XC4085XL Now Largest FPGA ...... 11 New 64,000-Gate XC6264 ...... 11 DESIGN TIPS & HINTS DEVELOPMENT SYSTEMS XACTstep M1 Software Released .. 12 Xilinx Shipping Cadence Interface . 13 XC9500 CPLD CORE Generator for PCI ...... 14 DSP CORE Generator ...... 15 Programming HINTS & ISSUES Simple XC9500 CPLD Guidelines Programming Guidelines ...... 16 To reap the advantages of in- Technical Questions & Answers Viewlogic, Mentor Graphics ...... 18 system-programmable CPLDs, Technical Support Resources ...... 18 some simple guidelines must XACTstep M1 Design Portability .... 19 Programmable be followed ... Mixed Voltages and PLDs ...... 20 See Page 16 XC9500 ISP With GR228X ...... 22 Logic in Mixed Component Availability Chart ... 24-25 Programming Support Charts .... 26-27 Voltage Applications Alliance Program Charts ...... 28-30 Development Systems Chart ...... 31 A guide to using Xilinx devices in mixed Fax Back Form ...... 32 3.3 V/5 V systems ... See Page 20 ○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○ FROM THE FAWCETT FPGAs, Power and Packages By BRADLY FAWCETT ◆ Editor As programmable logic suppliers acceler- system performance (switching frequency), ate their use of advanced deep-submicron and device utilization (the number of intercon- process technologies, the performance and nects and logic elements used and the percent- 2 density capabilities of FPGAs continues to age of these that switch at a given time). increase dramatically. As with most CMOS devices, the operating System designers can now power consumption of an FPGA is almost take advantage of pro- exclusively dynamic, and varies with the grammable logic devices square of the supply voltage. Thus, using exceeding 100,000 logic FPGAs based on the 3.3V power standard, as gates and supporting sys- opposed to the 5V standard, greatly reduces tem clock rates approach- device power requirements. For a given circuit ing 100 MHz. and clock speed, just reducing the supply In general, the CMOS voltage from 5V to 3.3V decreases operating technology used to produce power consumption by 56%. (The move to FPGAs is a low-power lower supply voltages is largely driven by the technology. However, given fact that the ever-shrinking transistors within a the density and performance levels of leading- submicron device cannot withstand high volt- edge FPGA devices, power consumption issues ages; however, even if this was not the case, can no longer be ignored during high-density the industry would be driven to lower supply FPGA design. In the past, the availability of voltages due to device power dissipation is- architectural resources (such as logic blocks and sues alone.) interconnect routing) and the inherent delays of Low-Power Architectures the various logic elements and routing switches The architectures of Xilinx high-density were almost always the limiting factors in deter- XCell FPGAs — specifically the XC4000E, XC4000EX, mining device utilization levels and system Xilinx, Inc. and XC4000XL families — have been designed 2100 Logic Drive speed. Now, power consumption can be the to minimize power consumption. For example, San Jose, CA 95124 limiting factor. In other words, a designer might Phone: 408-559-7778 the patented segmented- not be able to use all the available logic blocks FAX: 408-879-4676 interconnect architecture and run the design as fast as possible without ©1997 Xilinx Inc. minimizes the lengths of risking reliability problems due to overheating All rights reserved. metal traces, thereby ❝... the devices. power XCell is published quarterly preventing unnecessary for customers of Xilinx, Inc. As well as affecting the maximum possible interconnect capacitance consumption issues Xilinx, the Xilinx logo, XACT, density and performance, the power character- FPGA Foundry, and NeoCAD from slowing device are registered trademarks; istics of FPGA devices directly affect packaging can no longer be operation and causing all XC-designated products, (and, therefore, component costs) and device HardWire, XACTstep, extra power dissipation. reliability. Junction temperatures within a ignored during high- LogiCORE, AllianceCORE, The extra buffering that CORE Generator, Foundation device are a function of power consumption Series, Alliance Series, was added to the long ❞ and the thermal resistance of the package density FPGA design. WebLINX, SmartSearch, lines and quad lines Select-RAM, NGBuild, XABEL- (θ ). Overall device reliability decreases expo- CPLD, Zero+ and EZTag are JA when adapting the nentially as junction temperature increases. In trademarks; and “The original XC4000 architecture to create the new Programmable Logic Com- general, junction temperatures need to stay XC4000EX and XC4000XL series devices fur- pany” is a service mark of below 125° C for plastic packages and 150° C Xilinx, Inc. All other trade- ther minimizes interconnect capacitances. As a marks are the property of for ceramic packages. result, these devices can be fully utilized and their respective owners. Several factors determine the power con- operated with high system clock frequencies, sumption within an FPGA, including the sup- R even when using plastic packages. ply voltage, the architecture of the device, Continued on page 4 ○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○ GUEST EDITORIAL HardWire ASIC + LogiCORE = Reduced Time-to-Volume by RICK PADOVANI ◆ Marketing Director
Increasingly, systems designers in fast-moving, competitive markets cannot tolerate the long development cycles required for the successful implementation 3 of conventional mask-programmed gate arrays. Successful gate array develop- ment time can range from six to 18 months or more, and often requires addi- tional time for re-spins. In addition, the demand for rapid product enhance- ments has dramatically shrunk typical product life cycles. As a result, leading-edge designers must look for innovative development approaches to reduce risk, while gaining a time-to-market advantage. As the performance and density of Field-Programmable Gate Arrays (FPGAs) increase, many traditional mask-programmed gate array designers are taking advantage of the fast development time and flexibility of FPGA technology. Sub- micron CMOS process technology and architectural enhancements are making die sizes more cost-effective; and price points for FPGAs are declining rapidly. In fact, in the lower complexity ranges, FPGAs have been approaching price parity with mask- programmed gate arrays as die sizes in both technologies have become pad-limited. In the higher complexity ranges, where the cost difference between FPGAs and masked-programmed devices is still significant, the HardWire ASIC model, pioneered by Xilinx in 1989, has gained broad market accep- tance. Xilinx FPGA-to-HardWire ASIC migration provides total life-cycle ❝ FPGA-to- management of high-volume applications by combining the advantages of Xilinx FPGA development time and flexibility with the cost-efficiency of masked- HardWire migration programmed devices. The technology enables designers to achieve the fastest possible time-to-market and the lowest overall production cost. provides total life-cycle While the FPGA is in use, late design changes or system upgrades can be accommodated. Production ramps up much more rapidly than it would management of high- with a conventional ASIC approach. When the design is final, the systems volume applications.❞ vendor has the option of requesting a HardWire conversion from Xilinx, leaving no gap between development completion and high-volume produc- tion. This represents a major competitive advantage for our users. The efficiency of using pre-verified LogiCORE modules for high-complexity FPGA de- sign really brings the HardWire advantage into focus. The system hardware and software verification process can proceed much more rapidly using FPGAs. Concurrent hardware and software engineering is facilitated by virtue of the FPGA, as opposed to the longer development and prototyping time of conventional mask-programmed gate arrays. Hard- ware corrections, as well as software corrections, can be implemented at the same time, so designers have the option to make optimal corrections, rather than using software patches to work around hardware bugs. The HardWire conversion process preserves the total func- tionality and performance of the design, including the LogiCORE module. For example, user-specific PCI designs can be implemented very cost-effectively for high-volume production using the Xilinx PCI LogiCORE module and HardWire ASIC devices. A fully-compliant PCI core and up to 10,000 gates or more of user-specific logic can be implemented for less than $20 in volume quantities. Continued on page 10 R THE FAWCETT (con’t)
Continued from page 2 For example, the figure shows the power careful not to fall victim to “bait and switch” consumption of an XC4036EX device (a 5V tactics, wherein a designer is enticed to select a FPGA) when the entire device is filled with high-density FPGA based on performance 8-bit and 16-bit counters. (In an 8-bit counter, claims and the price of plastic-packaged parts, 25% of the flip-flops toggle each clock pe- only to later discover that power consumption riod, while in a 16-bit counter 12.5% of the considerations dictate the use of a more expen- flip-flops toggle; thus, the power consump- sive package and/or slower speed operation. 4 tion with the 8-bit counter benchmark is about twice that of the 16-bit counter.) The Estimating/Minimizing Consumption horizontal lines on the graph correspond to Unfortunately, power consumption within the maximum power dissipation recom- an FPGA is design-dependent and can be mended for various package types (without difficult to calculate prior to implementing the heat sinks or fans). Thus, it is safe to operate design. Charts provided in Xilinx data sheets the full XC4036EX device in a low-cost HQFP provide dynamic power consumption values plastic package at speeds up to 70 MHz for typical design elements (for example, the without requiring heat sinks or fans. power consumption of one XC4000E CLB In contrast, some other vendors’ high- flip-flop driving its neighbor and nine lines of density FPGAs have interconnect structures interconnect is 0.2mW per million transitions based on a multiplicity of long metal traces. per second); these can be used to derive The high-speed switching of these long useful power consumption estimates, but traces, with require the designer to estimate the average their inher- percentage of nodes in the FPGA design that 4036EX ently larger switch with each clock transition. In any 14.00— 8-bit capacitance, event, it is highly-recommended that users of counter 12.00— results in high-density FPGAs always measure device power consumption (usually by measuring 10.00— considerably the total I current at actual system fre- higher power CC 8.00— 16-bit consumption. quency) upon completion of a design to counter insure that the right package and cooling 6.00— 411 PGA As a result, methods are being employed. 4.00— 304 HQFP while the data sheets offered Some design techniques can be employed Active Power (W) 432 BGA 2.00— by these ven- to minimize FPGA power consumption (see XCell 19, page 34). As mentioned earlier, 0.00— dors boast of 0 20406080 high densities users of high-density, high-performance Device Full Frequency (MHz) devices should strongly consider the use of Counters and perfor- mance rates, of FPGAs based on the 3.3V supply voltage these rates can standard, such as the XC4000XL series. Most only be reliably sustained by using expensive power dissipation is produced by external ceramic packages (and even then often re- capacitive loads on output buffers, so those quire the further expense of heat sinks and loads should be minimized and outputs fans). For example, one competitor’s device, should be switched as infrequently as pos- with a density roughly equivalent to the sible. Similarly, use clock enables to switch XC4036EX, was benchmarked using the same off inactive portions of circuits, preventing methodology as described above. Due to internal nodes from toggling unnecessarily. power dissipation limits, it can be run only at Use the place and route tools to maximize the speeds below 18 MHz in plastic packages, performance of the design, even if the result- and at speeds below 35 MHz in ceramic ing performance far exceeds requirements. packages; at any higher performance level, Circuits that are able to run faster can do so heat sinks and fans will be needed. because of lower routing capacitance; conse- Thus, users of high-density FPGAs must be quently, they dissipate less power at any given clock frequency. ◆ CUSTOMER SUCCESS FPGAs Bring Needed Flexibility to Telecomm Testers
The rapid proliferation of new services tured here, is a typical example of the use of and standards complicates the already chal- FPGAs in the various system modules. This lenging task of meeting the high-performance module can act as both an ATM cell simulator needs of the telecommunications equipment and an ATM cell monitor. The majority of the market. At ICT Electronics (Barcelona, logic on the board is implemented in 11 differ- 5 Spain), a leading manufacturer of telecom- ent FPGAs, ranging from the XC4013E to the munications test equipment, the flexibility of XC3042A device. The FPGAs implement a wide SRAM-based FPGA technology plays a key variety of logic functions, including finite state role in meeting that challenge. machines, counters, register files, multiplexers/ Since 1989, designers at ICT Electronics demultiplexers, and decoders. The XC4000E have exploited the reconfigurable nature of architecture’s on-chip memory capability is Xilinx FPGA technology to create high- used to efficiently implement large register files performance, cost-effective test equipment. and look-up tables used to identify virtual Their systems take advantage of the recon- channels. The FPGA’s dedicated arithmetic figurable nature of Xilinx FPGAs in two ways: carry logic is key to implementing the large counters needed to simultaneously monitor up ➤ to implement multiple operations with the to 16 communication channels. Utilization of minimal amount of logic. these devices ranges from about 65% to over ➤ to enable field upgrades. 90%, and system clock speeds range from 512 KHz to 40 MHz. Often, multiple potential bitstreams are Data I/O’s Synario design software was available for a particular FPGA device, so the used to create the FPGA FPGA is configured (and reconfigured) depen- designs for the ATM dent on the user’s selection of a particular module. The designs command or operating mode. When the vari- were entered in the ous industry organizations issue new standards VHDL hardware or recommendations, systems can be upgraded description lan- in the field by supplying new FPGA configura- guage, and tion bitstreams. Typically, the FPGAs are con- implemented figured using the asynchronous peripheral using the mode, with the configuration bitstreams stored Xilinx on a hard or floppy disk within the system. XACT- Equipment can be easily updated by sending Foundry out new configuration bitstreams via floppy tools. Both PC disk or over the Internet. and HP workstation For example, the new Flexacom Analyzer/ platforms were employed. Generator for broadband ISDN digital trans- As noted by Faustino mission systems contains a mix of about one Cuadrado, lead designer at ICT Elec- hundred XC3000 and XC4000 series FPGA tronics, “The FPGAs’ reconfigurability pro- devices in a typical system configuration. This vides an important advantage. ATM standards powerful instrument allows users to work are changing every day, so any equipment separately or simultaneously with both the with ‘closed hardware’ will quickly become Synchronous and Plesiochronous Digital obsolete. Flexacom ATM can be updated Hierarchies (SDH and PDH). Optional mod- easily, via floppy or remote control, helping ules support Jitter and Wander analysis and make Flexacom the best solution for B-ISDN generation. ◆ The Flexacom system’s FPGA-based asyn- networks.” chronous transfer mode (ATM) module, pic- More Enhancements to WebLINX Several significant enhancements have been added to SmartSearch and Agent tools, and “Expert Journals” are now WebLINX, the Xilinx World Wide Web site (www.xilinx.com). part of the Technical Answers section. A further addition is In addition to posting hundreds of new documents, improve- the “LogiCORE Lounge”, designed to provide the latest and ments have focused on making technical information easier to most-accurate information on our LogiCORE products, in- find. For example, new capabilities have been added to the cluding the new PCI CORE Generator (see page 14).
6 SmartSearch & Agents the agent sign-up page or the Popular Agents WebLINX SmartSearch lets you quickly page. These Agents range from alerting you to find information on the Xilinx site and any of changes on the Xilinx “What’s New” page to the over 50 PLD-industry sites that we index. keeping you abreast on PCI developments Agents automatically notify you of changes to throughout the industry. Furthermore, the for- those sites by sending you an e-mail notifica- mat of the e-mail notification has been updated tion whenever new documents are added that to provide additional information about new match your designated areas of interest. Several documents that have been posted, as well as recent improvements have increased the utility document revisions. Thus, at a quick glance, ❝SmartSearch of these tools. you can decide if the information is important In an effort to help you find information to you, without spending a lot of time “surfing” improvements faster, two new SmartSearch pages have been the sites. Remember, you are in complete con- are intended added. These pages include checkboxes to help trol, and can start and stop the e-mail activity at narrow your search to specific topics, such as any time simply by deleting or creating agents. PCI or DSP, and specific sites (or even areas to produce Expert Journals within those sites!). “Expert Journal” pages are a useful recent Other SmartSearch improvements are in- significantly addition to the “Technical Answers” area of tended to produce significantly better results WebLINX. Here, Xilinx Technical Support from your search queries. Searches now include better results experts provide the latest installation and matching to document “keywords.” For in- “getting started” tips, top solutions, design from your stance, searching for “install” might find hun- techniques and software patches for Xilinx dreds of documents, while there might only be ❞ Foundation software and Xilinx Alliance search queries. a dozen documents that really directly address interfaces to Cadence, Mentor Graphics, the topic of Install. The use of keywords will Synopsys and Viewlogic tools. ensure that those dozen documents are pre- sented at the top of the search results list. Key- LogiCORE VIP Lounges words will be added to the documents on our The LogiCORE VIP Lounge is a password- site over the next few months, so you should protected area; registered LogiCORE product see continued improvements in your search owners have access. This site is designed to results. Searches also can be narrowed to just provide the most current information and document titles by clicking an op- design files for our LogiCORE products, tion on the search page. This will including product enhancements, design tips, significantly reduce the number of known issues, new releases of design files and matches, and result in locating much more. If you are a current LogiCORE documents that more closely match PCI user, register today. your interests. The LogiCORE VIP Lounge also is the site While over 2,000 visitors to of the first web-based tool for fast FPGA core WebLINX have signed up for Agents, design, the CORE Generator for PCI (see page only a small percentage have actually 14). The CORE Generator for PCI will be created them. To make SmartSearch merged with the CORE Generator for DSP Agents even easier to use, Agents for later this year to form a generic framework several popular topics now can be for providing and using both LogiCORE and created simply by checking a box on AllianceCORE products. ◆ “Power of Innovation” Seminars Reach WorldWide By the time this publication reaches you, to register for an upcoming seminar in South- the Xilinx seminar series The Power of Inno- east Asia, please contact your local Xilinx vation will be drawing to a close. The semi- sales representative. ◆ nar discusses programmable logic solutions for digital systems, with an emphasis on new 7 products such as the XC4000XL FPGA family, the XC9500 CPLD family, and the LogiCORE drop-in modules. During May and June, these one-day semi- nars are being held at more than 40 locations throughout North America, Europe, and Ja- pan. Seminars are scheduled for several loca- tions in Southeast Asia in late July. To those of you who attended one of these seminars, our sincere thanks for your time. If you were unable to attend, but would like to receive a copy of the seminar materials or information about new Xilinx products, or
TECHNICAL TRAINING UPDATE XACTstep Version M1 Training to Debut With the impending release of the on courses provide the user with an overall XACTstep version M1 software (see page 12), better knowledge of how to use the Xilinx the Customer Education Group has focused tools and devices in conjunction with the on the development of new technical various third-party design entry, synthesis education courses that coincide with this and verification tools. new software release. In the same time frame as the XACTstep The three-day XACTstep version M1 course version M1 release, a one-day M1 update is organized in a modular manner. Basically, course will be offered to the Xilinx user the course is divided into two sections: community, providing further information low-density design (one day) and high- and specifics on the new release. density design (two days). This method of Dates and schedules for both the XACTstep organization allows the course to focus on the M1 and XACTstep M1 Update courses will be use of all the Xilinx tools, including the specific disseminated in this publication and on tools associated with the XACTstep version M1 WebLINX (www.xilinx.com). software release. The 1997 Educational Services Brochure The XACTstep version M1 course will be will be updated at mid-year with all of the complemented by one- and two-day “bolt-on” latest course descriptions and schedule infor- courses focused on the CAE interfaces mation. This updated brochure will be avail- supported and sold through Xilinx (e.g., able at all Xilinx sales offices in July. ◆ Foundation, FPGA Express, etc.). These bolt- New Learn about the newest Xilinx products and services through our extensive library of prod- uct literature. The most recent pieces are listed below. To order or to obtain a complete list of Product all available literature, please contact your local Xilinx sales representative. ◆ Literature TITLE DESCRIPTION NUMBER Corporate Product Overview Brochure Features & Benefits #0010130-06 Xilinx Packaging Guide Technical Data #100120 AppLINX CD Technical Data #106425-04 8 Software Software Quick Reference Card Technical Data #0010104-07
UPCOMING EVENTS
Look for Xilinx tech- Design Automation Electronic Design Electronic Design Auto- PC Card ‘97 nical papers and/or Conference (DAC) Automation and mation and Test Confer- Sept. 17-18 June 9-13 Test Conference ence (EDA&T) Santa Clara, CA product exhibits at Anaheim, CA (EDA&T) Aug. 25-26 these upcoming indus- Aug. 18-19 Hsinchu,Taiwan DSP France try forums. For further Embedded Computing Shanghai, China Sept. 17-19 information about any June 17 International Workshop Paris, France Santa Clara, CA Electronic Design on Field Programmable of these conferences, Automation and Logic and Applications EuroDAC please contact Embedded Computing Test Conference (FPL ‘97) Sept. 22-26 Kathleen Pizzo June 19 (EDA&T) Sept. 1-3 Dusseldorf, Irvine, CA Aug, 21-22 London, UK Germany (Tel: 408-879-5377 Seoul, Korea FAX: 408-879-4676). Japan PLD Conference DSP World Expo DSP Germany ◆ June 25-27 Sept. 15-17 Sept. 30-Oct. 1 Tokyo, Japan San Diego, CA Munich, Germany
FINANCIAL RESULTS Another Record Fiscal Year As in every year since Xilinx was all-time high of about 1,700 new software founded, the company again established a seats. Earlier this year, Xilinx announced new annual revenue record for fiscal year the shipment of its 35,000th software 1997 (April 1996 to March 1997). Fiscal design system. 1997 sales revenue totaled $568.1 million, Looking forward, Chief Executive up from $560.8 million in fiscal 1996. Officer Wim Roelandts commented, “Fiscal Revenues for the fourth quarter (January- 1998 is shaping up to be an exciting year Xilinx Inc. stock is traded March 1997) reached a record $151.8 for Xilinx. Our density and performance on the NASDAQ million, an 11.9% increase from the leadership coupled with our leading edge exchange under previous quarter. software solidifies our position as the symbol XLNX. While revenue growth for the fourth premier PLD company. As we continue quarter was strong across all product to engineer more comprehensive solutions lines, sales of the flagship XC4000 series for our customers, and aggressively FPGA products were particularly robust, converge on the sweet spot of the gate increasing by more than 24% sequentially. array market, I am confident in our Development system sales reached an opportunities for future growth.” ◆ PRODUCT INFORMATION-COMPONENTS
Industry’s Fastest 5V XC4000E-1 Series Offers FPGAs in Production 25% Performance Gain As introduced in XCell 24, XC4000E devices featuring the new -1 speed grade are now shipping in production volumes. Based on an optimized 0.5µ three-layer-metal process, the new -1 devices support typical system clock speeds in the 80 MHz range — 20-25% higher performance than the 9 XC4000E-2 FPGAs, previously the fastest devices in the XC4000E family. Extensive performance analysis using comparable 5V FPGAs from other vendors has ○○○○○○○○○○ confirmed that the XC4000E-1 device is 5-20% high-speed telecommunications can benefit faster in end-user applications. The analysis from this FPGA family’s increased perfor- included three different types of benchmarks: mance capabilities. ➤ the actual implementations of representa- The performance leadership of the XC4000 tive macro- and core-level functions from series complements its highly-integrated feature set, including on-chip three-state key application areas. ○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○ buffers, dedicated arithmetic carry logic, ➤ the actual implementations of representa- multiple global clock networks, and on-chip tive “real-world” system designs of various Select-RAM memory. The XC4000E family density and performance levels obtained spans from 237 to 2,432 logic cells (approxi- from systems manufacturers. mately 2,000 to 25,000 logic gates), and is ➤ the guaranteed system I/O speed, as available in a variety of packages. measured by adding the clock-to-out The Xilinx Foundation and Alliance Series and global-clock-setup specifications development systems support the new obtained in product data sheets. XC4000E-1 speed grade. The Foundation series is a fully-integrated, ready-to-use, When compared with its closest com- Windows-based solution, including support petitor, the XC4000E-1 FPGA delivers 20% for industry-standard HDLs, synthesis, sche- better performance, on average, for the scaled matic entry, simulation, and the XACTstep functions, and 12% better performance for the implementation tools. The Alliance series real-world designs. System I/O speed for the allows the use of the XACTstep tools with the XC4000E-1 device is 5% better than the fastest industry’s most-popular third-party EDA tools; competitive device. this series of development system products The XC4000E-1 device expands the power provides open-system benefits with support of the LogiCORE PCI design solution. This for industry-standard design methodologies performance improvement extends full PCI and interfaces, including EDIF, VHDL (VITAL compliance to 20,000-gate densities and 95), and Verilog/SDF. increases overall design flexibility for PCI Please contact your local Xilinx sales interface designs. Other emerging applica- representative for current pricing R tions such as networking, multimedia, and information. ◆ Five XC9500 CPLD family members are mixed 3.3V/5V system compatibility, pin-to- XC95288 now in production, including the new 288- pin speeds as fast as 5 ns, and a large variety CPLD Enters macrocell XC95288 device (Table 1). The of density/package combinations. Full foot- XC9500 family continues to lead the industry print-compatibility whenever multiple densi- Production with user-proven in-system-programmability ties share a common package type facilitates and pin-locking capabilities, support for a full design migrations between family members suite of IEEE 1149.1 (JTAG) instructions, (Table 2). ◆
Table 1: XC9500 Device Family Table 2: Available Packages and Device I/O Pins (not including dedicated JTAG pins)
XC9536 XC9572 XC95108 XC95144 XC95216 XC95288
Macrocells 36 72 108 144 216 288 XC9536 XC9572 XC95108 XC95144 XC95216 XC95288 Usable Gates 800 1,600 2,400 3,200 4,800 6,400 44-Pin VQFP 34 10 Registers 36 72 108 144 216 288 44-Pin PLCC 34 34 t (ns) 5 7.5 7.5 7.5 10 15 PD 84-Pin PLCC 69 69 t (ns) 4.5 5.5 5.5 5.5 6.5 8.0 SU 100-Pin TQFP 72 81 t (ns) 4.5 5.5 5.5 5.5 6.5 8.0 CO 100-Pin PQFP 72 81 81 f (MHz) 100 125 125 125 111 95 CNT 160-Pin PQFP 108 133 133 fSYSTEM (MHz) 100 83 83 83 67 56 Availability NOW NOW NOW 4Q97 NOW NOW 208-Pin HQFP 166 168 352-Pin BGA 166 192 Notes:fCNT = Operating frequency for 16-bit counters
fSYSTEM = Internal operating frequency for general purpose system designs spanning multiple FBs.
GUEST EDITORIAL Continued from page 3 Customer re-verification of the complex design re-targeting and verification are design is not required with the HardWire solu- virtually eliminated. tion; Xilinx guarantees equivalent functionality HardWire conversion is superior to and performance. In some cases (depending conventional gate array conversions because on the design), speed improvements can be the HardWire conversion is based on “design obtained in the HardWire device by eliminating mapping” at the physical level, rather than delays associated with programmable intercon- common gate array “re-targeting” that begins nects in the FPGA, and because of the shorter at the design capture level. Gate array routing delays associated with the re-targeting actually requires a second ❝ smaller HardWire die size. complete design cycle after the FPGA dev- HardWire About HardWire elopment; re-targeting techniques alter the netlist and require significant re-verification HardWire technology allows ASIC devices are effort (and high risk!). The HardWire process users to “design once” with FPGAs. reduces the user’s expense of time and engi- available to support It uses FPGA-specific gate arrays neering resources, while offering guaranteed and libraries, along with a special- each Xilinx FPGA “socket compatibility” and very low risk. Fur- ized conversion methodology thermore, the production test program for the family.❞ patented by Xilinx that uses the HardWire device is developed by Xilinx using circuit and physical layout data of a scan path insertion and ATPG (automatic the routed and verified FPGA netlist to gener- test pattern generation) methodology. No ate a similar physical mapping of equivalent vectors are required from the user and >95% logic cells in the mask-programmed HardWire fault coverage of the user’s logic is provided. device. This ensures circuit equivalence and HardWire ASIC devices are available to timing compatibility. Risks associated with support each Xilinx FPGA family. ◆ XC4085XL FPGA Sets New Density Standard This May, Xilinx began shipping tional routing available in the XC4000XL Extends sample quantities of the new XC4085XL family architecture, along with improved Density of FPGA. The XC4085XL device is now the routing algorithms in the new M1 release, largest member of the XC4000XL family result in dramatically-reduced software com- XC4000XL (a position previously held by the pilation times for these high-density FPGAs. FPGA XC4062XL device). It is the industry’s The XC4085XL device is available in 560- leading high-performance 3.3V FPGA pin super ball grid array and 559-pin pin grid Family solution, with 7,448 logic cells (3,136 array packages. Please contact your local by 40% CLBs) and 448 I/Oblocks. Xilinx sales representative for the latest price With the introduction of the high-den- and availability information.◆ 11 sity XC4062XL and XC4085XL devices, FPGA technology can now effectively address new, high-density markets such as telecommunications, data processing and industrial applications. As FPGA costs decline and densities increase, all gate array designers who are currently using devices with up to 100,000 gates can now secure the convenience and time-to-mar- ket benefits of FPGA technology. The development system software for the XC4000XL family, available now, is included as part of the new XACTstep version M1 design environment. The addi-
XC6264 Added to XC6200 Family of RPUs Xilinx recently announced the addition out” unnecessary pieces of a design to save of the 64,000-gate XC6264 device to the silicon space or by changing logic on-the-fly XC6200 family of reconfigurable processing to increase performance. units (RPUs). The XC6264 and XC6216 RPUs Innovative XC6200 features such as fast are the only programmable logic devices that partial reconfiguration, a built-in microproces- have been optimized for reconfigurable logic sor interface and an open bitstream format applications such as real-time adaptive filter- make RPUs the component of choice for ing and algorithm acceleration. system designers exploring or using dynamic While FPGAs traditionally have been used hardware designs. to implement individual logic designs, RPUs are intended to support multiple designs in a single piece of silicon — either by “swapping 3 PRODUCT INFORMATION-DEVELOPMENT SYSTEMS Xilinx Delivers Next Generation ○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○ New XACTstep M1 Places and Routes 1,000 Gates per Minute With a 25% Performance Increase
The new XACTstep version M1 software XACTstep M1 User Benefits technology enables users at every design Maximum Design Performance — Version M1 level to increase design performance, lever- software enables maximum design performance by age standards-based, high-level design meth- providing a unique combination of advanced algo- odologies, and quickly receive future soft- rithms and interactive tools. Designer productivity is ware updates and device support for Xilinx greatly enhanced with its simple, push-button flows and optional auto-interactive tools. User testing has FPGA and CPLD solutions. shown that version M1 software used with Version M1's design Version M1.2 is available now for the PC XC4000XL devices results in 70 percent shorter run flow engine. and for UNIX work- times, up to a 25 percent performance improvement, 12 stations, including and the ability to place and route devices with up to Sparc-compatible 100 percent utilization with a push-button flow. SunOS 4.1.3 and Modular Software System — The modular architec- Solaris 2.3, HP-UX ture of the M1 system will allow Xilinx to rapidly and IBM RS6000 deliver incremental technologies, new features, device platforms. Current support and new versions of its leading software product families. New feature sets can now be re- users of XACTstep leased independently; as a result, users can quickly 5.2/6.0 with an active complete designs without having to re-learn new support or mainte- tools as enhancements are made. The investment nance plan will re- Xilinx has made in the M1 technology ensures that ceive a free upgrade the continuous delivery of innovative device architec- to XACTstep M1.3; tures and improved software solutions can be accom- plished more rapidly and more predictably. upgrades are sched- uled to start shipping Methodology Flexibility — High-level design in mid-summer. methodologies are becoming the methodology choice for the design of complex programmable XACTstep version logic. Version M1 software delivers programmable M1, developed as a logic specific high-level flows. The flows provide result of the Xilinx high-quality, high-performance and optimized re- merger with sults, and allow fast, flexible design changes and NeoCAD, Inc., dra- iterations, matching the way that engineers design. matically improves Xilinx users often employ a mixture of graphical and language-based design entry methods to design their design performance Schematic editing an products. The flow is built to complement existing XC4028 device in a using advanced placement and routing algo- schematic-based design methods while providing an BG352 package. rithms, powerful “auto-interactive” tools that easy-to-learn environment for Hardware Description deliver the choice between a push-button or Language (HDL) based design. Xilinx recognizes manually-directed design methodology, and that design environments are variant and, therefore, support for industry standard-based design has created a flexible system, enabling the user to choose the best methodology for the environment flows, including EDIF, SDF, VHDL (Vital) and and design challenge. R Verilog support. Software Platform Product Configurations Please contact your XACTstep version M1 software delivers local Xilinx sales repre- all these benefits through both the sentative for the latest XACTstep Foundation and Alliance Series availability and pricing software solutions. The Foundation Series information. Inquiries features a complete, front-to-back design regarding the status of solution based on industry-standard software maintenance HDLs and push-button design flows. The contracts should be Alliance Series focuses on open systems directed to Xilinx Cus- integration, with the industry’s most tomer Service. ◆ extensive set of third-party EDA vendor The logic block editor. integration. 13 Xilinx Now Shipping Cadence Interface Kit
To provide the best possible support to our users, are now dedicated to developing and testing Concept Xilinx and Cadence Design Systems have mutually and Verilog libraries; dedicated Cadence experts have agreed to have Xilinx take over development, sales and been added to the technical support organization. Xilinx support of the interface kit for using Cadence design has developed detailed documentation on the design entry and simulation tools with the Xilinx XACTstep flow, including a new guide for users migrating from system. Cadence has discontinued sale and support of XACTstep v5.2.1 to M1. their Xilinx interface kit; the last Cadence version of that Cadence will continue to sell and support its HDL kit is the 97A release. synthesis solution for Xilinx components. Synergy synthe- A new Cadence interface kit is available directly from sis libraries for the XC4000EX family will be available on Xilinx. The currently-released beta version is for the the Cadence ftp site by early summer. (For more informa- XACTstep version M1.2 release — full production will start tion on the availability of synthesis libraries, please contact in conjunction with the introduction of M1.3, scheduled the Cadence support organization in your area.) for mid-summer. This new interface kit has superior sche- Cadence discontinued sales of Xilinx place and route matic and HDL support for all Xilinx architectures, includ- tools in November 1996 — version 9604 was the last ing the XC4000EX/XL FPGA families. The new release release. All in-warranty owners of these tools can supports EDIF netlist entry, VHDL- and Verilog-based receive the latest XACTstep package by calling Xilinx design, as well as both functional and timing simulation. customer service. The VITAL libraries in XACTstep M1 will work with the If you are currently a Cadence Design Systems Cadence Leapfrog VHDL simulator. (The EDIF netlister is customer and are using Xilinx tools purchased available from Cadence on its ftp site.) from Cadence, please fax a copy of the following Xilinx is committed to fully support our Cadence information to the Xilinx Customer Service group users, including the timely introduction of schematic and (408-559-0115) — company name, user name, mail- HDL libraries for new component architectures. Re- ing address, telephone number, fax number and sources in engineering and software quality assurance e-mail address. ◆ CORE The First Web-Based Generator for PCI: Development Tool for FPGA Design This spring, Xilinx introduced an innova- parameters by selecting the appropriate values tive, web-based tool that radically simplifies in pre-defined menus. The GUI prevents de- the use of cores for FPGA design. The new, signers from entering invalid parameters. On- on-line CORE Generator tool facilitates core line help is available, as well as application usage by enabling designers to instantly ac- notes describing the complete design flow cess, customize, and download core designs from core configuration to implementation. using WebLINX (www.xilinx.com). The CORE Generator allows the designer to It features an intuitive graphical interface, integrate the LogiCORE PCI module using any thereby shortening the learning curve for logic chosen tool environment, including VHDL, designers. Initially designed to support users Verilog, or schematic-based design. (Previ- of the LogiCORE PCI module, the CORE Gen- ously, Viewlogic schematic entry tools were erator will be extended to support other Xilinx required to modify and customize the design.) LogiCORE and third-party AllianceCORE prod- The CORE Generator creates all the files ucts later this year. needed to integrate the PCI core within the 14 The CORE Generator FPGA design and verify the results, including: tool for PCI introduces a 1) a netlist with constraints that ensure that timing new methodology for is met without any manual tuning. acquiring and using cores 2) a “wrapper” used to instantiate the core in a with FPGAs. Since the VHDL, Verilog or schematic-based design. tool executes on the web, 3) a VHDL/Verilog simulation model for functional LogiCORE PCI users verification. always have access to the These files are then downloaded over the latest versions of the web to the designer’s development platform. cores (as well as the The PCI cores created by the CORE Gen- latest product informa- erator are “firm” cores, with relative placement tion). “Customized” cores and timing constraints embedded in the netlist are created by the CORE to ensure that the performance of the imple- Generator based on user- mented design meets the requirements of the defined parameters, al- PCI specification. Thus, PCI timing can be met lowing designers to easily without any manual tuning of the core, and, create and download as a result, engineering resources can be fo- their unique versions of cused on the system-level design, potentially the core netlist, regardless saving months of development time. Figure 1: CORE of the design tools and methodologies used Figure 2 compares typical development Generator tool for for design entry and simulation. PCI, main menu times and costs for designing a PCI interface Using CORE Generator from scratch using a generic, synthesizable To create a PCI core netlist using the CORE core and using a proven LogiCORE PCI core. Generator, designers enter their system’s pa- Visit the VIP Lounge rameters by using the program’s graphical user To access the tool, use a Java-enabled web interface (GUI). The GUI mirrors the already- browser such as Netscape 3.0 or Microsoft familiar PCI Specification Standard table. For Explorer 3.0 to visit WebLINX (www.xilinx.com). example, the GUI includes a copy of the con- The CORE Generator is part of the new figuration space header from the PCI specifica- “LogiCORE VIP lounge” site that holds useful tion (Figure 1); the user simply enters the Continued on page 22 The Xilinx DSP CORE Generator Automated Tool Generates Parameterized DSP Designs Optimized for FPGAs Today’s FPGAs offer an attractive solution for the computationally-intensive functions found in digital signal processing (DSP) appli- cations. By combining the flexibility of a gen- eral-purpose, programmable digital signal processor with the speed and density of a custom-hardware implementation, FPGAs can provide increased DSP system performance at a reduced system cost. However, to achieve this high level of FPGA-based DSP performance, you must craft the DSP algorithm into the architecture of the FPGA. Ironically, many DSP designers, while well-versed in the algorithmic approaches used when programming conventional DSP proces- sors, are not familiar with distributed arithmetic Figure 1 15 and similar techniques applicable to the highly- parallel structures of FPGA-based solutions. contains support for the generation of serial Rather than learning all the details of these distributed arithmetic FIR filters, one-dimen- approaches and their implementations, Xilinx sional ROM- or RAM-based correlators, Comb users can take advantage of the new DSP filters, integrators, delay elements, and high- Figure 2: DSP CORE Generator. With the DSP CORE Genera- speed area-efficient parallel multipliers. Sup- Design Explorer Tree tor, complex parameterized DSP building port for Comb and Integrator filter blocks, optimized for the target FPGA architec- functions facilitate the implementa- ture, can be implemented automatically and tion of Hogenauer filters. integrated into Xilinx FPGA designs. This first release (Alpha 1.0) The DSP CORE Generator accepts param- supports Windows 95 (PC only), eters from a dialog box (Figure 1), and out- and can be obtained through any puts a completed design in the form of a of the Xilinx DSP FAEs in the US netlist, complete with the appropriate relative- and Europe, or through DSP placement constraints. The tool also produces marketing for Japan and Asia. a symbol for the module suitable for use with This release requires Foundation a schematic editor, VHDL / Verilog software, since it accesses the instantiation code, and behavioral models. Metamor synthesis tools. Thus, the CORE Generator meshes smoothly The next release, scheduled for with any combination of HDL and schematic- mid-summer, will add support for based design methodologies. additional functions, including The user interface for the DSP CORE Gen- parallel FIR filters, IIR filters erator delivers all of the parameterized cores, (biquads), Fast Fourier Transforms, fixed cores, and the DSP Toolbox Library of and FIFO buffers. The summer parameterized base building blocks, as well as release also will include support for all of the data sheets and documentation, workstation platforms, and will through a hierarchical, expandable tree struc- work with all the XACTstep pack- ture similar to Windows 95 Explorer (Figure 2). ages, eliminating the requirement The initial release, currently available, for Foundation software only. ◆ DESIGN HINTS AND ISSUES ○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○ Some Simple XC9500 Prog In-system-programmable (ISP) CPLDs To take advantage of ISP, some simple guidelines provide remarkable capabilities for logic de- must be followed. These guidelines are straightfor- sign. They permit the development of non- ward — but some users overlook them and be- volatile designs without the aid of a device come frustrated. As usual, frustration is avoided by programmer. planning. In essence, this capability is obtained by Charge pumps (Figure 1) derive their internal incorporating the device programmer within “supervoltages” by pumping the external voltage
the CPLD device itself. Internal circuitry takes provided at the VCC pin(s). Charge pumps are de- the user-provided pattern and sets the internal signed to be robust, but they do require simple care. storage cells automatically. The circuits in- The various stages of the pump are mathematically
volved include a programming state machine related to the VCC level, so it is critical that VCC be and a charge pump. within the specified range for the pump to achieve its correct internal voltage. With the XC9500 family, this range is between 4.5 and 5.5 volts. While this sounds simple, it can be difficult to
ensure in practice. VCC voltage can be measured at the card edge or, preferably, right at the CPLD
device’s pins, but noise on the VCC signal due to 16 the dynamic behavior of the PC board while the system is running can be difficult to detect and quantify. However, as described above, it is critical
that the ISP circuitry be provided a stable VCC so the charge pumps can function properly. The usual solution is to attach decoupling capacitors right at
the CPLD VCC and VCCIO pins terminating directly to Figure 1: Simplified Charge Pump Diagram the nearest ground plane. The stability of the board signals that drive CPLD devices’ JTAG circuitry is of equal impor- For the Xilinx XC9500 family, the state tance. The JTAG specification dictates that the TMS machine is driven by extended JTAG instruc- and TDI signals be “pulled up” to the system tions, and uses the same 4-pin set used by the power supply, but does not include the specific IEEE 1149.1 test commands, thereby minimiz- resistance value required. This creates an interest- ing the chip overhead needed to provide ISP ing quandary, particularly for long JTAG ISP chains capability. Coming from the JTAG controller, across multiple vendor chips (Figure 2). the bits are delivered to the ISP controller, Figure 2a shows a mix of JTAG chips, attached in which forwards them to the target locations, a standard format. Figure 2b shows that each chip where the charge pump programs them into may provide an internal pullup resistor of a different the appropriate bit locations. value at each site; in Figure 2b, the pull-up resistors ❝ R To take advantage of ISP, some simple guidelines must be followed. These guidelines are straightforward...❞ gramming Guidelines
Figure 2a: Ideal JTAG Chain
17
Figure 2b: More “real” JTAG Chain
are shown external to the chips, but in reality, parallel termination resistance can be they are contained inside the respective chip — attached. This will have to be determined and are out of the designer’s control. Luckily, experimentally. most JTAG TCK speeds are well below 10 ➤ If prototype difficulty persists, consider MHz, minimizing transmission line effects. breaking up the on-board JTAG chain with Recommendations that will aid in trouble- additional buffers. shooting problems caused by impedance mismatches on the JTAG signal lines include Finally, continuing improvements to the the following: software protocols are increasing the reliabil- ity of in-system programming. The new ➤ For long JTAG chains (greater than 5 or 6 XACTstep M1 JTAG download software in- chips) include a buffer site. This is a point cludes the latest ISP protocols to best manage where the external cable may be isolated the actual delivery of bits into the end sys- from the rest of the chain. tem. Patches and updated releases are made ➤ Consider including sites where series or available at WebLINX (www.xilinx.com). ◆ TECHNICAL QUESTIONS & ANSWERS Viewlogic How do I select the correct Xilinx Hundreds of warnings/errors about libraries for an M1 design within “Unexpanded Blocks,” “No Driver/ Workview Office? Load,” and “Multiple Drivers” appear The file %WVOFFICE%\STANDARD\LIBS.LST when running NGDBUILD. What causes defines the library listings for Workview Office. this, and how can it be prevented? The LIBS.LST file that is shipped with current The flow for a Viewlogic-Xilinx M1 design includes versions of Workview Office contains Xilinx librar- writing out an EDIF file from the Viewlogic design envi- ies for XACTstep v6.0.1. To update this file for ronment. The Viewlogic program EDIFNETO is respon- version M1, you will need to download a file from sible for this, but it must be run with a Xilinx option. our FTP site to replace the current LIBS.LST. The When using the Workview Office or Powerview GUI to file, called M1LIBS.ZIP, can be found at ftp:// run EDIFNETO, enter the word “xilinx” in the Level field. ftp.xilinx.com/pub/swhelp/viewlogic. The command line equivalent for this option is: edifneto -l xilinx design It stops the EDIF netlister at Xilinx primitives.
Mentor When running PLD_EDIF2TIM in the The EDIF file that PLD_EDIF2TIM is processing M1 simulation flow, what causes the should reference this simulation library as Graphics following error: “$SIMPRIMS”. However, in this situation, the // Error: Cannot find library library is referenced as simply “SIMPRIMS” (with- specified “/home/salma/dsprdo/ out the dollar sign). This causes ENRead, the SIMPRIMS” (from: Synthesis/EDIF Mentor EDIF reader used by PLD_EDIF2TIM, to Interface/Miscellaneous 15) look in the current directory for a SIMPRIMS // Error: View “view_1” was not subdirectory, where it expects to find the libraries. created successfully; // thus cannot instantiate “AND0”. To correct this, the EDIF file must be rewritten to (from: Synthesis/EDIF Interface/ Miscellaneous 1C) reference the simprim library as $SIMPRIMS. This // Note: Finding part “SIMPRIMS/ is done using the vendor option in the NGD2EDIF 18 x_and2” (from: Synthesis/EDIF command line: Interface/Eddm Interface 81) ngd2edif -v mentor // Error: Could not find the filename.nga External part “SIMPRIMS/x_and2”. (from: Synthesis/EDIF Interface/ Optionally, if using the Xilinx Design Manager/ Miscellaneous 25) Flow Engine, go to the Implementation Options Timing simulations in XACTstep version M1 use the Template. Under the Interface panel, change the simprim (simulation primitive) library to model Simulation Data Options: Vendor setting to “Men- routed designs. For Mentor Graphics, these simulation tor”. Rerun the Timing stage of the Flow Engine models are located in the $SIMPRIMS library. The and reprocess the EDN file through $SIMPRIMS variable typically is set to $LCA/simprims. PLD_EDIF2TIM.
TECHNICAL SUPPORT RESOURCES
Need technical 1. Find us on the Internet at www.xilinx.com If you don’t have access to the Web or help right now? — We update our “Answers” Web tool daily can’t locate an answer via step #1, Here’s where with the latest application notes, data sheets, then... to start: patches and solutions to your technical ques- 2. Contact your nearest Customer tions. Get immediate answers 24 hours per day! Support Hotline NORTH AMERICA UNITED KINGDOM FRANCE GERMANY JAPAN (Mon, Tues, Wed, Fri (Mon, Tues, Wed, Thur (Monday-Friday 9:30am- (Mon, Tues, Wed, Thur (Mon, Tues, Thur, Fri 6:30am-5pm, Thur 6:30am 9:00am-12:00pm, 1:00- 12:30pm, 2:00-5:30pm) 8:00am-12:00pm, 1:00- 9:00am-5:00pm, - 4:00pm Pacific Time) 5:30pm, Fri 9:00am- Hotline: (33) 1 3463 0100 5:00pm, Fri 8:00am- Wed 9:00am-4:00pm) Hotline: 800 255 7778 12:00pm, 1:00-3:30pm) Fax: (33) 1 3463 0959 12:00pm, 1:00pm-3:00pm) Hotline: (81) 3 3297 9163 or 408 879 5199 Hotline: (44) 1932 820821 Email: [email protected] Hotline: (49) 89 991 54930 FAX: (81) 3 3297 0067 Fax: 408 879 4442 Fax: (44) 1932 828522 Fax: (49) 89 904 4748 Email: [email protected] BBS: 408 559 9327 Email: [email protected] Email: [email protected] Email: [email protected] Need a software update, authorization code, or documentation update? Contact Customer Service: U.S.: 800 624 4782 Europe: (44) 1932-349401 International: 408 559 7778 Increased Design Portability with XACTstep Version M1
The Xilinx XACTstep version M1 software appropriate block and net delay data that technology enables users at every design arises from the place and route process. level to increase optimization, manage design As a result of this strategy, different simu- changes, and quickly complete designs with lation libraries are needed to support simula- the entire spectrum of Xilinx FPGA and CPLD tion before and after NGDBuild has been devices. For example, the version M1 tools applied to a design. Prior to NGDBuild, de- are designed to support multiple device archi- signs will be expressed as netlists containing tectures using the same core physical imple- Unified Library components. After NGDBuild, mentation (i.e., map, place and route) soft- designs will be expressed as netlists consist- ware. To implement this capability, a new ing of SimPrims. ◆ program has been introduced into the design flow: NGDBuild. NGDBuild is responsible for two functions during the design implementation process. First, the design’s elements are brought to- gether into a single database so that subse- quent operations, such as map, place and route, may be applied to the entire design at once. Second, NGDBuild re-expresses the design as a netlist of “technology-less” 19 primitives that are common to all CPLDs and FPGAs. The components in this technology- independent library are known as “SimPrims.” NGDBuild’s impact on the design is to make it instantly “re-targetable” between any of the Xilinx device architectures supported by the core software. Thus, a design’s performance may be investigated in any Xilinx architecture, with little or no design rework required. The core implementation tools (map, place and route) receive a netlist from NGDBuild that expresses the design as a netlist of SimPrims, and it’s these technology- independent cells that are implemented within the target device. Consequently, the back-annotation process (that is the creation of a post-Map or post-PAR netlist describing the design’s physical implementation) results in a netlist of SimPrims annotated with the Programmable Logic in 5V Mixed Voltage Applications 3.3V The use of advanced, deep-submicron IC 5V components can directly interface with fabrication processes is resulting in rapidly 3.3V devices. Table 1 lists the Xilinx compo- increasing density and performance for pro- nent product families that can be employed grammable logic devices. However, as device in mixed-voltage systems. All Xilinx device geometries shrink below 0.5 microns, the inputs maintain their excellent protection smallest transistors cannot withstand 5 volts against electrostatic discharge (ESD), even without damage. Thus, the largest and fastest in mixed-voltage applications. new devices are based on lower supply volt- Mixing 5V and 3.3V Devices ages. For example, the new XC4000XL FPGA When mixing 3.3V and 5V devices on the family, featuring the industry’s highest-capac- same board, I/O signaling levels compatible ity, high-performance FPGAs, is based on the with both types of components are needed 3.3V standard. on all signals lines connecting the two types To reap the benefits of advanced process of components. Since both types of supply technology — including increased perfor- share a common ground, there are no prob- mance, increased density, lower power con- lems interfacing logic Low levels in either sumption, and lower price — many program- direction, but there are compatibility issues mable logic users are making the transition for the logic High levels. from the 5V standard to lower voltages. This 20 transition affects not only the supply voltage, 3.3V Devices Driving Inputs but also I/O signaling levels. Xilinx is actively on 5V Devices The lowest output High voltage (V ) of taking the lead in working with programmable OH the 3.3 device must exceed the V require- logic users to plan an orderly transi- IH ments of the 5V device. Minimum V for all tion to a lower voltage standard. OH ❝Xilinx Xilinx introduced the Zero+ prod- Xilinx 3.3V devices is 2.4V, well above the uct line, the industry’s first 3.3V 2.0V minimum High level for TTL signaling. introduced the FPGAs, in 1993. Since then, the (This includes the XC3000L, XC3100L, number of 3.3V product offerings XC5200L, and XC4000XL FPGA families and Zero+ product line, has increased dramatically. However, the XC7300 and XC9500 CPLD families when V = 3.3V.) Thus, all Xilinx 3.3V devices the industry’s first many other system components CCIO remain available in 5V versions only. can drive inputs to devices with TTL-compat- 3.3V FPGAs, in Thus, mixed-voltage systems em- ible input thresholds, including all 5V Xilinx ploying a mix of 5V and 3.3V com- devices. (Note: Some Xilinx 5V devices can 1993. Since then, ponents are likely to be the rule be programmed for TTL or CMOS input rather than the exception in the thresholds; these devices must be configured the number of 3.3V immediate future. for TTL-compatible inputs to be directly product offerings Xilinx products have been driven from a 3.3V device.) designed with this mixed-voltage 5V Devices Driving Inputs has increased environment in mind. 5V input on 3.3V Devices ❞ tolerance has been designed into The highest 5V device output voltage must dramatically. many Xilinx 3.3V devices; these not force excessive current into the input of devices accept 5V signals on all I/Os the 3.3V device. The input structures of Xilinx and can drive TTL levels into any 5V device, 3.3V FPGAs include input protection circuits. eliminating all interface issues. Many Xilinx These protection circuits in the XC3000L and Accepts 3.3V Table 1: Xilinx Device Compatible Family Inputs1 Drives 3.3V Devices Key Features products and XC3000A Yes With limiting resistor Low quiescent current supply voltage Single XC3100A Yes With limiting resistor High performance options Supply XC4000E/EX Yes Yes Highest density and performance
VCC = 5V XC5200 Yes With limiting resistor Cost-effective XC7300 Yes With limiting resistor 5 ns T , 100% utilization PD Note: (1) Inputs must be XC9500 Yes With limiting resistor 5V in-system-programmable, pin locking configured for TTL thresholds
Device Accepts 5V Drives 5V Family Compatible Inputs Devices Key Features Single XC3000L With limiting resistor Yes Very low powerdown & quiescent current Supply XC3100L With limiting resistor Yes High performance
VCC = 3.3V XC4000XL Yes Yes Highest density & performance XC5200L With limiting resistor Yes Cost-effective
Device Accepts 5V Drives 5V Family Compatible Inputs Devices Key Features Dual Supply XC5200L Yes Yes Cost-effective
VCC = 5V XC7300 Yes Yes Mixed-voltage system capable
VCCIO/VTT = 3.3V XC9500 Yes Yes Mixed-voltage system capable
XC3100L devices are designed for 3.3V inputs. 3.3V FPGAs can be directly driven by 5V de- However, the protection circuits in the vices with either TTL or CMOS outputs. Power XC4000XL and XC5000L devices are designed supply sequencing is not a problem; the in- to withstand 5V levels. puts can be driven to 5V either before or after 21
Most 5V devices have complementary the 3.3V VCC power is supplied without risking
CMOS outputs where VOH can reach the 5V damage to the devices. rail. (All Xilinx 5V FPGAs and CPLDs, except In mixed voltage systems, the XC7300 and the XC4000 series devices, have complemen- XC9500 CPLDs can be driven directly by 5V tary CMOS outputs.) When driving XC3000L inputs when set up for 3.3V I/O operation and XC3100L inputs (and most other 3.3V (i.e., VCCIO = 3.3V). The input protection di- devices) from such a 5V device, then the input odes in these CPLDs are always connected to current must be limited by a series resistor of the 5V VCC power line, allowing them to toler- no less than 150Ω. This guarantees an input ate 5V inputs without the need for current- current below 10mA, flowing through the ESD limiting resistors. input protection diode backwards into the Similarly, the XC5000L FPGAs can be used 3.3V supply. That amount of input current is in mixed-voltage systems by connecting the generally considered safe, causing neither VTT pin to 5V. The input protection circuits are metal migration nor latch-up problems. Care connected to the VTT line, allowing these 3.3V must be taken to avoid forcing the nominally FPGAs to tolerate 5V inputs without the need 3.3V supply voltage above its 3.6V maximum for current-limiting resistors. whenever a large number of active High in- If the 5V device has “totem-pole” n-chan- puts drive the 3.3V device, potentially causing nel-only outputs (as in the XC4000E/EX FPGA the 3.3V supply current to reverse direction. series), VOH is reduced by one threshold and
The 3.3V VCC power should be on before the series resistor can be eliminated, provided driving the device inputs from a 5V device. the nominally 5V supply does not exceed 5.25. The I/O structures of the XC4000XL FPGAs Thus, the XC4000E and XC4000EX FPGAs can have been designed to tolerate being driven directly drive any 3.3V device without the to a 5V rail by a low-impedance source. These need for current-limiting resistors. ◆ Integrating XC9500 ISP With Manufacturing In-system programming (ISP) allows the This series includes the following Genrad programming and reprogramming of logic testers: the GR2287L, GR2286i, GR2287i, devices already soldered on a system board. GR2283i, GR2284i, GR2281i, and GR2280i ISP capability provides many advantages, systems. The tester must be running version including facilitating design changes during 3.2 (or higher) of the Genrad software. (Deep prototyping, remote system upgrades, and vector memory is not required.) Creating the manufacturing flows. appropriate “test program” for a GR228X The XC9500 CPLD family supports the in- system requires the Xilinx EZTag software system programming of its FLASH configura- and a Xilinx-supplied vector translation tool tion memory using the (svf2dts), as described below. IEEE 1149.1 (JTAG) Using EZTag to generate an SVF file test access port (TAP), EZTag can generate a serial vector format and without requiring (SVF) file from the JEDEC programming file externally applied of the target design. The SVF file is in ASCII “supervoltages” (i.e., format and describes 1149.1 TAP operations; voltages greater than the file encodes the entire programming 5V). This allows the algorithm for the selected device in the sys- use of automatic test tem as a series of JTAG TAP instructions. equipment (ATE) that The XC9500 programming operation in- supports the JTAG cludes a built-in verification step. However, TAP to program in developing a new ATE ISP flow, a separate 22 XC9500 family readback/verify step may be used as an ATE devices. Thus, CPLD device programming ISP process verification step. can be integrated with board testing in a EZTag can generate an SVF file for single manufacturing step. erasure, programming, or readback verifica- The Genrad GR228X series of board test tion, using the following steps: systems are examples of such ATE platforms.
CORE information and design files for registered For now, even WebLINX visitors without LogiCORE product owners; all users with a a valid maintenance agreement can access Generator valid maintenance agreement can log onto the a demonstration version of the PCI CORE Continued from page 14 new LogiCORE lounges and register for access Generator, allowing the evaluation of the to the CORE Generator. The CORE Generator GUI and an examination of the various Figure 2: Proven tool is password protected so that only options available for the PCI interface core. LogiCORE PCI core LogiCORE PCI owners have access to the core. In the future, all visitors will be allowed to cut development time create functional simulation models for LogiCORE PCI designs, allowing users to create and download the model, instantiate it into a custom design, and perform complete system functional verification, all prior to purchasing the core. Further information, including the dem- onstration version of the CORE Generator, can be found at www.xilinx.com/products/ logicore/logicore.htm. ◆ Test on the GR228X 1. Create the XC9500 design using XABEL-CPLD Generating a Genrad or any compatible third-party design entry tool. GR228X ISP Program 2. Fit the design and save it as a JEDEC output file. The svf2dts program translates SVF files to 3. Invoke the EZTag software from the XACT GR228X stimulus files. The svf2dts software and command line using the following command: accompanying documentation is available via eztag -svf WebLINX (www.xilinx.com), and the associated The following message appears: Xilinx ftp site. The svf2dts translation tool is Xilinx (R) EZTAG XC9500-CPLD-6.0.5 - JTAG Boundary-Scan Download supported on DOS, Windows 95, DOS window Copyright (C) Xilinx Inc. 1991- 1996. All Rights Reserved. on SCO UNIX, and Windows NT platforms. —————————————————————————— The svf2dts program is run on the com- SVF GENERATION MODE. EZTAG? puter that is the controller for the GR228X 4. At this prompt, type the following command: tester. On the tester’s controller, make a di- part deviceType1:designName1 … rectory called “svf” and copy all the SVF files deviceTypeN:designNameN into this directory. The svf2dts program per- where designName is the name of the design forms the SVF to DTS conversion, where DTS to translate into SVF, and deviceTypeN is the type of device in the nth position in the JTAG (digital test source) is the GR228X stimulus device chain (beginning with the first device to description language. The DTS file is parti- receive TDI and ending with the last device to tioned into “bursts” of 15K vectors. Invoke output TDO). For any non-XC9500 part in the the “svf2dts” program with the name of SVF JTAG chain, the BSDL file for the specified part must be available along the XACT path and is program file as follows: called deviceType.bsd (e.g., 4003pc84.bsd for a svf2dts
◆◆◆ ◆◆◆ ◆◆◆ ◆◆ ◆ ◆ ◆◆◆ ◆◆◆ ◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆ ◆◆ TYPE ◆◆ ◆◆ ◆ ◆◆ ◆◆ ◆ ◆◆ ◆◆ ◆◆◆ ◆◆ ◆◆ ◆◆◆◆◆ ◆◆◆ ◆◆ ◆◆ BG560 PG559 PG475 BG432 PG411 BG352 PG299 HQ240 PQ240 CB228 PG223 HQ208 PQ208 CB196 PG191 PG175 PP175 CB164 PQ160 PG156 PG144 PG132 PP132 PG120 CB100 VQ100 PQ100 PG84 WC84 PC84 WC68 PC68 VQ64 WC44 VQ44 PQ44 Q176 Q144 Q100
◆◆◆◆ ◆◆ CODE
◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆XC3020A XC3030A
XC3042A COMPONENT AVAILABILITY CHART XC3064A XC3090A XC3020L XC3030L XC3042L XC3064L XC3090L XC3142L XC3190L ◆◆ XC3120A XC3130A XC3142A XC3164A XC3190A ◆ XC3195A ◆◆◆ ◆◆ ◆ ◆ ◆◆ ◆◆◆◆◆ XC4003E ◆◆ ◆◆◆◆ ◆◆◆◆◆ ◆◆◆◆ ◆◆◆◆◆ ◆◆ ◆◆ XC4005E XC4006E
◆◆ XC4008E XC4010E ◆ ◆◆ ◆◆ ◆ ◆◆◆ ◆ XC4013E ◆◆ ◆◆◆◆◆ ◆ ◆◆◆◆◆ ◆◆◆◆◆ ◆◆◆ XC4020E XC4025E
◆◆ ◆◆ ◆◆◆ ◆◆ XC4028EX XC4036EX ◆◆◆◆ ◆◆ XC4005XL ◆◆◆◆ ◆◆◆ ◆ ◆ XC4010XL XC4013XL
◆◆◆ XC4020XL XC4028XL XC4036XL XC4044XL XC4052XL ◆◆ ◆ ◆ 299 256 240 228 225 223 208 196 191 176 175 164 160 156 144 132 120 100 560 559 475 432 411 352 304 84 68 64 44 PINS LSI G BG560 BGA PLASTIC PGA CERAMIC BG432 PGA CERAMIC BGA PLASTIC PGA CERAMIC PLASTIC BGA HI-PERF. QFP BG256 PGA CERAMIC BGA PLASTIC HI-PERF QFP PQFP PLASTIC BG225 TOP BRZ.CQFP BGA PLASTIC PGA CERAMIC HI-PERF QFP PQFP PLASTIC TOP BRZ.CQFP T PGA CERAMIC TQFP PLASTIC PGA CERAMIC PGA PLASTIC TOP BRZ.CQFP PQFP PLASTIC PGA CERAMIC T PGA CERAMIC TQFP PLASTIC PGA CERAMIC PGA PLASTIC PGA CERAMIC VQ100 TOP BRZ.CQFP T VQFP PLASTIC TQFP PLASTIC PG84 PQFP PLASTIC CERAMIC PGA LCC CERAMIC LCCPLASTIC LCC CERAMIC LCCPLASTIC VQFP PLASTIC VQ44 LCC CERAMIC PQ44 VQFP PLASTIC QFP PLASTIC LCCPLASTIC
TYPE ◆ ◆ ◆ ◆ ◆◆◆ ❖ ❖ PG559 PG475 PG411 BG352 HQ304 PG299 HQ240 PQ240 CB228 PG223 HQ208 PQ208 CB196 PG191 PG175 PP175 CB164 PQ160 PG156 PG144 PG132 PP132 PG120 CB100 PQ100 WC84 PC84 WC68 PC68 VQ64 WC44 PC44
Q176 Q144 Q100 CODE ◆ ◆◆ ◆◆◆ ◆◆ ◆◆ ◆ ◆◆◆◆ ◆◆ XC4062XL ◆◆◆ XC4085XL ◆ ◆◆ ◆◆◆ ◆◆ ◆ XC4005L
◆ ◆◆◆ ◆◆ ◆◆ ◆ ◆◆◆◆ ◆◆◆ ◆◆◆ XC4010L MAY 1997
◆◆◆ ◆◆ ◆◆ ◆ ◆◆◆◆ XC4013L XC5202 XC5204 ◆ XC5206
◆ ◆◆ ◆◆ ◆◆◆ XC5210 XC5215 XC6216 ❖ ❖ ❖ XC6264 ◆◆◆ ◆ ◆ ◆◆◆◆ ◆ XC7236A ◆◆◆◆◆◆ ◆ ◆◆◆ XC7272A
◆◆◆ XC7318 XC7336 ◆◆ XC7336Q XC7354 XC7372 XC73108 XC73144 ◆ XC9536 XC9572 XC95108 ❖ ◆◆ XC95216 XC95288 ◆◆ ❖ ◆ =Newsincelastissue = currently Product = of shipping orplanned XCell 25 PROGRAMMER SUPPORT FOR XILINX XC7200/XC7300 CPLDS — MAY 1997 MANUFACTURER MODEL 7236A 7272A 7318 7336 7336Q 7354 7372 73108 73144 ADVANTECH PC-UPROG NS NS LABTOOL-48 DISQUALIFIED ADVIN SYSTEMS PILOT-U40 10.84B 10.86B 10.86B 10.84B 10.84B PILOT-U84 10.84B 10.84B 10.86B 10.86B 10.84B 10.84B 10.84B 10.84B 10.84B AMERICAN RELIANCE, INC. SPECTRUM-48 DISQUALIFIED B&C MICROSYSTEMS, INC. Proteus Jun-97 Jun-97 Jun-97 Jun-97 Jun-97 Jun-97 Jun-97 Jun-97 Jun-97 BP MICROSYSTEMS BP-1200 V3.15 V3.15 V3.15 V3.18 V3.15 V3.15 V3.15 V3.15 BP-1400 V3.15 V3.15 V3.15 V3.18 V3.15 V3.15 V3.15 V3.15 BP-2100 V3.15 V3.15 V3.15 V3.18 V3.15 V3.15 V3.15 V3.15 BP-2200 V3.15 V3.15 V3.15 V3.18 V3.15 V3.15 V3.15 V3.15 BYTEK CHIPBURNER-40 1.0a 1.0a 1.0a 1.0a 1.0a 1.0a 1.0a DATAMAN DATAMAN-48 V1.30 V1.30 V1.30 V1.30 V1.30 V1.30 V1.30 V1.30 DATA I/O 2900 V5.3 V5.3 V5.3 V5.3 3900/AutoSite V5.3 V5.3 V5.3 V5.3 V5.3 V5.3 UniSite V5.3 V5.3 V5.3 V5.3 V5.3 V5.3 DEUS EX MACHINA ENGINEERING XPGM V1.60 V1.60 V1.60 V1.60 V1.60 V1.60 V1.60 V1.60 V1.60 ELECTRONIC ENGINEERING TOOLS ALLMAX/ALLMAX+ V2.4U V2.4U V2.5i V2.5i V2.4U V2.4U V2.4U V2.4U MEGAMAX V1.1E V1.1E V2.1x V2.1x V1.1E V1.1E V1.1E V1.1E ELAN 6000 APS DISQUALIFIED HI-LO SYSTEMS RESEARCH All-03A V3.09 V3.09 V3.09 V3.09 V3.09 V3.09 V3.09 V3.09 All-07 V3.09 V3.09 V3.09 V3.09 V3.09 V3.09 V3.09 V3.09 ICE TECHNOLOGY LTD Micromaster 1000/E V1.1 V1.1 V1.1 V1.1 V1.1 V1.1 V3.1 V1.1 V1.1 Speedmaster 1000/E V1.1 V1.1 V1.1 V1.1 V1.1 V1.1 V3.1 V1.1 V1.1 Micromaster LV V1.1 V1.1 V1.1 V1.1 V1.1 V1.1 V3.1 V1.1 V1.1 Speedmaster LV V1.1 V1.1 V1.1 V1.1 V1.1 V1.1 V3.1 V1.1 V1.1 LEAP ELECTRONIC CO., LTD. LEAPER-10 V3.2 V3.2 V3.2 V3.2 V3.2 V3.2 V3.2 V3.2 LP U4 V2.1 V2.1 V3.0 V3.0 V2.1 V2.1 V2.1 V2.1 LOGICAL DEVICES ALLPRO-88 V2.9Rev1 V2.9Rev1 V2.9Rev1 V2.9Rev1 V2.9Rev1 V2.9Rev1 ALLPRO-88XR V2.9Rev1 V2.9Rev1 V2.9Rev1 V2.9Rev1 V2.9Rev1 V2.9Rev1 ALLPRO-96 6.4.26 6.4.26 6.4.26 6.4.26 6.4.26 6.4.26 6.4.26 6.4.26 Chipmaster 2000 V2.4U V2.4U V2.4U V2.4U V2.4U V2.4U V2.4U V2.4U Chipmaster 6000 V1.31A V1.31A V1.31A V1.31A V1.31A V1.31A V1.31A V1.31A XPRO-1 DISQUALIFIED MICROPROSS ROM9000 V3.85 Jun-97 MQP ELECTRONICS SYSTEM 2000 PIN-MASTER 48 V1.25 V1.25 V1.25 V1.25 V1.25 V1.25 V1.25 V1.25 V1.25 NEEDHAM’S ELECTRONICS EMP20 V3.10 V3.10 V3.39 V3.39 V3.10 V3.10 V3.10 V3.10 SMS EXPERT DISQUALIFIED OPTIMA DISQUALIFIED STAG ECLIPSE 6.4.26 6.4.26 6.12.11 6.12.11 6.4.26 6.4.26 6.4.26 6.4.26 6.8.9 SUNRISE T-10 UDP DISQUALIFIED T-10 ULC DISQUALIFIED SUNSHINE POWER-100 V8.40 V8.40 V8.40 V8.40 V8.40 V8.40 V8.40 EXPRO-60/80 V8.40 V8.40 V8.40 V8.40 V8.40 V8.40 V8.40 26 SYSTEM GENERAL TURPRO-1/FX V2.30 V2.30 V2.31 V2.31 V2.30 V2.30 V2.30 V2.30 V2.30 MULTI-APRO V3.02 V3.02 V3.02 V3.02 V3.02 V3.02 V3.02 V3.02 V3.02 TRIBAL MICROSYSTEMS Flex-700 V3.09 V3.09 V3.09 V3.09 V3.09 V3.09 V3.09 V3.09 TUP-300 V3.09 V3.09 V3.09 V3.09 V3.09 V3.09 V3.09 TUP-400 V3.09 V3.09 V3.09 V3.09 V3.09 V3.09 V3.09 XELTEK SUPERPRO SUPERPRO II 2.4B 2.4B 2.5B 2.5B 2.5B 2.4B 2.4B 2.4B 2.4B SUPERPRO II/P 2.4B 2.4B 2.5B 2.5B 2.5B 2.4B 2.4B 2.4B 2.4B XILINX HW-130 V2.04 V2.04 V4.00 V4.00 V4.00 V4.00 V4.00 V4.00 V4.00
PROGRAMMER SUPPORT FOR XC9500 CPLDS — MAY 1997 MANUFACTURER MODEL 9536 9536F 9572 9572F 95108 95108F 95216 ADVANTECH LABTOOL-48 May-97 May-97 Jun-97 Jun-97 May-97 May-97 BP MICROSYSTEMS BP-1200 V3.21 V3.21 V3.24 V3.24 V3.21 V3.21 BP-1400 V3.21 V3.21 V3.24 V3.24 V3.21 V3.21 BP-2100 V3.21 V3.21 V3.24 V3.24 V3.21 V3.21 BP-2200 V3.21 V3.21 V3.24 V3.24 V3.21 V3.21 DATA I/O 2900 V5.4 V5.4 3900/AutoSite V5.4 V5.4 V5.4 V5.4 V5.4 V5.4 UniSite V5.4 V5.4 V5.4 V5.4 V5.4 V5.4 HI-LO SYSTEMS RESEARCH All-07 V3.02 V3.02 V3.02 V3.02 V3.02 V3.02 LOGICAL DEVICES ALLPRO-88 May-97 May-97 Jun-97 Jun-97 May-97 May-97 ALLPRO-96 V7.3.27 V7.3.27 Jun-97 Jun-97 V7.3.27 V7.3.27 SMS EXPERT May-97 May-97 Jun-97 Jun-97 May-97 May-97 OPTIMA May-97 May-97 Jun-97 Jun-97 May-97 May-97 STAG ECLIPSE V7.1.30 V7.1.30 Jun-97 Jun-97 V7.1.30 V7.1.30 SYSTEM GENERAL MULTI-APRO May-97 May-97 Jun-97 Jun-97 May-97 May-97 TRIBAL MICROSYSTEMS Flex-700 V3.02 V3.02 V3.02 V3.02 V3.02 V3.02 XILINX HW-130* V4.00 V4.00 V4.10 V4.10 V4.00 V4.00 V4.10 Changes since last issue are noted in color. * NOTE: Reflects the version of the Host Software. DISQUALIFIED DISQUALIFIED DISQUALIFIED DISQUALIFIED 1997 Changes since last issue printed in color 2.4B2.4B 2.4B 2.4B V2.0 V2.0 V2.7 V2.7 V1.94V3.84V3.10 V1.94 V3.84 V3.10 V3.19 V3.19 V3.19 V3.19 V1.25 V1.25 V1.25 V1.25 V1.24 V1.31A V1.31A AY XC1718D XC1736D XC1718L XC17128D XC17128L SPROM.310 SPROM.310 - M ROMS ROM 3000 U CLK-3100ALLPRO-88 ALLPRO-88XRALLPRO-96 V5.61CHIPMASTER 2000CHIPMASTER 6000 V2.7 V2.4U 6.5.10 6.5.10 V5.61 6.5.10 V2.4U V2.7 6.5.10 IQ-180 IQ-280Uniwriter 40 DISQUALIFIED TUP-400 V3.19 V3.19 V3.19 V3.19 LP U4LP V2.0XPRO-1 ROM9000 V2.0 SYSTEM 2000PIN-MASTER 48 2.25 2.25Chipmaster 5000 2.25 Sprint Plus48Quasar DISQUALIFIED T-10 ULCEXPRO-60/80 DISQUALIFIED TURPRO-1 F/XTURPRO-1 T/X V8.40 APRO V2.26HMULTI-APRO V2.26H DISQUALIFIED FLEX-700 V1.16 V2.26HSuperPRO V8.40 V2.26H SuperPRO II V1.16SuperPRO II/P V3.19 V1.16HW-130* V3.19 V1.16 V3.19 V2.03 V3.19 V2.03 V2.03 V2.03 OptimaMultisyte DISQUALIFIED DISQUALIFIED P ERIAL *NOTE: Reflects the version of host software MANUFACTURERLEAP ELECTRONICSLINK COMPUTER GRAPHICS MODELLOGICAL DEVICES LEAPER-10 ALLPRO-40 XC1765D XC1765L XC17256DMICRO PROSS XC17256L ROM 5000 B NEEDHAM’S ELECTRONICS EMP20 RED SQUARE MQP ELECTRONICS200 MODEL 6.46SMS 6.46STAG 6.46 SUNRISESUNSHINE ExpertSYSTEM GENERAL Eclipse T-10 UDP TURPRO-1 POWER-100TRIBAL MICROSYSTEMS TUP-300 6.5.10XELTEK V2.26H V8.40 6.5.10 V2.26HXILINX V2.26H 6.5.10 V2.26H 6.5.10 V8.40 HW-112* New algorithms in progress XC1700 S ILINX X
OR 27 F DISQUALIFIED UPPORT S V5.4V5.4V5.4 V5.4V5.4 V5.4V5.4 V5.4 V5.4 V5.4 V5.4 V5.4 V5.4 V5.4 BBS V5.4 BBS BBS BBS BBS V5.4 V5.4 V5.4 BBS 3.7Q 3.7Q V3.19 V3.19 V3.19 V3.19 V1.1E V1.1E V1.1E V3.17V3.17V3.17 V3.17V3.17 V3.17 V3.17 V3.17 V3.17 V3.17 V3.17 V3.17 V3.17 V3.17 V3.17 V3.17 V3.17 V3.17 V3.17 V3.17 V2.4U V2.4U V2.4U XC1718D XC1736D XC1718L XC17128D XC17128L ROGRAMMER 2900 3900 AutoSite ChipLab SPECTRUM-48 CP-1128 EP-1140 BP-1200BP-1400BP-2100 V3.15 V3.15 V3.15 V3.15 V3.15 V3.15 V3.15 V3.15 V3.15 XPGM5000-145 V1.60 V1.60 V1.60 V1.60 Micromaster LV LV40 Portable LABTOOL-48PILOT-U28PILOT-U32PILOT-U40PILOT-U84PILOT-142 10.84BPILOT-143 10.84BPILOT-144 10.84B DISQUALIFIED PILOT-145 10.84B 10.84B 10.84B 10.84B 10.84B 10.84B 10.84B 10.84B 10.84B 10.84B BP-2200 10.84B 10.84B 10.84B MTK-1000MTK-2000MTK-4000 V3.15FIREMAN-8MFIREMAN-8XCHIPBURNER-40 8E V3.15 8E 8E 8E 1.0a V3.15 8E 8E 8E 1.0a 8E 8E 8E2700 8E 1.0a 8E 8E 8EALLMAX/ALLMAX+ 8E 8E 1.0a 8E 8E 8E 6000 APS 8E All-07Micromaster 1000/E Speedmaster 1000/E Speedmaster LV V3.19 V3.19 V3.19 V3.19 P HI-LO SYSTEMS RESEARCH All-03A BP MICROSYSTEMS ELECTRONIC ELAN DIGITAL SYSTEMS 3000-145 MANUFACTURERADVANTECH MODEL PC-UPROG XC1765D XC1765L XC17256D XC17256L AMERICAN RELIANCE, iNC. B&C MICROSYSTEMS INC. PROTEUS-UP40 DATAMANDATA I/O DATAMAN-48DEUS EX MACHINA UniSite ENGINEERING TOOLS V1.30 MEGAMAX V1.30 ADVIN PILOT-U24 10.84BBYTEK 10.84B 135H-FT/U 8E 8E 8EICE TECHNOLOGY LTD 8E 28
XILINX ALLIANCE-EDA COMPANIES & PRODUCTS - MAY 1997 - 1 OF 2
3K/ XC CPLDNI U PLATFORMS COMPANY NAME PRODUCT NAME VERSION FUNCTION 4K 5200K 79K LIB PCUN S RS6000 HP7 Aldec Active-CAD 2.2 Schematic Entry, State Machine & HDL ✓✓✓✓ ✓ Editor, FPGA Synthesis & Simulation Cadence Verilog 97A Simulation ✓✓7k ✓ ✓✓✓ Concept 97A Schematic Entry ✓ 7k ✓ ✓✓✓ FPGA Designer 97A Topdown FPGA Synthesis ✓✓7k ✓ ✓✓✓ Synergy 97A FPGA Synthesis ✓✓7k ✓ ✓✓✓ Composer 97A Schematic Entry ✓ 7k ✓ ✓✓✓ Mentor Graphics Design Architect B.x Schematic Entry ✓✓7k ✓ ✓✓✓ Galileo 3.2.5 Synthesis/Timing Analysis ✓✓✓✓ ✓✓✓ Leonardo 4.0.3 Synthesis/Timing Analysis ✓✓✓✓ ✓✓✓ QuickSim II B.x Simulation ✓✓7k ✓ ✓✓✓ QuickHDL B.x Simulation ✓✓7k ✓ ✓✓✓ Synario Design Automation ABEL 6.3 Synthesis, Simulation ✓✓ ✓ DIAMOND Synario 2.3 Schematic Entry, Synthesis & Simulation ✓✓✓✓ ✓ Synopsys FPGA Express 1.1 Synthesis ✓✓9k ✓ FPGA Compiler 97.01 Synthesis ✓✓✓✓ ✓✓✓ Design Compiler 97.01 Synthesis ✓✓✓✓ ✓✓✓ VSS 97.01 Simulation ✓✓✓✓ ✓✓✓ Viewlogic WorkView Office 7.1.2/7.2 Schem/Sim/Synth ✓✓✓✓ ✓ PowerView 6.0 Schem/Sim/Synth/Timing Analysis ✓✓✓✓ ✓✓✓ Capilano Computing Design Works 3.1 Schematic Entry/Sim ✓✓✓ Compass Design ASIC Navigator Schematic Entry ✓✓7k ✓✓ Automation X-Syn Synthesis ✓✓✓ QSim Simulation ✓✓7k ✓✓ Escalade DesignBook 2.0 Design Entry ✓✓✓✓ Exemplar Logic Galileo 3.2.5 Synthesis/Timing Analysis Simulation ✓✓✓✓ ✓✓ ✓ Leonardo 4.0.3 Synthesis/Timing Analysis ✓✓✓✓ ✓✓✓ IK Technology Co. ISHIZUE PROFESSIONALS 1.06 Schematic Entry/Simulation ✓ 4Q ✓✓ ✓ IKOS Systems Voyager 2.31 Simulation ✓✓ ✓ ✓ Gemini 1.21 Simulation ✓✓ ✓ ✓ INCASES Engineering GmbH Theda 5.0 Design Entry ✓ ✓✓✓✓ ISDATA LOG/iC2 5.0 Synthesis Simulation ✓✓7k ✓✓✓ ✓ Logic Modeling Corp. Smart Model Simulation Models ✓✓7k,9k ✓✓✓✓ (Synopsis Division) LM1200 Hardware Modeler ✓ 7k,9k ✓✓✓
Model Technology V-System/VHDL 4.4j (PC) / Simulation ✓ ✓ ✓✓✓✓ 4.6a (WS) OrCAD Capture (Win) 7.0 Schematic Entry ✓✓✓✓ ✓ RUBY Simulate (Win) 6.10 Simulation ✓✓✓✓ ✓ VST 386+ (DOS) 1.2 Simulation ✓✓✓ SDT 386+ (DOS) 1.2 Schematic Entry ✓✓✓ PLD 386+ (DOS) 2.0 Synthesis ✓✓✓ Protel Technology Advanced Schematic 3.2 Schematic Entry ✓✓7k ✓✓ Advanced PLD 3 PLD/FPGA Design & Simulation ✓✓7k ✓ Quad Design Technology Motive 4.3 Timing Analysis ✓ ✓✓✓✓ SimuCad Silos III 96.1 Schematic Entry & Simulation ✓✓ ✓ ✓ Sophia Sys & Tech Vanguard 5.31 Schematic Entry ✓✓ ✓✓✓ Summit Design Corp. Visual HDL 3.0 Graphical Design Entry/ ✓✓✓✓ ✓✓✓✓ Simulation/Debug Synplicity, Inc. Synplify-Lite 2.6c Synthesis ✓✓9k ✓✓✓ ✓ Synplify 2.6c Synthesis ✓✓9k ✓✓✓ ✓ TopDown Design Solutions V-BAK 1.1 XNF to VHDL translator ✓✓ ✓ ✓✓✓ RS6000 HP7 UN ✓✓✓ PLATFORMS ✓✓ ✓ ✓✓ ✓ ✓ ✓ ✓✓ ✓ ✓ ✓ ✓ ✓ ✓✓ ✓✓✓✓✓✓ ✓ ✓✓ ✓ ✓✓ ✓ ✓ ✓ ✓ PC S NI IB ✓✓✓ ✓ ✓✓✓ ✓ ✓✓✓ ✓ ✓✓✓ ✓ ✓✓✓ ✓ ✓ L 2 K 9 ✓✓ K 7k 7k 7k 7k 7k 7k 7k 7k 7k 7k 7k 7k OF Proven Xilinx compatibility 7k,9k 7k,9k These partners have a high degree of compatibility ✓✓✓✓✓ ✓✓✓✓✓ ✓✓✓✓✓ ✓ ✓✓✓✓✓ ✓✓ 5200 7 Ruby: and have repeatedly shown themselves to be significant contributors to our users’ development solutions. Emerald: / XC CPLD U K K ✓ ✓ ✓✓ ✓✓ ✓ ✓✓✓ ✓✓✓✓ ✓ ✓✓✓✓ ✓ ✓✓✓✓ ✓✓ ✓ ✓✓✓✓ ✓ ✓ ✓✓✓✓ ✓✓ ✓✓ ✓✓✓✓ ✓✓✓✓ ✓ ✓✓✓✓✓✓ ✓✓✓ ✓ ✓ ✓ ✓✓✓ ✓✓✓✓ ✓✓✓✓✓ ✓ ✓✓✓ ✓✓✓✓ ✓✓ ✓✓✓ ✓✓✓✓ ✓✓ ✓✓ ✓✓ ✓✓ ✓✓✓✓ ✓ ✓✓✓ 4 3 3k,4k 3k,4k 3k,4k 3k,4k 3k,4k 1997 - 2 software step AY - M RODUCTS These partners have strong strategic relation- UNCTION Multi-FPGA Partitioning Simulation Synthesis Synthesis F & P for these products. Diamond: ships with Xilinx and have a direct impact on our re- leases. Typically, Xilinx is directly involved in the devel- opment and testing of the interface to XACT 3.2 3.20 1.3.3 ERSION V
OMPANIES 29 -EDA C AME N LLIANCE RODUCT PLDSyn 12.0 Design Entry Synthesis Synovation 12.2 Synthesis DMMVeriBest Synthesis 14.0 14.x Synthesis Design Management 3k,4k VeriBest Simulator 14.0 Simulation Veribest Verilog 14.0 Simulation Softwire 3.3 Multi-FPGA Partitioning FS-ATGCKTSIM 3.0 3.0 Test Vector Generation Logic Analysis ATGENAAF-SIMPROGBSDL 2.60 2.63 2.60 Automatic Test Generation BSDL Customization Fault Simulation P VulcanVerBest Design CapturePeak FPGA 4.5Gatran 14.x Simulation TESTBSDLCapture Design ASIC ExplorerQuickBench 3.3 3k,4k 2.63 ASIC to FPGA Netlist Mapping 2.3FS-SIM Boundary Scan ATG Emulation ASIC 1.0Ulysa Visual Test Bench Generator 3.0 4K Paradigm XP Simulation 1.0 VHDL Synthesis Gate-level Sim A ILINX X NC I UTOMATION AME A N ESIGN D
OMPANY EDA
Chronology Corporation TimingDesigner 3.0 Timing Specification and Analysis CINA-Computer SmartViewer 1.0e Schematic Generation ACEO Technology, Inc. Asyn 4.1 C V ALPS LSI TechnologiesAptix CorporationAster Ingenierie S.A.Auspy Development Co.SystemsDesign Edway Integrated Network Analysis System ExplorerEpsilon Design Systems APS XILLASFlynn SystemsFujitsu LSI Logic CompressorHarmonix CorporationDevicesLogical 3.1 Synthesis/Simlulation MicroSimMINC ProbeTeradyne PARTHENONTokyo Electron Limited System Emulation 4.2Trans EDA LimitedSolutionsSoftware Visual PROVERDZuken Total DesignerZycad LASAR model generation ViewCADoptimization Synthesis Statecad MicroSim Design Lab TransPRO 2.3 Lasar PLDesigner-XL/PL-Synthesizer 3.0 4.7 3.3/3.2.2 SynthesisAnalysis Testability Tsutsuji Synthesis Paradigm RP 1.2 Simulation & Synthesis 3.0 Top-Down Design System 1.2Simulation Schematic, FLDL to XNF translator 6 Grph. Design Entry, Sim., Debug Synthesis 3k,4k 4k Simulation 7k Rapid Prototyping Synthesis/Simulation 3k,4k VeribestAccolade Design Automation Peak VHDL Veribest VHDLAcugen Software, Inc. Sharpeye 14.0 Schematic Entry 2.60Analysis Testability
RUBY EMERALD Items that have changed since the last issue (XCell 24) are in color. XILINX ALLIANCE-EDA CONTACTS - MAY 1997
COMPANY NAME CONTACT NAME PHONE NUMBER E-MAIL ADDRESS COMPANY NAME CONTACT NAME PHONE NUMBER E-MAIL ADDRESS Accolade Design Automation Dave Pellerin (800) 470-2686 [email protected] Logical Devices Chip Willman (303) 279-6868 [email protected] ACEO Technology, Inc. Philip George (510) 656-2189 [email protected] Memec Design Services Maria Agular (602) 491-4311 [email protected] Acugen Software, Inc. Nancy Hudson (603) 881-8821 Mentor Graphics Sam Picken (503) 685-1298 [email protected] Aldec David Rinehart (702) 456-1222x12 [email protected] MINC Kevin Bush (719) 590-1155 ALPS LSI Technologies David Blagden 441489571562 Minelec Marketing Dept. +32-02-4603175 Alta Group Paul Ekas (408) 523-4135 [email protected] Model Technology Greg Seltzer (503) 526-5465 [email protected] Aptix Corporation Michel Courtney (408) 428-6226 [email protected] OrCAD Mike Jingozian (503) 671-9500 mikej@orcad.com Aster Ingenierie S.A. Christopher Lotz +33-99537171 Protel Technology Luise Markham (408) 243-8143 Cadence Ann Heilmann (408) 944-7016 [email protected] Quad Design Technology Britta Sullivan (805) 988-8250 Capilano Computing Chris Dewhurst (604) 522-6200 [email protected] SimuCad Richard Jones (510) 487-9700 [email protected] Chronology Corporation MikeMcClure (206) 869-4227x116 [email protected] Sophia Sys & Tech Tom Tilbon (408) 232-4764 CINA-Computer Integrated Brad Ashmore (415) 940-1723 [email protected] Summit Design Corporation Ed Sinclair (503) 643-9281 Network Analysis Synario Design Automation Jacquelin Taylor (206) 867-6257 [email protected] Compass Design Automation Marcia Murray (408) 474-5002 [email protected] Synopsys Lynn Fiance (415) 694-4289 [email protected] Epsilon Design Systems Cuong Do (408) 934-1536 [email protected] Synplicity, Inc. Marie McAllister (415) 961-4962 [email protected] Escalade Rod Dudzinski (408) 654-1651 Teradyne Mike Jew (617) 422-3753 [email protected] Exemplar Logic Tom Hill (503) 685-7750 [email protected] Tokyo Electron Limited Shige Ohtani +81-3-334-08198 [email protected] Flynn Systems Matt Van Wagner (603) 598-4444 [email protected] TopDown Design Solutions Art Pisani (603) 888-8811 Fujitsu LSI Masato Tsuru +81-4-4812-8043 Trans EDA Limited James Douglas +44-703-255118 Harmonix Corporation Shigeaki Hakusui (617) 935-8335 VEDA Design Automation Kathie O’Toole (408) 496-4515 IK Technology Co. Tsutomu Someya +81-3-3839-0606 [email protected] Veribest Mike O’Donohue (303) 581-2330 [email protected] IKOS Systems Brad Roberts (408) 366-8509 [email protected] Viewlogic Philip Lewer (508) 480-0881 [email protected] INCASES Engineering Christian Kerscher +49-89-839910 ckerscher@ Visual Software Solutions Riky Escoto (800) 208-1051 [email protected] GmbH muc.incases.com Zuken Makato Ikeda +81-4-594-27787 ISDATA Ralph Remme +49-72-1751087 [email protected] Zycad Charlene Locke (510) 623-4451 [email protected] Logic Modeling Corp. Marnie McCollow (503) 531-2412 marniem@ (Synopsis Division) synopsys.com Changes since last issue (XCell 24) printed in color. Inquiries about the Xilinx Alliance Program can be e-mailed to [email protected]
XILINX ALLIANCECORE PARTNERS - MAY 1997 Additional information is available on WebLINX, starting at: http://www.xilinx.com/products/logicore/alliance/tblpart.htm PARTNER NAME PHONE EMAIL/WEB URL EXPERTISE ARM Semiconductor (USA), Inc. Tel: 408-733-3344 [email protected] Microprocessors, microcontrollers, 1095 E. Duane Ave., Suite 211 Sunnyvale, CA 94086 (USA) Fax: 408-733-9922 peripherals, communications Comit Systems Tel: 408-988-2988 [email protected] Base functions, communications 1250 Oakmead Pkwy, Suite 210 Sunnyvale, CA 94088 (USA) Fax: 408-988-2133 www.comit.com 30 CoreEL Microsystems Tel: 510-770-2277 [email protected] ATM, communications 46750 Fremont Blvd #208 Fremont, CA 94538 (USA) Fax: 510-770-2288 www.coreel.com Digital Objects Tel: 510-795-2212 [email protected] PCMCIA, CardBus 3550 Mowry Ave., Suite 101 Fremont, CA 94538 (USA) Fax: 510-795-2219 www.digitalobjects.com Eureka Technology Tel: 415-960-3800 [email protected] PCI, PowerPC peripherals 4962 El Camino Real, #108 Los Altos, CA 94022 (USA) Fax: 415-960-3805 Integrated Silicon Systems, Ltd. Tel: +44-1232-664664 [email protected] DSP functions 29 Chlorine Gardens Belfast, BT9 5DL (North. Ireland) Fax: +44-1232-669664 www.iss-dsp.com Inventra/Mentor Tel: 503-685-8000 [email protected] USB, PCI, DSP, telecom, 1001 Ridder Park Drive, San Jose, CA 95131-2314 (USA) Fax: 408-451-5690 www.mentorg.com/inventra microprocessor peripherals Logic Innovations Tel: 619-455-7200 [email protected] PCI, MPEG-2, ATM, 6205 Lusk Boulevard San Diego, CA 92121 (USA) Fax: 619-455-7273 www.logici.com communications Memec Design Services Tel: 602-491-4311 [email protected] Microprocessor peripherals, base 1819 S. Dobson Rd., Suite 203, Mesa, AZ 85202 (USA) Fax: 602-491-4907 www.memecdesign.com functions, Xilinx design services NMI Electronics, Ltd., Fountain House, Great Cornbow, Tel: +44 121 585 5979 [email protected] Design services and base-level Halesowen, West Midlands, B63 3BL (UK) Fax: +44 121 585 5764 www.nmi.co.uk functions for the XC9500 Phoenix Technologies/Virtual Chips Tel: 408-570-1000 [email protected] PCI, USB, CardBus, ATM 411 E. Plumeria Drive, San Jose, CA 95134 (USA) Fax: 408-452-0952 www.phoenix.com Rice Electronics Tel: 314-838-2942 [email protected] DSP PO Box 741 Florissant, MO 63032 (USA) Fax: 314-838-2942 SAND Microelectronics Tel: 408-235-8600 [email protected] PCI, USB 3350 Scott Blvd., #24, Santa Clara, CA 95131 (USA) Fax: 408-235-8601 www.sandmicro.com SICAN Microeletronics Corp. Tel: 415-871-1494 [email protected] CAN bus, DSP, communications 400 Oyster Point Blvd., #512, So. San Francisco, CA 94080 (USA) Fax: 415-871-1504 www.sican-micro.com VAutomation Tel: 603-882-2282 [email protected] Microprocessors, microcontrollers, 20 Trafalgar Square Suite 443 (4th Floor) Nashua, NH 03063 (USA) Fax: 603-882-1587 www.vautomation.com communications / AP1 update OTES EATURES Includes 502/550/380 & Foundry Includes DS-401 v5.2 HP kits with v5.2.1 and v6.0.1 Sun, PC, DA1 platform remains at v5.2 Includes DS-401 v5.2 Requires signed license agreement Requires signed license agreement Sun and HP N F New version w/Win 95 to 3.11, update by request 5.20 5.20 5.20 No 5.20 5.20 ELEASE ERSION 01/04 5.26.0 DA1 platform remains at v6.0 REVIOUS R V P PDT AST OMP 7/96 7/967/96 5.2/6.0 Includes PRO Series 6.1 6.0 Includes PRO Series 6.1 7/96 6.0 7/96 5.2/6.0 Includes 502/550/380 4/96 L 11/96 6.1.1 C 1997 AY 9.01 LATFORM P BY X
- M 7.00 7.00 na na 7.00 7.00 na na 1.00 1.00 na na = Check BBS or FTP site for most current revision of EZTAG programming software.. * ERSION V TATUS URRENT 6.2 4.1. 7.00 7.007.00 7.007.00 na 7.00 na 7.00 na na na na 1.101.10 1.10 1.10 1.10 1.10 na na na na PC1 SN2 HP7 U C S ART OFTWARE P S VLS-EXT-PC1 6.0.1 7/96 6.0 Currently updating in-warranty cust. w/WVO UMBER S-SY-ADV-xxx EFERENCE ILINX DS-CDN-STD-xxxDS-MN8-STD-xxxDS-MN8-ADV-xxx DS-OR-BAS-PC1DS-OR-STD-PC1DS-VL-BAS-PC1 6.0.1 5.2.1DS-VL-STD-xxx 6.0.1 5.2.1DS-VL-ADV-xxx DS-VLS-BAS-PC1 5.2.1DS-VLS-STD-PC1 5.2.1 6.0.1 7/96 6.0.1DS-VLS-ADV-PC1 7/96 DS-3PA-BAS-xxx 6.0.1DS-3PA-STD-xxx 5.2.1 6.0.1DS-3PA-ADV-xxx DS-FND-BAS-PC1 5.2.1 7/96DS-FND-BSV-PC1 6.0.1DS-FND-STD-PC1 6.0.1 7/96 6.0DS-FND-STV-PC1 6.0.2 7/96 5.2.1 6.0.2 Customer w/v6.0 will receive v6.0.1 update 6.0.2DS-EVAL-XXX-C 5.2.1 6.0.2 6.0 7/96 7/96 Customer w/v6.0 will receive v6.0.1 update 6.0 2.00 6.0 7/96 Currently updating in-warranty cust. w/WVO Currently updating in-warranty cust. w/WVO 2.00 2/97 na 2/97 2.00 2/97 6.0.1 Customer w/v6.0 will receive v6.0.1 update 2/97 6.0.1 Includes support for XC4000E and XC9500 6.0.1 Includes support for XC4000E and XC9500 6.0.1 Includes support for XC4000E and XC9500 Includes support for XC4000E and XC9500 DS-371-xxxDS-380-xxx 5.2.1 5.2.1 5.2.1 5.2.1 5.2.1DS-SY-STD-xxx 5.2.1 7/96 7/96 5.2/6.0 5.2/6.0 Now available on HP7 5.2.1 5.2.1 7/96 X R N 31 ELEASED R SUPPORT
ILINX X SILICON RODUCT UNCTION Entry/Simulation/CoreCore + Interface DS-571-PC1 DS-560-xxxEntry,Simulation,Lib, Optimizer Module Generator & Optimizer 6.1.2 6.0.1 6.0.1 6.0.1 7/96 6.0 P F XXXXX XXXXX D XXXXXX XXXXXX XXXXXX XXXXXX XXXXXX XXXXXX XXXXXX XXXXXX XXXXXX XXXXXX XXXXXX DS- XXXXXX XXXXXX XXXXXX XXXXXX XXXXXX XXXXXX XXXXXX XXXXXX XXXXXX 2K 3K 4K/E 5K 7K 9K ESCRIPTION RODUCT P D XC7K, XC9500 Support XC7K, XC9500 Support ATEGORY RODUCT P C XEPLDCORE XABEL-CPLD XACT-CPLD Support XC7K MentorOrCADSynopsys Core ImplementationViewlogicViewlogic 8.4=A.4ViewlogicXABEL PROcaptureXBLOX DS-550-xxx PROsim Interface and Libraries Interface and LibrariesCadence Interface and LibrariesLibrariesand Interface 6.0.1Mentor Interface and Libraries DS-344-xxxMentor DS-390-PC1 5.2.1OrCAD Interface and Libraries DS-290-PC1Synopsys DS-35-PC1 5.2.1 DS-401-xxxSynopsys 7/96Viewlogic 6.0.1 DS-391-xxxViewlogic 5.2/6.0Viewlogic/S 6.0.1 Viewlogic/S PC update by request only 6.0.1 5.2.1Viewlogic/S Viewlogic/S 5.2.1 6.0.13rd Party Alliance 5.2.13rd Party Alliance 5.2.1Foundation Series 5.2.1Foundation Series 5.2.1Foundation Series Foundation Series 7/96 LogiCore-PCI Slave 7/96 7/96LogiCore-PCI MasterEvaluation 6.0 6.0 Support for SDT+, VST+ v1.2 X X LC-DI-PCIS-C LC-DI-PCIM-C : N=New Product E= Engineering software for in-warranty users by request only U= Update by request only * EY E VerilogLib. 2K,3K,4K,4KE,5K Models & XNF Translator ES-VERILOG-xxx
* U OrCAD U Viewlogic U 3rd Party Alliance U U
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XILINX INDIVIDUAL PRODUCTS INDIVIDUAL XILINX PACKAGES XILINX FAX RESPONSE FORM-XCELL 25 2Q97
Corporate Headquarters FAX Us Your Comments and Suggestions Xilinx, Inc. To: XCell Editor Xilinx Inc. FAX: 408-879-4676 2100 Logic Drive San Jose, CA 95124 From: ______Date: ______Tel: 408-559-7778 Fax: 408-559-7114 ❏ Please add my name to the XCell mailing list.
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