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Intel Stratix 10 Avalon-MM Interface for PCI Express Solutions User

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Intel Stratix 10 Avalon-MM Interface for PCI Express Solutions User L-tile and H-tile Avalon® Memory- mapped Intel® FPGA IP for PCI Express* User Guide Updated for Intel® Quartus® Prime Design Suite: 21.1 Subscribe UG-20033 | 2021.05.27 Send Feedback Latest document on the web: PDF | HTML Contents Contents 1. Introduction................................................................................................................... 5 1.1. Avalon-MM Interface for PCIe.................................................................................. 5 1.2. Features...............................................................................................................6 1.3. Release Information ..............................................................................................8 1.4. Device Family Support ...........................................................................................8 1.5. Recommended Fabric Speed Grades......................................................................... 9 1.6. Performance and Resource Utilization .................................................................... 10 1.7. Transceiver Tiles.................................................................................................. 10 1.8. PCI Express IP Core Package Layout.......................................................................11 1.9. Channel Availability..............................................................................................15 2. Quick Start Guide.......................................................................................................... 17 2.1. Design Components............................................................................................. 17 2.2. Directory Structure.............................................................................................. 18 2.3. Generating the Design Example............................................................................. 19 2.4. Simulating the Design Example..............................................................................21 2.5. Compiling the Design Example and Programming the Device..................................... 22 2.6. Installing the Linux Kernel Driver........................................................................... 23 2.7. Running the Design Example Application................................................................. 23 3. Interface Overview....................................................................................................... 25 3.1. Avalon-MM DMA Interfaces when Descriptor Controller Is Internally Instantiated.......... 25 3.2. Avalon-MM DMA Interfaces when Descriptor Controller is Externally Instantiated.......... 29 3.3. Other Avalon-MM Interfaces.................................................................................. 30 3.3.1. Avalon-MM Master Interfaces ....................................................................31 3.3.2. Avalon-MM Slave Interfaces.......................................................................32 3.3.3. Control Register Access (CRA) Avalon-MM Slave...........................................32 3.4. Clocks and Reset................................................................................................. 33 3.5. System Interfaces................................................................................................33 4. Parameters .................................................................................................................. 35 4.1. Avalon-MM Settings..............................................................................................36 4.2. Base Address Registers.........................................................................................37 4.3. Device Identification Registers...............................................................................38 4.4. PCI Express and PCI Capabilities Parameters........................................................... 39 4.4.1. Device Capabilities................................................................................... 39 4.4.2. Link Capabilities ......................................................................................39 4.4.3. MSI and MSI-X Capabilities ...................................................................... 39 4.4.4. Slot Capabilities ......................................................................................40 4.4.5. Power Management .................................................................................41 4.4.6. Vendor Specific Extended Capability (VSEC)................................................ 42 4.5. Configuration, Debug and Extension Options........................................................... 42 4.6. PHY Characteristics ............................................................................................. 43 4.7. Example Designs................................................................................................. 43 5. Designing with the IP Core........................................................................................... 44 5.1. Generation..........................................................................................................44 5.2. Simulation.......................................................................................................... 44 ® ® L-tile and H-tile Avalon Memory-mapped Intel FPGA IP for PCI Express* Send Feedback User Guide 2 Contents 5.3. IP Core Generation Output (Intel Quartus Prime Pro Edition)......................................45 5.4. Channel Layout and PLL Usage.............................................................................. 48 6. Block Descriptions........................................................................................................ 54 6.1. Interfaces........................................................................................................... 55 6.1.1. Intel Stratix 10 DMA Avalon-MM DMA Interface to the Application Layer......... 55 6.1.2. Avalon-MM Interface to the Application Layer...............................................67 6.1.3. Clocks and Reset..................................................................................... 72 6.1.4. Interrupts............................................................................................... 73 6.1.5. Flush Requests........................................................................................ 74 6.1.6. Serial Data, PIPE, Status, Reconfiguration, and Test Interfaces ......................75 7. Registers...................................................................................................................... 83 7.1. Configuration Space Registers............................................................................... 83 7.1.1. Register Access Definitions........................................................................85 7.1.2. PCI Configuration Header Registers............................................................ 86 7.1.3. PCI Express Capability Structures...............................................................87 7.1.4. Intel Defined VSEC Capability Header ........................................................ 90 7.1.5. Uncorrectable Internal Error Status Register ............................................... 92 7.1.6. Uncorrectable Internal Error Mask Register..................................................92 7.1.7. Correctable Internal Error Status Register .................................................. 93 7.1.8. Correctable Internal Error Mask Register .................................................... 93 7.2. Avalon-MM DMA Bridge Registers........................................................................... 94 7.2.1. PCI Express Avalon-MM Bridge Register Address Map....................................94 7.2.2. DMA Descriptor Controller Registers .......................................................... 99 8. Programming Model for the DMA Descriptor Controller...............................................105 8.1. Read DMA Example ........................................................................................... 107 8.2. Write DMA Example ...........................................................................................110 8.3. Software Program for Simultaneous Read and Write DMA ....................................... 113 8.4. Read DMA and Write DMA Descriptor Format .........................................................114 9. Programming Model for the Avalon-MM Root Port.......................................................116 9.1. Root Port TLP Data Control and Status Registers.....................................................116 9.2. Sending a TLP................................................................................................... 117 9.3. Receiving a Non-Posted Completion TLP................................................................ 117 9.4. Example of Reading and Writing BAR0 Using the CRA Interface................................ 117 10. Avalon-MM Testbench and Design Example ..............................................................121 10.1. Avalon-MM Endpoint Testbench ......................................................................... 122 10.2. Endpoint Design Example.................................................................................. 123 10.2.1. BAR Setup...........................................................................................125 10.3. Avalon-MM Test Driver Module............................................................................125
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