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Development of Field Programmable Gate Array-Based Reactor Trip NET176_proof ■ 30 March 2016 ■ 1/11 Nuclear Engineering and Technology xxx (2016): 1e11 Available online at ScienceDirect 65 66 1 67 2 Nuclear Engineering and Technology 68 3 69 4 70 5 journal homepage: www.elsevier.com/locate/net 71 6 72 7 73 8 74 9 Technical Note 75 10 76 11 Development of Field Programmable Gate Array-based 77 12 78 13 Reactor Trip Functions Using Systems Engineering Approach 79 14 80 15 81 16 * 82 17 Q20 Jaecheon Jung and Ibrahim Ahmed 83 18 Nuclear Power Plant Engineering, KEPCO International Nuclear Graduate School, 1456-1 Shinam-ri, Seosang-myeon, Ulju-gun, Ulsan 689- 84 19 85 882, Republic of Korea 20 86 21 87 22 article info abstract 88 23 89 24 90 25 Article history: Design engineering process for field programmable gate array (FPGA)-based reactor trip 91 26 Received 13 November 2015 functions are developed in this work. The process discussed in this work is based on the 92 27 Received in revised form systems engineering approach. The overall design process is effectively implemented by 93 28 16 February 2016 combining with design and implementation processes. It transforms its overall develop- 94 29 Accepted 17 February 2016 ment process from traditional V-model to Y-model. This approach gives the benefit of 95 30 Available online xxx concurrent engineering of design work with software implementation. As a result, it re- 96 31 97 32 duces development time and effort. The design engineering process consisted of five ac- Keywords: tivities, which are performed and discussed: needs/systems analysis; requirement 98 33 99 Field Programmable Gate Array analysis; functional analysis; design synthesis; and design verification and validation. 34 100 Finite State Machine with Data Those activities are used to develop FPGA-based reactor bistable trip functions that trigger 35 101 36 Path reactor trip when the process input value exceeds the setpoint. To implement design 102 37 Reactor Trip Functions synthesis effectively, a model-based design technique is implied. The finite-state machine 103 38 Systems Engineering with data path structural modeling technique together with very high speed integrated 104 39 circuit hardware description language and the Aldec Active-HDL tool are used to design, 105 40 model, and verify the reactor bistable trip functions for nuclear power plants. 106 41 Copyright © 2016, Published by Elsevier Korea LLC on behalf of Korean Nuclear Society. 107 42 108 43 109 44 110 45 111 46 112 47 113 48 1. Introduction support, and being easier to qualify. The RPS is the most 114 49 safety-critical instrumentation and control (I&C) system in 115 50 Q1 In the nuclear domain, the field programmable gate array NPPs. It safely trips the reactor whenever one or more of the 116 51 (FPGA) is the most recent electronic device that is being monitored plant processes exceed predefined limits. 117 52 considered by stakeholders to replace the software-based Due to criticality of the RPS, the software used in pro- 118 53 119 54 systems in performing the trip functions of the reactor pro- grammable logic controllers (PLCs) is rated as high-integrity tection system (RPS) of nuclear power plants (NPPs) because of software, and therefore assigned the highest software integ- 120 55 121 its potentials such as simplicity, testability, long-term rity level: 4. The higher the software integrity level the higher 56 122 57 123 58 * Corresponding author. 124 59 E-mail address: [email protected] (J. Jung). 125 60 This is an Open Access article distributed under the terms of the Creative Commons Attribution Non-Commercial License (http:// 126 61 creativecommons.org/licenses/by-nc/3.0) which permits unrestricted non-commercial use, distribution, and reproduction in any me- 127 62 dium, provided the original work is properly cited. 128 63 http://dx.doi.org/10.1016/j.net.2016.02.011 129 64 1738-5733/Copyright © 2016, Published by Elsevier Korea LLC on behalf of Korean Nuclear Society. Please cite this article in press as: J. Jung, I. Ahmed, Development of Field Programmable Gate Array-based Reactor Trip Functions Using Systems Engineering Approach, Nuclear Engineering and Technology (2016), http://dx.doi.org/10.1016/ j.net.2016.02.011 NET176_proof ■ 30 March 2016 ■ 2/11 2 Nuclear Engineering and Technology xxx (2016): 1e11 1 66 2 67 3 68 4 69 5 70 6 71 7 72 8 73 9 74 10 75 11 76 12 77 13 78 14 79 15 80 16 81 Fig. 1 e Design process (DOD MIL-STD-499B [4]). FPGA, field programmable gate array. Q17 17 82 18 83 19 84 20 the demand for verification and validation (V&V) activities. As the FPGA design life cycle. The Y-model is known for a hard- 85 21 indicated by IEEE Std. 1012 [1], the high-integrity software wareesoftware codesign. The suitability of Y-cycle for safety 86 22 requires a larger set of V&V processes and a more rigorous critical software for I&C system in NPP was demonstrated by 87 23 application of V&V tasks. Jung et al. [6] using the 3-Step software development process, 88 24 By replacing the PLC-based system with the FPGA-based and concluded that around 50% of development time savings 89 25 system, the use of OS and complex software applications is expected to be achieved by adopting Y-Cycle. This indicates 90 26 91 during plant operation can be minimized if not completely Y-model transformed from the traditional V-model for FPGA- 27 92 eliminated. An FPGA is a digital semiconductor device that can based trip function design (Fig. 2). 28 93 be used as a replacement for the current microprocessor- In the design and development of an FPGA system, the 29 94 30 based software systems. It is a digital programmable inte- code is compiled and mapped on the target architecture. The 95 31 grated circuit (IC) that contains thousands or millions of logic resulting intermediate implementation is then tested and 96 32 gates and interconnections that can be configured to imple- evaluated with respect to timing, power consumption, cost, 97 33 ment desired functionality. Even though FPGA design process etc., using simulation and analysis. Based on these metrics, 98 34 involves the use of configuration/programing software, the the designer decides about architecture and/or code adapta- 99 35 end product of the design can be regarded as a hardware- tions. This process is iteratively repeated until a satisfactory 100 36 based system [2,3]. design is found. Therefore, according to Hamann [7], the risk 101 37 However, to replace PLC functionalities with FPGA to that is linked to the design flow due to the Y-model is rela- 102 38 103 perform the trip functions, the development of FPGA-based tively small, since the designer can react in each iterations to 39 104 bistable trip algorithms is essential. Without the develop- performance problem and solve them. 40 105 41 ment of proper algorithms for FPGA, the replacement is The design synthesis phase, which comprises design and 106 42 completely impossible. implementation stages of FPGA-based RPS functions, is 107 43 Applying an FPGA to perform RPS functions requires 108 44 proper and accurate RPS bistable algorithms development. If a 109 45 proper and well-defined design process is applied to FPGA- 110 46 based RPS design, the V&V tasks can easily be achieved and 111 47 design error can be minimized. Therefore, the main focus area 112 48 of this work is to make the V&V of FPGA-based RPS functions 113 49 114 simpler using systems engineering approach in combination 50 115 with finite-state machine with data path (FSMD) structural 51 116 modeling techniques. 52 117 53 In order to develop an FPGA-based reactor trip functions, 118 54 the systems engineering approach defined by DOD MIL-STD- 119 55 499B [4] is applied (Fig. 1). The rectangular boxes represent 120 56 the stages for the development process. There are also inputs 121 57 to and outputs from the design process. The inputs are needs 122 58 from need/system analysis to the requirement analysis phase, 123 59 and the output is the final design outcome from design 124 60 synthesis. 125 61 126 Q2 The development life cycles recommended by IEC 62566 [5] 62 127 and EPRI TR1019181 [3] for FPGA development in NPP are based 63 128 64 on the traditional software V-model. The design of FPGA in- 129 e 65 volves both hardware and software design process. However, Fig. 2 Y-model transformed from traditional V-model for 130 the classical software development life cycle is not suitable for field programmable gate array based trip function design. Please cite this article in press as: J. Jung, I. Ahmed, Development of Field Programmable Gate Array-based Reactor Trip Functions Using Systems Engineering Approach, Nuclear Engineering and Technology (2016), http://dx.doi.org/10.1016/ j.net.2016.02.011 NET176_proof ■ 30 March 2016 ■ 3/11 Nuclear Engineering and Technology xxx (2016): 1e11 3 1 66 2 67 3 68 4 69 5 70 6 71 7 72 8 73 9 74 10 75 11 76 12 77 13 78 14 79 15 80 16 81 17 82 18 83 19 84 20 Fig. 3 e Trend of reactor trip events in Korea since 2000. I&C, instrumentation and control. 85 21 86 22 87 23 88 24 89 25 developed using FSMD architectural modeling techniques. 2. Need and system analysis 90 26 An FSMD is a structural design method used for designing 91 27 92 the digital circuits.
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