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Product Line Product Line Product Line Product Line High-Performance Simulator for Mixed Language Designs IEEE VHDL, SystemVerilog, Verilog-AMS, SystemC/C/C++ Verication Libraries: UVM, OS-VVM Verification Ecosystem Assertion-Based Verication: SVA, PSL for FPGA/SoC Designs Riviera-PRO™ A trusted name in EDA since 1984, Aldec understands that today’s engineers require innovative solutions to enable rapid deployment at every stage of ADVANCED Active-HDL™ development. VERIFICATION IEEE VHDL, Verilog, SystemVerilog (Design) Multi-FPGA & EDA Tool Design Flow Manager Aldec works closely with customers to understand HTML and PDF Design Documentation their real-world challenges and requirements, and Text, Schematic, FSM Design Entry Tools deliver a personal blueprint of solutions customized to fit their needs. FPGA DESIGN & SIMULATION HES-DVM™ ALINT™ Industry-leading Rule Libraries: STARC, RMM, DO-254 Acceleration, SCE-MI Emulation, Prototyping HW/SW DESIGN RULE Early Bug Detection during RTL Design Phase Virtual Platform Integration – HW/SW Co-Verification EMULATION CHECKING IEEE VHDL, Verilog, Mixed-Language Designs Transactor Library - Bus Models and Peripherals IDE for In-Depth Design Troubleshooting Extensive Debugging Capabilities PROTOTYPING BOARDS CyberWorkBenchR HES-7™ HIGH-LEVEL Supports control dominated circuits, datapath module Scalable up to 144 million ASIC gates Dedicated support for Altera® & Xilinx® FPGAs ARM® Cortex®-A9 Support with Xilinx® Zynq® SoC SYNTHESIS Automatic pipelining, Power optimization HDMI, USB, Bluetooth, Wi-Fi, Ethernet, and more C-based Formal Verification (Assertions, Properties) Expandable, Non-proprietary Connectors REQUIREMENTS LIFECYCLE Traceability to HDL Design and Testbench MANAGEMENT Requirements Coverage Analysis FPGA LEVEL Change Impact Analysis DO-254/CTS™ Test-Results Management IN-TARGET Increase verification coverage by test TESTING Testbench reuse as hardware test vectors Spec-TRACER™ 100% device I/O controllability and visibility Testing at-speed on target device: Altera®, Microsemi®, Xilinx® www.aldec.com R THE DESIGN VERIFICATION COMPANY Customer Stories Active-HDL™ Riviera-PRO™ “With a good editor/compiler and a versatile, easy to “Riviera-PRO provided Infineta with high speed use simulator, Active-HDL was considered the best simulation of high-density Verilog design with DPI featured design tool compared to leading connections for system software integration. competitors. The quality of the design environment Riviera-PRO is used by individual engineers for and good integration with source control tools interactive debugging and regressions on an definitely saves time on both new development and automated, multi-node simulator farm.” maintaining existing code.” DO-254/CTS™ ALINT™ “Our project involved an Altera® Cyclone® II FPGA “Prior to using ALINT from Aldec, all VHDL code had to with multiple clocks and speeds in excess of 128 be personally reviewed by a principal engineer. This was MHz. We wanted a complete verification path with becoming an increasingly laborious task consuming requirements traceability and simulation results large amounts of valuable time and had the potential to maintenance to validate that our system would miss errors – especially in larger projects. Using ALINT work on the final hardware we deliver to our means that code can be checked by a design engineer customer. Aldec’s DO-254/ED-80 CTS gave us an much earlier in the design cycle, thus increasing effective way to meet the Level B Verification effectiveness and reducing development time by process requirements imposed by the DO-254 reducing code errors. The final review can now rely on certification authorities.” the ALINT reports – simplifying the process, thus reducing the time taken for approval.” Technical Support Microsemi® RTAX Prototyping “Thanks to Aldec’s support team, learning how to “We had a very aggressive schedule. We needed a way simulate a new and rather complex design took to quickly verify the design functionality and integrate nearly no time at all. It is quite clear that Aldec’s support. The Aldec prototyping adaptor saved us two engineers have left no stone unturned in their quest months off our development schedule and over for excellence.” $72,000 off our project costs.” Headquarters - US Europe Israel Japan China India Taiwan 2260 Corporate Circle Mercia House 1 Haofe Street Shinjyuku Estate Bldg. 9F Suite 2004, BaoAn Building #2145, 17th Main No. 37, Section 2 Henderson,Aldec, NV 89074 Inc. 51 The Green, South Bar KadimaIsrael 60920 1-34-15, Shinjyuku,Europe Shinjyuku-ku #800 DongFang JapanRoad 2nd Cross, HAL 2nd Stage Liujia 5th Road Corporate - N. AmericaBanbury, OX16 9AB IsraelPh. +972.072.2288316 Ph. +44.1295. 20.1240 Ph. +81.3.5312.1791 USA Tokyo 160-0022 PuDong District Indiranagar Hsinchu County 302 R Ph +1.702.990.4400United Kingdom [email protected] Japan [email protected] Shanghai City, 200122,[email protected] P.R. China Bangalore, 560008, India Zhubei City, Taiwan THE DESIGN VERIFICATION COMPANY [email protected] Phone: +1.702.990.4400 Phone: +44.1295. 20.1240 Phone:China +972.072.2288316 Phone: +81.3.5312.1791India Phone: +86.21.6875.2030Taiwan Phone: +91.80.3255.1030 Phone: +886.3.6587712 Email: [email protected] Email: [email protected] Email: [email protected] Email: [email protected] Email: [email protected] Email: [email protected] Email: [email protected] R Ph. +86.21.6875.2030 Ph. +91.80.3255.1030 Ph. +886.3.6587712 THE DESIGN VERIFICATION COMPANY © 2012 Aldec,Visit Inc. Aldecus isat a trademark www.aldec.com of Aldec, Inc. All other trademarks or registered [email protected] are property of their respective owners. Rev_07.12 [email protected] [email protected] www.aldec.com © 2013 Aldec, Inc. Aldec is a trademark of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners. Rev_10.13.
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