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Hardware & Software Standards
Hardware & Software Standards Introduction This document identifies the current City of Chicago standards for its hardware and software environments, and is intended primarily for City department and vendor use. These standards do not mean that other software and hardware, which might have been previously listed as standard, may not be used or supported, but the following items should be purchased for any new initiative or growth/replacement needs. Any proposals for non-standard hardware or software purchases or questions/comments should be forwarded to the Department of Innovation and Technology (DoIT) Enterprise Architecture Board for review, and will need to be approved via the Technology Purchase Review and Approval (TPRA) process. Standards denoted with an asterisk (*) are currently under review. Platform Standards Operating System (O/S) Hardware Platform Solaris 10 (Unix) (Oracle) Sun Microsystems RedHat Linux Enterprise Server 6.x, 7.x Dell RedHat Linux Enterprise Server 7.x (PCI Services) Dell VMWare VSphere 6.5U1 Dell Windows 2012 R2 & 2016 (Standard and Enterprise) Dell Windows 7, Windows 10 Dell, Panasonic Page 1 of 6 Last Revised January 2018 Hardware & Software Standards Enterprise Services Type Windows 2008 Server All other platforms Oracle Enterprise 11gR2, 12cR1; Postgres 9.x or 10.x (EnterpriseDB or Database N/A community) Print O/S n/a File O/S n/a Email Exchange 2016 / Office365 n/a Desktops, Laptops, & Tablets Type Model Standard Users Dell OptiPlex 5050 SFF, Dell OptiPlex 7450 All-In-One Mobile User Latitude 12 Rugged Extreme Latitude 14 Rugged 5414 Latitude 12 2 in 1 with case and Doc Latitude 5480 14" Laptop 6th gen proc High-End Workstation Dell Precision T5810 Laptop Accessories Docking- For the E-5470 units, Dell Business Dock - WD15 with 130W Adapter Monitor Dell 23 Monitor – P2317H Page 2 of 6 Last Revised January 2018 Hardware & Software Standards Printing and Scanning The Department of Fleet and Facility Management (2FM) oversees print services for the City of Chicago. -
Cadence SPB / Orcad 17.4 System Requirements
A Parallel Systems Technical Note Cadence SPB / OrCAD 17.4 System Requirements Supported Operating Systems Windows 10 (64-bit) Professional, including Dark Theme mode Windows Server 2012 (All Service Packs) Windows Server 2012 R2 Windows Server 2016 Note: Cadence Allegro and OrCAD products do not support Windows 10 Starter and Home Basic. In addition, Windows Server support does not include support for Windows Remote Desktop. Windows RT and Tablets/Phones, including Windows 10 Phone, are not supported. Note: 64-bit Windows require 64-bit Flex software dongle drivers if using dongle-based licensing. Recommended Hardware Intel® Core™ i7 4.30 GHz or AMD Ryzen™ 7 4.30 GHz with at least 4 cores Note: Faster processors are preferred. 16 GB RAM 50 GB free disk space (SSD drive is recommended) 1920 x 1200 display resolution with true color (at least 32bit colour) A dedicated graphics card supporting OpenGL, minimum 2GB (with additional support for DX11 for 3D Canvas) Dual monitors (For physical design) Broadband Internet connection for some service Ethernet port/card (for network communications and security hostID) Three-button Microsoft-compatible mouse Supported MATLAB Version R2019A-64Bit (For the PSpice-MATLAB interface) Microsoft SharePoint for Allegro Pulse Cadence® Allegro® Pulse supports an interface to Microsoft SharePoint. Following are the requirements for SharePoint: • Windows Server 2012 (64-bit) • SharePoint Foundation 2013 • Microsoft SQL Server 2012 (64-bit) • Following 64-bit browsers: • Microsoft® Internet Explorer® 11.0 on windows • Mozilla Firefox 52.0 ESR on Windows • Mozilla Firefox 52.0 on Linux • Google Chrome 58.0 on Windows Using Spaces in File and Directory Names Support for spaces in file and directory names applies only to Windows. -
Media Contacts
Media Contacts: Sarika Patel GolinHarris 972-341-2504 [email protected] Debbie Shemony Texas Instruments 301-407-9338 [email protected] (Please do not publish these numbers or e-mail addresses.) A better way to cloud: TI’s new KeyStone multicore SoCs revitalize cloud applications Announcement quote sheet 3L Ltd. “Supporting TI’s new KeyStone-based multicore SoCs is a natural extension for us, as we have been simplifying the development of solutions involving multiple processing elements for over 20 years,” said Peter Robertson, President and TechFounder, 3L Ltd. “Together with TI, we’re making designing with multicore easier for developers by automating the interconnection management when tasks are removed between cores or devices. The end result of our collaboration is making the development processes easier, faster and more efficient for designers.” 6WIND “We are delighted to support TI as it broadens its KeyStone-based SoC product line into additional markets with critical network performance requirements,” said Eric Carmès, CEO, 6WIND. “As one of the first members of the TI Design Network to announce support for the KeyStone multicore architecture, we look forward to providing the proven 6WINDGate™ packet processing software to our mutual customers. The combination of the 6WINDGate software and the newest KeyStone architecture-based SoCs represent an ideal system solution for the demanding network performance challenges faced in today’s mobile and cloud infrastructure markets.” Advantech “With TI’s new KeyStone-based multicore SoCs, Advantech is able to expand its product lines from existing DSP-based signal and media processing centric solutions to hybrid designs that leverage multiple ARM and DSP cores in a seamless integration for control and data processing,” said David Lin, senior director of DSP and video solutions, Advantech. -
GS40 0.11-Μm CMOS Standard Cell/Gate Array
GS40 0.11-µm CMOS Standard Cell/Gate Array Version 1.0 January 29, 2001 Copyright Texas Instruments Incorporated, 2001 The information and/or drawings set forth in this document and all rights in and to inventions disclosed herein and patents which might be granted thereon disclosing or employing the materials, methods, techniques, or apparatus described herein are the exclusive property of Texas Instruments. No disclosure of information or drawings shall be made to any other person or organization without the prior consent of Texas Instruments. IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this war- ranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (“Critical Applications”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WAR- RANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. -
1A APPENDIX a UNITED STATES COURT of APPEALS for THE
1a APPENDIX A UNITED STATES COURT OF APPEALS FOR THE FEDERAL CIRCUIT ___________________ MENTOR GRAPHICS CORPORATION, AN OREGON CORPORATION, Plaintiff-Cross-Appellant v. EVE-USA, INC., A DELAWARE CORPORA- TION, SYNOPSYS EMULATION AND VERIFI- CATION S.A.S., FORMED UNDER THE LAWS OF FRANCE, SYNOPSYS, INC., A DELAWARE CORPORATION, Defendants-Appellants ___________________ 2015-1470, 2015-1554, 2015-1556 ___________________ Appeals from the United States District Court for the District of Oregon in Nos. 3:10-cv-00954-MO, 3:12-cv-01500-MO, 3:13-cv-00579-MO, Judge Michael W. Mosman. ___________________ Decided: March 16, 2017 ___________________ MARK E. MILLER, O’Melveny & Myers LLP, San Francisco, CA, argued for plaintiff-cross-appellant. 2a Also represented by ANNE E. HUFFSMITH, LUANN LO- RAINE SIMMONS. E. JOSHUA ROSENKRANZ, Orrick, Herrington & Sutcliffe LLP, New York, NY, argued for defendants- appellants. Also represented by DANIEL A. RUBENS, ANDREW D. SILVERMAN; ROBERT M. LOEB, ERIC SHUM- SKY, Washington, DC; INDRA NEEL CHATTERJEE, VICKI L. FEEMAN, TRAVIS JENSEN, SCOTT T. LONARDO, Menlo Park, CA; WILLIAM H. WRIGHT, Los Angeles, CA. SEAN C. CUNNINGHAM, DLA Piper LLP (US), San Diego, CA, for amici curiae Hewlett-Packard Com- pany, Aruba Networks, Inc., NETGEAR, Inc., Newegg Inc., Oracle America, Inc., Ruckus Wireless, Inc., Safeway Inc., SAS Institute Inc., Varian Medical Sys- tems, Inc., VeriFone, Inc., VIZIO, Inc. ________________________ Before LOURIE, MOORE, and CHEN, Circuit Judges. MOORE, Circuit Judge. The present appeal arises from litigation in the District of Oregon between Mentor Graphics Corp. (“Mentor”) and Synopsys, Inc., Synopsys Emulation and Verification S.A.S., and EVE-USA, Inc. -
Java Programming Language, Java SE 6
Java Programming Language, Java SE 6 Electronic Presentation SL-275-SE6 REV G.2 D61748GC11 Edition 1.1 Copyright © 2008, 2010, Oracle and/or its affiliates. All rights reserved. Disclaimer This document contains proprietary information, is provided under a license agreement containing restrictions on use and disclosure, and is protected by copyright and other intellectual property laws. You may copy and print this document solely for your own use in an Oracle training course. The document may not be modified or altered in any way. Except as expressly permitted in your license agreement or allowed by law, you may not use, share, download, upload, copy, print, display, perform, reproduce, publish, license, post, transmit, or distribute this document in whole or in part without the express authorization of Oracle. The information contained in this document is subject to change without notice. If you find any problems in the document, please report them in writing to: Oracle University, 500 Oracle Parkway, Redwood Shores, California 94065 USA. This document is not warranted to be error-free. Sun Microsystems, Inc. Disclaimer This training manual may include references to materials, offerings, or products that were previously offered by Sun Microsystems, Inc. Certain materials, offerings, services, or products may no longer be offered or provided. Oracle and its affiliates cannot be held responsible for any such references should they appear in the text provided. Restricted Rights Notice If this documentation is delivered to the U.S. Government or anyone using the documentation on behalf of the U.S. Government, the following notice is applicable: U.S. -
Co-Emulation of Scan-Chain Based Designs Utilizing SCE-MI Infrastructure
UNLV Theses, Dissertations, Professional Papers, and Capstones 5-1-2014 Co-Emulation of Scan-Chain Based Designs Utilizing SCE-MI Infrastructure Bill Jason Pidlaoan Tomas University of Nevada, Las Vegas Follow this and additional works at: https://digitalscholarship.unlv.edu/thesesdissertations Part of the Computer Engineering Commons, Computer Sciences Commons, and the Electrical and Computer Engineering Commons Repository Citation Tomas, Bill Jason Pidlaoan, "Co-Emulation of Scan-Chain Based Designs Utilizing SCE-MI Infrastructure" (2014). UNLV Theses, Dissertations, Professional Papers, and Capstones. 2152. http://dx.doi.org/10.34917/5836171 This Thesis is protected by copyright and/or related rights. It has been brought to you by Digital Scholarship@UNLV with permission from the rights-holder(s). You are free to use this Thesis in any way that is permitted by the copyright and related rights legislation that applies to your use. For other uses you need to obtain permission from the rights-holder(s) directly, unless additional rights are indicated by a Creative Commons license in the record and/ or on the work itself. This Thesis has been accepted for inclusion in UNLV Theses, Dissertations, Professional Papers, and Capstones by an authorized administrator of Digital Scholarship@UNLV. For more information, please contact [email protected]. CO-EMULATION OF SCAN-CHAIN BASED DESIGNS UTILIZING SCE-MI INFRASTRUCTURE By: Bill Jason Pidlaoan Tomas Bachelor‟s Degree of Electrical Engineering Auburn University 2011 A thesis submitted -
Uwlink Interface / Development Platform
UWLink Interface / Development platform UWLink Mainboard User Guide Hardware / Tool description User Guide 1.0, 2010-06-01 Wireless Control Edition 2010-07-16 Published by Infineon Technologies AG 81726 Munich, Germany © 2010 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain -
MACABEL ABEL for the APPLE MACINTOSH Nor IIX WORKSTATION A/UX VERSION
SPECIFICATIONS MACABEL ABEL FOR THE APPLE MACINTOSH nOR IIX WORKSTATION A/UX VERSION GENERAL DESCRIPTION ABEL.'" the industry standard PLD design software, is now available on the Apple Macintosh® II or IIx workstation. MacABEL allows you to take advantage of the personal productivity features of the Macintosh to easily describe and implement logic designs in programmable logic devices (PLDs) and PROMs. Like ABEL Version 3.0 for other popular workstations, MacABEL combines a natural high-level design language with a language processor that converts logic descriptions to programmer load files. These files contain the required information to program and test PLDs. MacABEL allows you to describe your design in any combi nation of Boolean equations, truth tables or state diagrams whichever best suits the logic you are describing or your comfort level. Meaningful names can be assigned to signals; signals grouped into sets; and macros used to simplify logic descriptions - making your logic design easy to read and • Boolean equations understand. • State machine diagram entry, using IF-THEN-ELSE, CASE, In addition, the software's language processor provides GOTQ and WITH-ENDWITH statements powerful logic reduction, extensive syntax and logic error • Truth tables to specify input to output relationships for both checking - before your device is programmed. MacABEL combinatorial and registered outputs supports the most powerful and innovative complex PLDs just • High-level equation entry, incorporating the boolean introduced on the market, as well as many still in development. operators used in most logic designs < 1 1 & 1 # 1 $ 1 1 $ ) , MacABEL runs under the Apple A/UX'" operating system arithmetic operators <- I + I * I I I %I < < I > > ) , relational utilizing the Macintosh user interface. -
GOOGLE LLC V. ORACLE AMERICA, INC
(Slip Opinion) OCTOBER TERM, 2020 1 Syllabus NOTE: Where it is feasible, a syllabus (headnote) will be released, as is being done in connection with this case, at the time the opinion is issued. The syllabus constitutes no part of the opinion of the Court but has been prepared by the Reporter of Decisions for the convenience of the reader. See United States v. Detroit Timber & Lumber Co., 200 U. S. 321, 337. SUPREME COURT OF THE UNITED STATES Syllabus GOOGLE LLC v. ORACLE AMERICA, INC. CERTIORARI TO THE UNITED STATES COURT OF APPEALS FOR THE FEDERAL CIRCUIT No. 18–956. Argued October 7, 2020—Decided April 5, 2021 Oracle America, Inc., owns a copyright in Java SE, a computer platform that uses the popular Java computer programming language. In 2005, Google acquired Android and sought to build a new software platform for mobile devices. To allow the millions of programmers familiar with the Java programming language to work with its new Android plat- form, Google copied roughly 11,500 lines of code from the Java SE pro- gram. The copied lines are part of a tool called an Application Pro- gramming Interface (API). An API allows programmers to call upon prewritten computing tasks for use in their own programs. Over the course of protracted litigation, the lower courts have considered (1) whether Java SE’s owner could copyright the copied lines from the API, and (2) if so, whether Google’s copying constituted a permissible “fair use” of that material freeing Google from copyright liability. In the proceedings below, the Federal Circuit held that the copied lines are copyrightable. -
Simulating Altera Designs
1. Simulating Altera Designs May 2013 QII53025-13.0.0 QII53025-13.0.0 This document describes simulating designs that target Altera® devices. Simulation verifies design behavior before device programming. The Quartus® II software supports RTL and gate level design simulation in third-party EDA simulators. Altera Simulation Overview Simulation involves setting up your simulator working environment, compiling simulation model libraries, and running your simulation. Generate simulation files in an automated or custom flow. Refer to Figure 1–1 and Table 1–3. Figure 1–1. Simulation in Quartus II Design Flow Design Entry (HDL, Qsys, DSP Builder) Altera Simulation RTL Simulation Models Quartus II Design Flow Gate-Level Simulation Post-synthesis functional Post-synthesis Analysis & Synthesis simulation netlist functional simulation EDA Fitter Netlist Post-fit functional Post-fit functional (place-and-route) Writer simulation netlist simulation Post-fit timing TimeQuest Timing Analyzer (Optional)Post-fit timing Post-fit simulation netlist (1) timing simulation simulation (3) Device Programmer (1) Timing simulation is not supported for Arria® V, Cyclone® V, Stratix® V, and newer families. You can use the Quartus II NativeLink feature to automatically generate simulation files and scripts. NativeLink can launch your simulator a from within the Quartus II software. Use a custom flow for more control over all aspects of simulation file generation. © 2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. -
Siemens EDA / Mentor Graphics License Usage Reports
Siemens EDA / Mentor Graphics License Usage Reports Siemens EDA (formerly Mentor Graphics) is a US-based Effectively optimize your electronic design automation multinational corporation for Siemens EDA / Mentor Graphics electrical engineering and electronics. licenses and ensure all resource requirements are met. Tracking usage across the organization (location, team, etc.) is critical for optimizing license selection and expenditures. Product Suites: Optimize Siemens EDA (formerly Mentor Graphics) licenses All IC Products that your team uses by taking a look at patterns of historical All PCB Software All IC Packaging Software usage: Calibre Design Tanner EDA Groups and Projects Solid Edge License Denials And more License Efficiency License Harvesting License Pool - Total number of Siemens EDA (formerly Mentor Graphics) licenses and Users Real-Time / Actual usage Checkout times - Times and frequency Alerts Set up alerts to stay informed about the status of Siemens 1 EDA (formerly Mentor Graphics) licenses (See here). 2 0 2 . 5 1 . Generate Reports 6 - We have a full suite of reports available (more here). A D Our reports can also help you to look at license usage E m statistics according to organizational units. a e T Looking for a license optimization tool for growth and monitoring Siemens EDA / Mentor Graphics license servers? Looking to control access to high-cost, advanced features licenses offered by one of TeamEDA, Inc. the Siemens EDA / Mentor Graphics license servers? (603) 656-5200 [email protected] “License Asset Manager” and “LAMUM” are trademark names of TeamEDA and are products solely of TeamEDA..