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Xilinx Vivado Design Suite User Guide: Logic Simulation (UG900)

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Vivado Design Suite User Guide Logic Simulation UG900 (v2013.1) March 20, 2013 Notice of Disclaimer The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of the Limited Warranties which can be viewed at http://www.xilinx.com/warranty.htm; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in Critical Applications: http://www.xilinx.com/warranty.htm#critapps. © Copyright 2012-2013 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. Logic Simulation www.xilinx.com UG900 (v2013.1) March 20, 2013 Revision History The following table shows the revision history for this document. Date Version Revision 03/20/13 2013.1 Throughout the document: interspersed 64 Tcl Commands. Expanded Using Non-Project Mode: Command and Batch Script Options, page 15. Added information about using Tcl commands in Introduction, page 18. Changed Simulation Library paths and the <Vivado_Install_Area> to be Vivado specific. Added UNISIM Library module examples. Added content to SECUREIP Simulation Library, page 23 Added Riviera-PRO/Active HDL from Aldec in Table 2-4, page 24. Added Special Considerations for Using SECUREIP Libraries, page 24 along with a note on Verilog requirements. Changed IES and VCS examples in Method 1: Using Library or File Compile Order (Recommended), page 27. Added Using the VCD Feature - Using the Value Change Dump Feature, page 35. Changed Using the ASYNC_REG Constraint, page 40. Added information about Global Set and Reset and Global Tristate Signals in VHDL, page 37. Corrected the zip file location in System Level Description, page 44. Changed WARN_ALL to WARNING_ALL in SIM_COLLISION_CHECK Strings, page 46. Added the -O switch to xelab Command Syntax Options, page 51. Replaced Figure 4-6, page 78 Replaced Project Settings: Target Simulator Options, Figure 4-2. Replaced Add Sources Dialog Box, page 71, Figure 4-4. Replaced Simulation Menu Options, page 76, Figure 4-7. Added Relaunch option description. Replaced the image of the Simulation Toolbar, page 80 Added Using the report_driver Tcl Command, page 92. Added Using the add_force Tcl Command, page 93. Added Debugging in Third Party Simulators, page 128. Added a caution about verifying library compile order. Added content to Using Mixed Language Simulation. Added information on how to setup and run a third party simulator to Appendix A, Running Simulation with Third Party Simulators Outside Vivado IDE. Added a diagram on how to debug third party simulations: Figure A-2, page 128. Logic Simulation www.xilinx.com UG900 (v2013.1) March 20, 2013 Table of Contents Revision History . 3 Chapter 1: Logic Simulation Overview Introduction . 7 Simulation Flow . 7 Supported Simulators . 11 Vivado Simulator Features . 11 Language Support . 12 OS Support and Release Changes . 12 Simulation Libraries . 12 Simulation Modes of Operation . 14 Chapter 2: Understanding Vivado Simulation Components Introduction . 18 About Testbenches or Stimulus Files . 18 Using Simulation Libraries. 20 Netlist Generation Process in Non-Project Mode . 30 Using the Value Change Dump Feature . 35 Using Global Reset and Tristate for Simulation . 35 RTL Simulation Using Xilinx Libraries . 38 Disabling X Propagation for Synchronous Elements . 41 Simulation of Configuration Interfaces . 42 Disabling Block RAM Collision Checks for Simulation . 46 Chapter 3: Compiling and Simulating the Design Introduction . 47 Parsing Design Files . 47 Elaborating and Generating a Snapshot Using xelab. 50 Using xsim to Simulate the Design Snapshot. 55 Project File Syntax . 56 Predefined XILINX_SIMULATOR Macro for Verilog Simulation . 57 Simulating the Design in Non-Project Mode . 57 Running a Behavioral Simulation . 58 Running Post-Synthesis and Post-Implementation Simulations. 59 Logic Simulation www.xilinx.com 4 UG900 (v2013.1) March 20, 2013 Library Mapping File (xsim.ini) . 60 xelab, xvhd, and xvlog Command Options. 61 Using Mixed Language Simulation . 64 Chapter 4: Running Simulation in the Vivado IDE and Debugging Source Code Introduction . 69 Using Simulation Settings . 70 Managing Simulation Sources. 73 Using the Vivado Simulator. 77 Running Post-Synthesis and Post-Implementation Timing Simulation . 85 Running Post-Synthesis Simulations. 86 Running Post-Implementation Simulations . 87 Identifying the Simulation Run . 88 Pausing a Simulation . 88 Saving Simulation Results . 88 Closing Simulation . 89 Vivado Simulator Standalone Flow Example . 89 Debugging at the Source Level . 90 Rules for Values in Simulation Tcl Commands. 94 Chapter 5: Analyzing with Waveforms Introduction . 96 Using Wave Configurations and Windows . 97 Viewing Simulation Data from Prior Simulation Settings (Static Simulation) . 99 Understanding HDL Objects in Waveform Configurations . 100 Customizing the Waveform. 104 Controlling the Waveform Display . 112 Organizing Waveforms . ..
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