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UG908 (V2019.2) October 30, 2019 Revision History See all versions of this document Vivado Design Suite User Guide Programming and Debugging UG908 (v2019.2) October 30, 2019 Revision History Revision History The following table shows the revision history for this document. Section Revision Summary 10/30/2019 Version 2019.2 General Updates Updated for Vivado 2019.2 release. 05/22/2019 Version 2019.1 Appendix E: Configuration Memory Support Replaced Configuration Memory Support Tables. Bus Plot Viewer Added new section on Bus Plot Viewer. High Bandwidth Memory (HBM) Monitor Added new section on High Bandwidth (HBM) Monitor. UG908 (v2019.2) October 30, 2019Send Feedback www.xilinx.com Vivado Programming and Debugging 2 Table of Contents Revision History...............................................................................................................2 Chapter 1: Introduction.............................................................................................. 8 Getting Started............................................................................................................................ 8 Debug Terminology.................................................................................................................... 9 Chapter 2: Vivado Lab Edition................................................................................13 Installation................................................................................................................................. 13 Using the Vivado Lab Edition .................................................................................................. 14 Vivado Lab Edition Project .......................................................................................................16 Programming Features ........................................................................................................... 19 Debug Features ........................................................................................................................ 20 Chapter 3: Generating the Bitstream or Device Image.......................... 21 Changing the Bitstream File Format Settings........................................................................22 Changing Device Configuration Bitstream Settings............................................................. 22 Chapter 4: Programming the Device................................................................. 24 Opening the Hardware Manager............................................................................................ 24 Opening Hardware Target Connections.................................................................................24 Connecting to a Hardware Target Using hw_server............................................................. 25 Opening a New Hardware Target........................................................................................... 26 Troubleshooting a Hardware Target.......................................................................................28 Associating a Programming File with the Hardware Device................................................30 Programming the Hardware Device....................................................................................... 30 Closing the Hardware Target...................................................................................................34 Closing a Connection to the Hardware Server...................................................................... 35 Reconnecting to a Target Device with a Lower JTAG Clock Frequency ..............................35 Connecting to a Server with More Than 32 Devices in a JTAG Chain.................................. 36 Chapter 5: Remote Debugging in Vivado........................................................ 38 Using Vivado Hardware Server to Debug Over Ethernet..................................................... 38 Xilinx Virtual Cable (XVC).......................................................................................................... 39 UG908 (v2019.2) October 30, 2019Send Feedback www.xilinx.com Vivado Programming and Debugging 3 Chapter 6: Programming Configuration Memory Devices....................50 Generate Bitstreams for use with Configuration Memory Devices.................................... 51 Creating a Configuration Memory File................................................................................... 52 Creating a Configuration Memory File for SPI Dual Quad (x8) Devices............................. 53 Connect to the Hardware Target in Vivado............................................................................54 Adding a Configuration Memory Device................................................................................ 55 Programming a Configuration Memory Device.................................................................... 56 Booting the Device....................................................................................................................59 Configuration Failures in Master Mode..................................................................................60 Chapter 7: Advanced Programming Features.............................................. 61 Readback and Verify................................................................................................................. 61 Generating Encrypted and Authenticated Files for 7 Series Devices..................................65 Generating Encrypted and Authenticated Files for UltraScale and UltraScale+................68 Programming the AES Key for 7 Series Devices.................................................................... 73 Programming the AES Key for UltraScale and UltraScale+ Devices....................................75 eFUSE Register Access and Programming............................................................................. 77 Cable Support for eFUSE Programming.................................................................................78 eFUSE Register Access and Programming for 7 Series Devices.......................................... 78 eFUSE Register Access and Programming for UltraScale and UltraScale+ Devices..........84 eFUSE NKZ File...........................................................................................................................91 System Monitor ........................................................................................................................ 92 Chapter 8: Serial Vector Format (SVF) File Programming......................94 Creating an SVF Target............................................................................................................. 94 Adding Devices to an SVF Target.............................................................................................97 Adding Configuration Memory Parts to Xilinx Devices...................................................... 102 Operations on the SVF Chain.................................................................................................104 Writing SVF Files...................................................................................................................... 107 Executing SVF Files..................................................................................................................109 Chapter 9: Debugging the Design..................................................................... 110 RTL-Level Design Simulation..................................................................................................110 Post-Implemented Design Simulation................................................................................. 110 In-System Logic Design Debugging......................................................................................111 In-System Serial I/O Design Debugging.............................................................................. 111 Chapter 10: In-System Logic Design Debugging Flows......................... 112 UG908 (v2019.2) October 30, 2019Send Feedback www.xilinx.com Vivado Programming and Debugging 4 Probing the Design for In-System Debugging.................................................................... 112 Using the Netlist Insertion Debug Probing Flow................................................................ 113 HDL Instantiation Debug Probing Flow Overview.............................................................. 128 Using the HDL Instantiation Debug Probing Flow..............................................................129 Debug Flow in IP Integrator.................................................................................................. 139 Implementing the Design Containing the Debug Cores....................................................142 ILA Core and Timing Considerations.................................................................................... 142 Debug Cores Clocking Guidelines.........................................................................................143 Adding Vivado Debug Cores to a Partial Reconfiguration Design.................................... 147 Chapter 11: Debugging Logic Designs in Hardware................................148 Using Vivado Logic Analyzer to Debug the Design.............................................................148 Connecting to the Hardware Target and Programming the Device.................................149 Vivado Hardware Manager Dashboards ............................................................................. 150 Setting up the ILA Core to
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