DOCSLIB.ORG

UG898 (V2019.2) October 30, 2019 Revision History

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
UG898 (V2019.2) October 30, 2019 Revision History See all versions of this document Vivado Design Suite User Guide Embedded Processor Hardware Design UG898 (v2019.2) October 30, 2019 Revision History Revision History The following table shows the revision history for this document. Section Revision Summary 10/30/2019 Version 2019.2 General Updates • Updated for Vivado 2019.2 release • Updated for Vitis™ software platform 06/04/2019 Version 2019.1 General Updates Initial 2019.1 release. MicroBlaze Configuration Wizard: MMU Page Updated links to Cache Page. Using the MicroBlaze Configuration Window Clarified number of block RAMs in 32-bit and 64-bit modes. Trace and Profiling Additional information on Extended Profiling. UG898 (v2019.2) October 30, 2019 Send Feedback www.xilinx.com Embedded Processor Hardware Design 2 Table of Contents Revision History...............................................................................................................2 Chapter 1: Introduction..............................................................................................5 Device Tools Flow Overview....................................................................................................... 5 General Steps for Creating an Embedded Processor Design................................................ 7 Completing Connections Using Designer Assistance.............................................................9 Making Manual Connections in a Design...............................................................................15 Manually Creating and Connecting to I/O Ports...................................................................16 Enhanced Designer Assistance................................................................................................17 Platform Board Flow in IP Integrator..................................................................................... 18 Memory-Mapping in the Address Editor................................................................................19 Adding RTL to Block Design..................................................................................................... 20 Running Design Rule Checks................................................................................................... 24 Integrating a Block Design in the Top-Level Design.............................................................24 Vivado Pin Planner View of PS I/O...........................................................................................26 Vivado IDE Generated Embedded Files ................................................................................. 26 Using the Vitis software platform .......................................................................................... 27 Chapter 2: Using a Zynq UltraScale+ MPSoC Device in an Embedded Design.................................................................................................... 30 Designing Zynq UltraScale+ MPSoC Devices......................................................................... 30 Overview of Zynq UltraScale+ MPSoc Configurations.......................................................... 33 Validation IP............................................................................................................................... 56 Finishing the Design................................................................................................................. 56 Chapter 3: Using a Zynq-7000 Processor in an Embedded Design.... 58 Designing with Zynq-7000 Processors....................................................................................58 Overview of the Zynq-7000 Block Design and Configuration Window...............................62 Using the Programmable Logic (PL).......................................................................................80 Chapter 4: Using a MicroBlaze Processor in an Embedded Design.. 84 Creating a MicroBlaze Processor Design............................................................................... 85 UG898 (v2019.2) October 30, 2019 Send Feedback www.xilinx.com Embedded Processor Hardware Design 3 Using the MicroBlaze Configuration Window........................................................................87 Cross-Trigger Feature of MicroBlaze Processors................................................................ 112 Custom Logic........................................................................................................................... 116 Embedded IP Catalog............................................................................................................. 117 Completing Connections........................................................................................................118 Multiple MicroBlaze Processor Designs............................................................................... 125 Chapter 5: Designing with the Memory IP Core........................................133 Adding the Memory IP............................................................................................................133 Chapter 6: Reset and Clock Topologies in IP Integrator.......................144 MicroBlaze Design without a Memory IP Core....................................................................144 MicroBlaze Design with a Memory IP Core..........................................................................148 Zynq Design without PL Logic............................................................................................... 151 Zynq-7000 Design with PL Logic............................................................................................153 Zynq Design with a Memory IP Core in the PL.................................................................... 159 Designs with Memory IP and the Clocking Wizard............................................................. 161 Chapter 7: Using UpdateMEM to Update BIT files with MMI and ELF Data....................................................................................................................... 162 Using UpdateMEM.................................................................................................................. 163 Memory (MEM) Files............................................................................................................... 165 BRAM Memory Map Info (MMI) File..................................................................................... 166 Xilinx Parameterized Macros (XPM) Memories................................................................... 174 Appendix A: Additional Resources and Legal Notices........................... 180 Xilinx Resources.......................................................................................................................180 Solution Centers...................................................................................................................... 180 Documentation Navigator and Design Hubs...................................................................... 180 References................................................................................................................................181 Please Read: Important Legal Notices................................................................................. 182 UG898 (v2019.2) October 30, 2019 Send Feedback www.xilinx.com Embedded Processor Hardware Design 4 Chapter 1 Introduction This chapter provides an introduction to using the Xilinx® Vivado® Design Suite flow for programming an embedded design using the Zynq® UltraScale+™ MPSoC device, the Zynq®-7000 SoC device, or the MicroBlaze™ processor. Embedded systems are complex. Hardware and software portions of an embedded design are projects in themselves. Merging the two design components so that they function as one system creates additional challenges. Add an FPGA design project, and the situation can become very complicated. To simplify the design process, Xilinx provides several sets of tools with which you need to become acquainted. The following describes a few of the basic tool names and acronyms for these tools. The Vivado Integrated Design Environment (IDE) includes the IP integrator tool, which you can use to stitch together a processor-based design. This tool, combined with the Xilinx Vitis™ software platform, provide an integrated environment to design and debug microprocessor-based systems and embedded software applications. For an example of working with embedded processors, hardware and software cross-triggering, and debugging designs, see the Vivado Design Suite Tutorial: Embedded Processor Hardware Design (UG940). In this tutorial, you use the Vivado IP integrator tool to build embedded processor designs, and then debug the design with the Vitis software development platform and the Vivado Integrated Logic Analyzer (ILA). The following section provides an overview of the general hardware and software flow and the related information for generating an embedded design with a Xilinx processor. These sections apply to all Xilinx processor development. Device Tools Flow Overview The Vivado tools provide specific flows for programming, based on the processor. The Vivado IDE uses the IP integrator with graphic connectivity screens to specify the device, select peripherals, and configure hardware settings. UG898 (v2019.2) October 30, 2019 Send Feedback www.xilinx.com Embedded Processor Hardware Design 5 Chapter 1: Introduction You can use the Vivado IP integrator to capture hardware platform information in XML format applications,
Load more

Recommended publications
  • Open Source Synthesis and Verification Tool for Fixed-To-Floating and Floating-To-Fixed Points Conversions
    Circuits and Systems, 2016, 7, 3874-3885 http://www.scirp.org/journal/cs ISSN Online: 2153-1293 ISSN Print: 2153-1285 Open Source Synthesis and Verification Tool for Fixed-to-Floating and Floating-to-Fixed Points Conversions Semih Aslan1, Ekram Mohammad1, Azim Hassan Salamy2 1Ingram School of Engineering, Electrical Engineering Texas State University, San Marcos, Texas, USA 2School of Engineering, Electrical Engineering University of St. Thomas, St. Paul, Minnesota, USA How to cite this paper: Aslan, S., Mo- Abstract hammad, E. and Salamy, A.H. (2016) Open Source Synthesis and Verification Tool for An open source high level synthesis fixed-to-floating and floating-to-fixed conver- Fixed-to-Floating and Floating-to-Fixed Points sion tool is presented for embedded design, communication systems, and signal Conversions. Circuits and Systems, 7, 3874- processing applications. Many systems use a fixed point number system. Fixed point 3885. http://dx.doi.org/10.4236/cs.2016.711323 numbers often need to be converted to floating point numbers for higher accuracy, dynamic range, fixed-length transmission limitations or end user requirements. A Received: May 18, 2016 similar conversion system is needed to convert floating point numbers to fixed point Accepted: May 30, 2016 numbers due to the advantages that fixed point numbers offer when compared with Published: September 23, 2016 floating point number systems, such as compact hardware, reduced verification time Copyright © 2016 by authors and and design effort. The latest embedded and SoC designs use both number systems Scientific Research Publishing Inc. together to improve accuracy or reduce required hardware in the same design.
    [Show full text]
  • Xilinx Vivado Design Suite User Guide: Release Notes, Installation, And
    Vivado Design Suite User Guide Release Notes, Installation, and Licensing UG973 (v2013.3) October 23, 2013 Notice of Disclaimer The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of the Limited Warranties which can be viewed at http://www.xilinx.com/warranty.htm; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx.
    [Show full text]
  • Electronics/Computers
    Electronics/Computers Spaceborne Hybrid-FPGA System for Processing FTIR Data NASA’s Jet Propulsion Laboratory, Pasadena, California Progress has been made in a continu- vantage of the reconfigurable hardware in the software, it has been possible to re- ing effort to develop a spaceborne com- resources of the FPGAs. duce execution time to an eighth of that puter system for processing readout data The specific FPGA/embedded-proces- of a non-optimized software-only imple- from a Fourier-transform infrared sor combination selected for this effort is mentation. A concept for utilizing both (FTIR) spectrometer to reduce the vol- the Xilinx Virtex-4 FX hybrid FPGA with embedded PowerPC processors to fur- ume of data transmitted to Earth. The one of its two embedded IBM PowerPC ther reduce execution time has also been approach followed in this effort, ori- 405 processors. The effort has involved considered. ented toward reducing design time and exploration of various architectures and This work was done by Dmitriy L. Bekker, reducing the size and weight of the spec- hardware and software optimizations. By Jean-Francois L. Blavier, and Paula J. Pin- trometer electronics, has been to exploit including a dedicated floating-point unit gree of Caltech and Marcin Lukowiak and the versatility of recently developed hy- and a dot-product coprocessor in the Muhammad Shaaban of Rochester Institute brid field-programmable gate arrays hardware and utilizing optimized single- of Technology for NASA’s Jet Propulsion Lab- (FPGAs) to run diverse software on em- precision math library functions and a oratory. For more information, contact iaof- bedded processors while also taking ad- modified PowerPC performance library [email protected].
    [Show full text]
  • Vivado Design Suite User Guide: High-Level Synthesis (UG902)
    Vivado Design Suite User Guide High-Level Synthesis UG902 (v2018.3) December 20, 2018 Revision History Revision History The following table shows the revision history for this document. Section Revision Summary 12/20/2018 Version 2018.3 Schedule Viewer Updated information on the schedule viewer. Optimizing the Design Clarified information on dataflow and loops throughout section. C++ Arbitrary Precision Fixed-Point Types: Reference Added note on using header files. Information HLS Math Library Updated information on how hls_math.h is used. The HLS Math Library, Fixed-Point Math Functions Updated functions. HLS Video Library, HLS Video Functions Library Moved the HLS video library to the Xilinx GitHub (https:// github.com/Xilinx/xfopencv) HLS SQL Library, HLS SQL Library Functions Updated hls::db to hls::alg functions. System Calls Added information on using the __SYNTHESIS__ macro. Arrays Added information on array sizing behavior. Command Reference Updated commands. config_dataflow, config_rtl Added the option -disable_start_propagation Class Methods, Operators, and Data Members Added guidance on specifying data width. UG902 (v2018.3) December 20, 2018Send Feedback www.xilinx.com High-Level Synthesis 2 Table of Contents Revision History...............................................................................................................2 Chapter 1: High-Level Synthesis............................................................................ 5 High-Level Synthesis Benefits....................................................................................................5
    [Show full text]
  • Vivado Tutorial
    Lab Workbook Vivado Tutorial Vivado Tutorial Introduction This tutorial guides you through the design flow using Xilinx Vivado software to create a simple digital circuit using Verilog HDL. A typical design flow consists of creating model(s), creating user constraint file(s), creating a Vivado project, importing the created models, assigning created constraint file(s), optionally running behavioral simulation, synthesizing the design, implementing the design, generating the bitstream, and finally verifying the functionality in the hardware by downloading the generated bitstream file. You will go through the typical design flow targeting the Artix-100 based Nexys4 board. The typical design flow is shown below. The circled number indicates the corresponding step in this tutorial. Figure 1. A typical design flow Objectives After completing this tutorial, you will be able to: • Create a Vivado project sourcing HDL model(s) and targeting a specific FPGA device located on the Nexys4 board • Use the provided partially completed Xilinx Design Constraint (XDC) file to constrain some of the pin locations • Add additional constraints using the Tcl scripting feature of Vivado • Simulate the design using the XSim simulator • Synthesize and implement the design • Generate the bitstream • Configure the FPGA using the generated bitstream and verify the functionality • Go through the design flow in batch mode using the Tcl script Procedure This tutorial is broken into steps that consist of general overview statements providing information on the detailed instructions that follow. Follow these detailed instructions to progress through the tutorial. www.xilinx.com/university Nexys4 Vivado Tutorial-1 [email protected] © copyright 2013 Xilinx Vivado Tutorial Lab Workbook Design Description The design consists of some inputs directly connected to the corresponding output LEDs.
    [Show full text]
  • Xilinx Vivado Design Suite 7 Series FPGA and Zynq-7000 All Programmable Soc Libraries Guide (UG953)
    Vivado Design Suite 7 Series FPGA and Zynq-7000 All Programmable SoC Libraries Guide UG953 (v 2013.1) March 20, 2013 Notice of Disclaimer The information disclosed to you hereunder (the "Materials") is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of the Limited Warranties which can be viewed at http://www.xilinx.com/warranty.htm; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx.
    [Show full text]
  • Vivado Design Suite User Guide: Implementation
    See all versions of this document Vivado Design Suite User Guide Implementation UG904 (v2021.1) August 30, 2021 Revision History Revision History The following table shows the revision history for this document. Section Revision Summary 08/30/2021 Version 2021.1 Sweep (Default) Added more information. Incremental Implementation Controls Corrected Block Memory and DSP placement example. Using Incremental Implementation in Project Mode Corrected steps and updated image. Using report_incremental_reuse Updated Reuse Summary example and Reference Run Comparison. Physical Optimization Reports Updated to clarify that report is not cumulative. Available Logic Optimizations Added -resynth_remap. Resynth Remap Added logic optimization. opt_design Added [-resynth_remap] to opt_design Syntax. Physical Synthesis Phase Added entry for Property-Based Retiming. 02/26/2021 Version 2020.2 General Updates General release updates. 08/25/2020 Version 2020.1 Appendix A: Using Remote Hosts and Compute Clusters Updated section. UG904 (v2021.1) August 30, 2021Send Feedback www.xilinx.com Implementation 2 Table of Contents Revision History...............................................................................................................2 Chapter 1: Preparing for Implementation....................................................... 5 About the Vivado Implementation Process............................................................................. 5 Navigating Content by Design Process...................................................................................
    [Show full text]
  • Of the Securities Exchange Act of 1934
    FORM 8-K SECURITIES AND EXCHANGE COMMISSION Washington, D.C. 20549 CURRENT REPORT Pursuant to Section 13 or 15(d) of the Securities Exchange Act of 1934 Date of Report: March 10, 1994 ADVANCED MICRO DEVICES, INC. ---------------------------------------------------- (Exact name of registrant as specified in its charter) Delaware 1-7882 94-1692300 - ------------------------------ ------------ ------------------- (State or other jurisdiction (Commission (I.R.S. Employer of incorporation) File Number) Identification No.) One AMD Place P.O. Box 3453 Sunnyvale, California 94088-3453 - --------------------------------------- ---------- (Address of principal executive office) (Zip Code) Registrant's telephone number, including area code: (408) 732-2400 Item 5 Other Events - ------ ------------ I. Litigation ---------- A. Intel ----- General ------- Advanced Micro Devices, Inc. ("AMD" or "Corporation") and Intel Corporation ("Intel") are engaged in a number of legal proceedings involving AMD's x86 products. The current status of such legal proceedings are described below. An unfavorable decision in the 287, 386 or 486 microcode cases could result in a material monetary award to Intel and/or preclude AMD from continuing to produce those Am386(Registered Trademark) and Am486(Trademark) products adjudicated to contain any copyrighted Intel microcode. The Am486 products are a material part of the Company's business and profits and such an unfavorable decision could have an immediate, materially adverse impact on the financial condition and results of the operations of AMD. The AMD/Intel legal proceedings involve multiple interrelated and complex issues of fact and law. The ultimate outcome of such legal proceedings cannot presently be determined. Accordingly, no provision for any liability that may result upon an adjudication of any of the AMD/Intel legal proceedings has been made in the Corporation's financial statements.
    [Show full text]
  • 2003 - 2019 Top 200 Employers for CPT Students**
    2003 - 2019 Top 200 Employers for CPT Students** **If a student is employed at the same Employer while in a different program, he/she will be counted multiple times for that employer. Top 200 Employer Names Number of Students Participating in CPT in 2003-2019 Amazon 9,302 Intel Corporation 6,453 Microsoft Corporation 6,340 Google 6,132 IBM 4,721 Deloitte 3,870 Facebook 3,810 Qualcomm Technologies, Inc 3,371 Ernst & Young 2,929 Goldman Sachs 2,867 Cummins 2,729 JP Morgan Chase 2,474 PricewaterhouseCoopers 2,295 Bank of America 2,241 Apple, Inc 2,229 Cisco System, Inc 2,133 Disney 2,041 Morgan Stanley 1,970 World Bank 1,956 Citigroup 1,904 Merrill Lynch 1,850 KPMG 1,464 Dell, Inc 1,448 Yahoo 1,403 Motorola 1,357 Tesla, Inc 1,314 eBay or PayPal 1,268 Kelly Services 1,195 EMC Corporation 1,119 NVIDIA Corporation 1,110 Walmart 1,108 Samsung Research America 1,102 Ericsson, Inc 1,100 Adobe Systems Incorporated 1,085 PRO Unlimited 1,042 Texas Instruments 1,022 Credit Suisse 1017 Barclays 970 Randstad 942 Sony 930 Schlumberger 928 McKinsey & Company 883 2003 - 2019 Top 200 Employers for CPT Students** **If a student is employed at the same Employer while in a different program, he/she will be counted multiple times for that employer. VMWare 868 Adecco 845 Philips 829 Deutsche Bank 797 Broadcom Corporation 791 HP, Inc 789 Oracle 789 Advanced Micro Devices, Inc 782 Micron Technology, Inc 775 Boston Consulting Group 755 CVS Pharmacy 741 Robert Bosch LLC 723 Bloomberg 711 State Street 705 Hewlett-Packard 702 Alcatel-Lucent 666 Oak Ridge Institute for Science and Education 662 Genentech 657 Symantec Corporation 657 Nokia 642 Aerotek, Inc 638 Los Alamos National Laboratory 638 LinkedIn 635 Tekmark Global Solutions LLC 634 Populus Group 624 Salesforce 623 SAP America, Inc 619 Juniper Network 609 Atrium 584 The Mathworks, Inc 582 Monsanto 581 Wayfair 580 Autodesk 571 Intuit 562 Wells Fargo 559 Synopsys, Inc 546 NEC Laboratories America, Inc.
    [Show full text]
  • UG908 (V2019.2) October 30, 2019 Revision History
    See all versions of this document Vivado Design Suite User Guide Programming and Debugging UG908 (v2019.2) October 30, 2019 Revision History Revision History The following table shows the revision history for this document. Section Revision Summary 10/30/2019 Version 2019.2 General Updates Updated for Vivado 2019.2 release. 05/22/2019 Version 2019.1 Appendix E: Configuration Memory Support Replaced Configuration Memory Support Tables. Bus Plot Viewer Added new section on Bus Plot Viewer. High Bandwidth Memory (HBM) Monitor Added new section on High Bandwidth (HBM) Monitor. UG908 (v2019.2) October 30, 2019Send Feedback www.xilinx.com Vivado Programming and Debugging 2 Table of Contents Revision History...............................................................................................................2 Chapter 1: Introduction.............................................................................................. 8 Getting Started............................................................................................................................ 8 Debug Terminology.................................................................................................................... 9 Chapter 2: Vivado Lab Edition................................................................................13 Installation................................................................................................................................. 13 Using the Vivado Lab Edition .................................................................................................
    [Show full text]
  • Xilinx Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (IUG973)
    Vivado Design Suite User Guide Release Notes, Installation, and Licensing UG973 (v2013.2) June 19, 2013 Notice of Disclaimer The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of the Limited Warranties which can be viewed at http://www.xilinx.com/warranty.htm; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx.
    [Show full text]
  • Analýza Síťového Provozu Na Síťové Kartě Fpga Network Traffic Analysis on Fpga Network Card
    VYSOKÉ UČENÍ TECHNICKÉ V BRNĚ Fakulta elektrotechniky a komunikačních technologií BAKALÁŘSKÁ PRÁCE Brno, 2019 Marie Crháková VYSOKÉ UČENÍ TECHNICKÉ V BRNĚ BRNO UNIVERSITY OF TECHNOLOGY FAKULTA ELEKTROTECHNIKY A KOMUNIKAČNÍCH TECHNOLOGIÍ FACULTY OF ELECTRICAL ENGINEERING AND COMMUNICATION ÚSTAV TELEKOMUNIKACÍ DEPARTMENT OF TELECOMMUNICATIONS ANALÝZA SÍŤOVÉHO PROVOZU NA SÍŤOVÉ KARTĚ FPGA NETWORK TRAFFIC ANALYSIS ON FPGA NETWORK CARD BAKALÁŘSKÁ PRÁCE BACHELOR'S THESIS AUTOR PRÁCE Marie Crháková AUTHOR VEDOUCÍ PRÁCE Ing. David Smékal SUPERVISOR BRNO 2019 Bakalářská práce bakalářský studijní obor Teleinformatika Ústav telekomunikací Studentka: Marie Crháková ID: 152417 Ročník: 3 Akademický rok: 2018/19 NÁZEV TÉMATU: Analýza síťového provozu na síťové kartě FPGA POKYNY PRO VYPRACOVÁNÍ: Cílem bakalářské práce je navrhnout vhodné metody pro analýzu síťového provozu a následně je implementovat na síťovou kartu FPGA. Zvolený návrh odsimulujte a následně proveďte základní implementaci na hardwaru. Seznamte se s programovacím jazykem VHDL, FPGA kartami NFB, vývojovým frameworkem NDK a platformou Xilinx Vivado. DOPORUČENÁ LITERATURA: [1] WOLF, Wayne. FPGA based system design. New Jersey: Prentice-Hall, 2004, 530 s. ISBN 0-13-142461-0. [2] PINKER, Jiří, Martin POUPA. Číslicové systémy a jazyk VHDL. 1. vyd. Praha: BEN - technická literatura, 2006, 349 s. ISBN 80-7300-198-5. Termín zadání: 1.2.2019 Termín odevzdání: 27.5.2019 Vedoucí práce: Ing. David Smékal Konzultant: prof. Ing. Jiří Mišurec, CSc. předseda oborové rady UPOZORNĚNÍ: Autor bakalářské práce nesmí při vytváření bakalářské práce porušit autorská práva třetích osob, zejména nesmí zasahovat nedovoleným způsobem do cizích autorských práv osobnostních a musí si být plně vědom následků porušení ustanovení § 11 a následujících autorského zákona č. 121/2000 Sb., včetně možných trestněprávních důsledků vyplývajících z ustanovení části druhé, hlavy VI.
    [Show full text]