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Xilinx Vivado Design Suite User Guide: Release Notes, Installation, And Vivado Design Suite User Guide Release Notes, Installation, and Licensing UG973 (v2013.1) April 15, 2013 Notice of Disclaimer The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of the Limited Warranties which can be viewed at http://www.xilinx.com/warranty.htm; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in Critical Applications: http://www.xilinx.com/warranty.htm#critapps. © Copyright 2013 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. ARM® is a registered trademark of ARM in the EU and other countries. CPRI is a trademark of Siemens AG. MATLAB and Simulink are registered trademarks of The MathWorks, Inc. PCI, PCIe and PCI Express are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners. Revision History The following table shows the revision history for this document. Date Version Revision 04/15/2013 2013.1 Added details to Vivado XDC Changes in Chapter 1, and noted the use of Vivado synthesis for Xilinx IP in Compatible Third-Party Tools in Chapter 2. 03/20/2013 2013.1 Initial Xilinx release. Vivado Design Suite 2013 Release Notes www.xilinx.com 2 UG973 (v2013.1) April 15, 2013 Table of Contents Revision History . 2 Chapter 1: Release Notes 2013.1 What’s New . 5 Important Information . 12 Known Issues . 17 Chapter 2: Architecture Support and Requirements Operating Systems. 18 Architectures . 18 Compatible Third-Party Tools . 19 System Requirements . 20 Chapter 3: Download and Installation Downloading the Vivado Design Suite Tools . 23 Installing the Vivado Design Suite Tools: Overview for All Platforms . 24 Platform-Specific Installation Instructions. 25 Installation Flow. 25 USB FLEXid Dongle Driver Installation . 30 Network Installations . 31 Obtaining Quarterly Releases . 33 Uninstalling the Vivado Design Suite Tool . 34 Chapter 4: WebTalk WebTalk Participation . 35 Setting WebTalk Install Preference . 36 Setting WebTalk User Preferences . 38 Checking WebTalk Install and User Preferences . 39 Types of Data Collected. 39 Transmission of Data . 40 Chapter 5: Obtaining and Managing a License Accessing the Product Licensing Site . 41 Vivado Design Suite 2013 Release Notes www.xilinx.com 3 UG973 (v2013.1) April 15, 2013 Changing Xilinx User Account Information . 42 Product Licensing Accounts. 45 User Types and Actions . 46 Creating a License Key File . 47 Managing License Key Files . 53 Legacy Licensing . 57 Understanding Your Tool and IP Orders. 58 Managing User Access to Product Licensing Account . 59 Installing Your License Key File . 61 Appendix A: Additional Resources Xilinx Resources . 63 Solution Centers. 63 Xilinx Documentation Navigator. 63 Licenses and End User License Agreements. 64 References . 64 Vivado Design Suite 2013 Release Notes www.xilinx.com 4 UG973 (v2013.1) April 15, 2013 Chapter 1 Release Notes 2013.1 What’s New Vivado™ Design Suite 2013.1 introduces two major advances in productivity that will accelerate both time to integration and system-level design. It features the early access of the Vivado IP integrator which is the new Xilinx® intellectual property (IP) centric design environment. It also includes a comprehensive set of libraries to accelerate C/C++ system-level design and high-level synthesis (HLS) in the Vivado HLS tool. Device Support • Zynq™-7000 devices now supported ° Requires Early Access to Vivado IP integrator ° Zynq support includes 7Z100 device • The following devices are production ready ° Virtex®-7 - 7VX690T, 7VX1140T, 7VX330T, 7VX415T, 7VX980T ° Zynq-7000 - 7Z030 and 7Z045 ° Defense-Grade Kintex™-7Q - 7K325T and 7K410T ° Defense-Grade Virtex-7Q - 7V585T and 7VX485T • The following devices are General ES ready ° Virtex-7 - 7VH580T and 7VH870T Vivado Design Suite 2013 Release Notes www.xilinx.com 5 UG973 (v2013.1) April 15, 2013 What’s New New Vivado Installer Vivado Design Suite is now available separately from ISE® Design Suite. Both Vivado Design Suite and ISE Design Suite now have their own independent download and installation files. Vivado System Edition Products Vivado High-Level Synthesis The Vivado HLS tool has enhanced libraries with support for industry standard floating point math.h operations and real-time video processing functions. Users now have immediate access to video processing functions integrated into an OpenCV environment for embedded vision running on the dual-core ARM® processing system. • C libraries are enhanced with a new Video library providing support for 31 video and OpenCV Input/Output (I/O) interface functions ° OpenCV I/O functions: cvMat2hlsMat, IplImage2hlsMat, CvMat2hlsMat, hlsMat2cvMat, hlsMat2IplImage, hlsMat2CvMat ° Interfaces: hls::AXIvideo2Mat, hls::Mat2AXIvideo ° Video functions: hls::Filter2D, hls::Erode, hls::Dilate, hls::Min, hls::Max, hls::MinS, hls::MaxS, hls::Mul, hls::Zero, hls::Avg, hls::AbsDiff, hls::CmpS, hls::Cmp, hls::And, hls::Not, hls::AddS, hls::AddWeighted, hls::Mean, hls::SubRS, hls::SubS, hls::Sum, hls::Reduce, hls::Scale • Integration of designs into a software controlled environment is greatly eased with the auto-generation of standalone and Linux software driver files for packaged IP ° Supported for IP packaged for the Vivado IP catalog and the Embedded Development Kit (EDK) (pcore) environment • Support is provided for designs packaged for the Vivado IP catalog allowing them to be used in IP integrator • A new design analysis perspective allows designs to be quickly and intuitively analyzed ° Both performance and resource metrics can be reviewed in an inter-active graphical environment ° Cross-linked windows on register-transfer level (RTL) structure and scheduled operations can be cross-referenced with the C source and HDL output allowing hot-spots to be identified and optimized • The synthesis report has been enhanced to be more intuitive and provide more design level details for latency and initiation interval • Designs packaged as IP for System Generator for DSP will simulate faster Vivado Design Suite 2013 Release Notes www.xilinx.com 6 UG973 (v2013.1) April 15, 2013 What’s New ° A cycle accurate C model is now provided as part of the IP package and automatically used for simulation in System Generator for DSP • Packaging IP now generates a project file which can be directly opened in the Vivado Design Suite • Assertions on variable ranges in the C sourced code are now supported for C synthesis, enabling more optimal hardware to be created • AXI4 Master, Lite and Stream interfaces are now supported on SystemC designs • Arrays in the top-level function argument list can now be synthesized with an ap_bus I/O protocol allowing them to be implemented as an AXI4 Master interface System Generator for DSP • Support is now provided for the auto-migration of versioned IP, allowing existing designs to be quickly updated to the latest release • Faster compile and netlist generation times are realized by the auto-propagation of device and interface parameters • Faster simulation times are optionally available for IP created by the Vivado HLS tool ° The simulation can use the RTL model or optionally use a faster cycle-accurate C model of the Vivado HLS IP Vivado Design Edition Tools Interactive Design Environment • Support for bottom-up synthesis • Basic support for module analysis flow • Enhanced run “hook” scripts ° Allows customization in run flows • Find infrastructure now issues Tcl commands ° Improves search – and learning how to use Tcl • Schematic Editor combines vector instances ° Simplifies schematics for busses • Graphical User Interface (GUI) object references update to be consistent with Tcl objects • Vivado device editor ° Ability to start from either destination or source in manual routing mode Vivado Design Suite 2013 Release Notes www.xilinx.com 7 UG973 (v2013.1) April 15, 2013 What’s New •Design Rule Checks (DRC) ° New RTL and netlist linting checks •Bitstream
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