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Xilinx Vivado Design Suite 7 Series FPGA and Zynq-7000 All Programmable Soc Libraries Guide (UG953)

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Xilinx Vivado Design Suite 7 Series FPGA and Zynq-7000 All Programmable Soc Libraries Guide (UG953) Vivado Design Suite 7 Series FPGA and Zynq-7000 All Programmable SoC Libraries Guide UG953 (v 2013.1) March 20, 2013 Notice of Disclaimer The information disclosed to you hereunder (the "Materials") is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of the Limited Warranties which can be viewed at http://www.xilinx.com/warranty.htm; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in Critical Applications: http://www.xilinx.com/warranty.htm#critapps. © Copyright 2002-2013 Xilinx Inc. All rights reserved. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. Vivado Design Suite 7 Series FPGA and Zynq-7000 All Programmable SoC Libraries Guide UG953 (v 2013.1) March 20, 2013 www.xilinx.com 2 Chapter 1 Introduction Overview This HDL guide is part of the Vivado™ Design Suite documentation collection. This guide contains the following: • Introduction. • Descriptions of each available macro. • A list of design elements supported in this architecture, organized by functional categories. • Descriptions of each available primitive. About Design Elements This version of the Libraries Guide describes the valid design elements for 7 series architectures including Zynq™, and includes examples of instantiation code for each element. Instantiation templates are also supplied in a separate ZIP file, which you can find on www.xilinx.com linked to this file or within the Language Templates in the Vivado Design Suite. Design elements are divided into the following main categories: • Macros : These elements are in the UniMacro library in the tool, and are used to instantiate primitives that are complex to instantiate by just using the primitives. The synthesis tools will automatically expand the unimacros to their underlying primitives. • Primitives: Xilinx components that are native to the architecture you are targeting. Vivado Design Suite 7 Series FPGA and Zynq-7000 All Programmable SoC Libraries Guide UG953 (v 2013.1) March 20, 2013 www.xilinx.com 3 Introduction Design Entry Methods For each design element in this guide, Xilinx evaluates four options for using the design element, and recommends what we believe is the best solution for you. The four options are: • Instantiation: This component can be instantiated directly into the design. This method is useful if you want to control the exact use, implementation, or placement of the individual blocks. • Inference: This component can be inferred by most supported synthesis tools. You should use this method if you want to have complete flexibility and portability of the code to multiple architectures. Inference also gives the tools the ability to optimize for performance, area, or power, as specified by the user to the synthesis tool. • IP Catalog: This component can be instantiated from the IP Catalog. The IP Catalog maintains a library of IP Cores assembled from multiple primitives to form more complex functions, as well as interfaces to help in instantiation of the more complex primitives. References here to the IP Catalog generally refer to the latter, where you use the IP catalog to assist in the use and integration of certain primitives into your design. • Macro Support: This component has a UniMacro that can be used. These components are in the UniMacro library in the Xilinx tool, and are used to instantiate primitives that are too complex to instantiate by just using the primitives. The synthesis tools will automatically expand UniMacros to their underlying primitives. Vivado Design Suite 7 Series FPGA and Zynq-7000 All Programmable SoC Libraries Guide UG953 (v 2013.1) March 20, 2013 www.xilinx.com 4 Chapter 2 Unimacros Overview This section describes the unimacros that can be used with 7 series FPGAs and Zynq™-7000 All Programmable SoC devices. The unimacros are organized alphabetically. The following information is provided for each unimacro, where applicable: • Name of element • Brief description • Schematic symbol • Logic table (if any) • Port descriptions • Design Entry Method • Available attributes • Example instantiation code • For more information Vivado Design Suite 7 Series FPGA and Zynq-7000 All Programmable SoC Libraries Guide UG953 (v 2013.1) March 20, 2013 www.xilinx.com 5 Unimacros BRAM_SDP_MACRO Macro: Simple Dual Port RAM Introduction 7 series FPGA devices contain several block RAM memories that can be configured as general-purpose 36Kb or 18Kb RAM/ROM memories. These block RAM memories offer fast and flexible storage of large amounts of on-chip data. Both read and write operations are fully synchronous to the supplied clock(s) of the component. However, READ and WRITE ports can operate fully independently and asynchronously to each other, accessing the same memory array. Byte-enable write operations are possible, and an optional output register can be used to reduce the clock-to-out times of the RAM. Note This element must be configured so that read and write ports have the same width. Vivado Design Suite 7 Series FPGA and Zynq-7000 All Programmable SoC Libraries Guide UG953 (v 2013.1) March 20, 2013 www.xilinx.com 6 Unimacros Port Description Name Direction Width (Bits) Function DO Output See Configuration Table Data output bus addressed by RDADDR. DI Input See Configuration Table Data input bus addressed by WRADDR. WRADDR, Input See Configuration Table Write/Read address input buses. RDADDR WE Input See Configuration Table Byte-Wide Write enable. WREN, Input 1 Write/Read enable RDEN SSR Input 1 Output registers synchronous reset. REGCE Input 1 Output register clock enable input (valid only when DO_REG=1). WRCLK, Input 1 Write/Read clock input. RDCLK Port Configuration This unimacro is a parameterizable version of the primitive, and can be instantiated only. Use this table to correctly configure the unimacro to meet design needs. DATA_WIDTH BRAM_SIZE ADDR WE 72 - 37 36Kb 9 8 36 - 19 36Kb 10 4 18Kb 9 18 - 10 36Kb 11 2 18Kb 10 9 - 5 36Kb 12 1 18Kb 11 4 - 3 36Kb 13 1 18Kb 12 2 36Kb 14 1 18Kb 13 1 36Kb 15 1 18Kb 14 Vivado Design Suite 7 Series FPGA and Zynq-7000 All Programmable SoC Libraries Guide UG953 (v 2013.1) March 20, 2013 www.xilinx.com 7 Unimacros Design Entry Method This unimacro is a parameterizable version of the primitive, and can be instantiated only. Consult the Port Configuration section to correctly configure this element to meet your design needs. Instantiation Yes Inference No IP Catalog No Macro support Recommended Available Attributes Attribute Data Type Allowed Values Default Description BRAM_SIZE String "36Kb", "18Kb" "18Kb" Configures RAM as "36Kb" or "18Kb" memory. DEVICE String "7SERIES" "7SERIES" Target hardware architecture. DO_REG Integer 0, 1 0 A value of 1 enables to the output registers to the RAM enabling quicker clock-to-out from the RAM at the expense of an added clock cycle of read latency. A value of 0 allows a read in one clock cycle but will have slower clock to out timing. INIT Hexadecimal Any 72-Bit Value All zeros Specifies the initial value on the output after configuration. READ_WIDTH, Integer 1-72 36 Specifies the size of the DI and WRITE_WIDTH DO buses. The following combinations are allowed: • READ_WIDTH = WRITE_WIDTH • If asymmetric, READ_WIDTH and WRITE_WIDTH must be in the ratio of 2, or must be values allowed by the unisim (1, 2, 4, 8, 9, 16, 18, 32, 36, 64, 72) INIT_FILE String String NONE Name of the file containing initial representing values. file name and location. Vivado Design Suite 7 Series FPGA and Zynq-7000 All Programmable SoC Libraries Guide UG953 (v 2013.1) March 20, 2013 www.xilinx.com 8 Unimacros Attribute Data Type Allowed Values Default Description SIM_COLLISION_ String "ALL", "ALL" Allows modification of the CHECK "WARNING_ simulation behavior if a memory ONLY", collision occurs. The output is "GENERATE_X_ affected as follows: ONLY", "NONE" • "ALL" - Warning produced and affected outputs/memory location go unknown (X). • "WARNING_ONLY" - Warning produced and affected outputs/memory retain last value. • "GENERATE_X_ONLY" - No warning. However, affected outputs/memory go unknown (X). • "NONE" - No warning and affected outputs/memory retain last value. Note Setting this to a value other than "ALL" can allow problems in the design go unnoticed during simulation. Care should be taken when changing the value of this attribute.
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