Electronics/Computers

Spaceborne Hybrid-FPGA System for Processing FTIR Data NASA’s Jet Propulsion Laboratory, Pasadena, California Progress has been made in a continu- vantage of the reconfigurable hardware in the software, it has been possible to re- ing effort to develop a spaceborne com- resources of the FPGAs. duce execution time to an eighth of that puter system for processing readout data The specific FPGA/embedded-proces- of a non-optimized software-only imple- from a Fourier-transform infrared sor combination selected for this effort is mentation. A concept for utilizing both (FTIR) spectrometer to reduce the vol- the Xilinx Virtex-4 FX hybrid FPGA with embedded PowerPC processors to fur- ume of data transmitted to Earth. The one of its two embedded IBM PowerPC ther reduce execution time has also been approach followed in this effort, ori- 405 processors. The effort has involved considered. ented toward reducing design time and exploration of various architectures and This work was done by Dmitriy L. Bekker, reducing the size and weight of the spec- hardware and software optimizations. By Jean-Francois L. Blavier, and Paula J. Pin- trometer electronics, has been to exploit including a dedicated floating-point unit gree of Caltech and Marcin Lukowiak and the versatility of recently developed hy- and a dot-product coprocessor in the Muhammad Shaaban of Rochester Institute brid field-programmable gate arrays hardware and utilizing optimized single- of Technology for NASA’s Jet Propulsion Lab- (FPGAs) to run diverse software on em- precision math library functions and a oratory. For more information, contact iaof- bedded processors while also taking ad- modified PowerPC performance library [email protected]. NPO-45957

FPGA Coprocessor for Accelerated Classification of Images NASA’s Jet Propulsion Laboratory, Pasadena, California An effort related to that described in phenomena such as flooding, volcanic that translates C-language programs into the preceding article focuses on develop- eruptions, and sea-ice break-up. The hardware description language (HDL) ing a spaceborne processing platform for FPGA provides hardware acceleration for files, the legacy C-language program, fast and accurate onboard classification increased onboard processing capability and two newly formulated programs for of image data, a critical part of modern than previously demonstrated in software. a more capable expanded-linear-kernel satellite image processing. The approach The original C-language program — and a more accurate polynomial-kernel again has been to exploit the versatility of demonstrated on an imaging instrument SVM algorithm, have been implemented recently developed hybrid Virtex-4FX aboard the Earth Observing-1 (EO-1) in the Virtex-4FX FPGA. In tests, the field-programmable gate array (FPGA) to satellite — implements a linear-kernel FPGA implementations have exhibited run diverse science applications on em- SVM algorithm for classifying parts of significant speedups over conventional bedded processors while taking advan- the images as snow, water, ice, land, or software implementations running on tage of the reconfigurable hardware re- cloud or unclassified. Current onboard general-purpose hardware. sources of the FPGAs. In this case, the processors, such as on EO-1, have lim- This work was done by Paula J. Pingree, FPGA serves as a coprocessor that imple- ited computing power, extremely lim- Lucas J. Scharenbroich, and Thomas A. ments legacy C-language support-vector- ited active storage capability and are no Werne of Caltech for NASA’s Jet Propulsion machine (SVM) image-classification algo- longer considered state-of-the-art. Laboratory. For more information, contact rithms to detect and identify natural Using commercially available software [email protected]. NPO-45961

SiC JFET Transistor Circuit Model for Extreme Temperature Range Simple modifications of common silicon model provide reasonable approximation from 25 to 500 °C. John H. Glenn Research Center, Cleveland, Ohio

A technique for simulating extreme- with Integrated Circuit Emphasis source code enable SiC JFETs to be sim- temperature operation of integrated cir- (SPICE) general-purpose analog-inte- ulated to 500 °C using the well-known cuits that incorporate silicon carbide grated-circuit-simulating software. “Level 1” model for silicon metal oxide (SiC) junction field-effect transistors NGSPICE in its unmodified form is used semiconductor field-effect transistors (JFETs) has been developed. The tech- for simulating and designing circuits (MOSFETs). First, the default value of nique involves modification of made from silicon-based transistors that the MOSFET surface potential must be NGSPICE, which is an open-source ver- operate at or near room temperature. changed. In the unmodified source sion of the popular Simulation Program Two rapid modifications of NGSPICE code, this parameter has a value of 0.6,

NASA Tech Briefs, December 2008 9 which corresponds to slightly more than perimental SiC JFETs, a T–1.3 tempera- sary to model experimental SiC JFET half the bandgap of silicon. In NGSPICE ture dependence must be implemented current-voltage performance across the modified to simulate SiC JFETs, this pa- in the NGSPICE source code. entire temperature range from 25 to rameter is changed to a value of 1.6, cor- Following these two simple modifica- 500 °C. responding to slightly more than half tions, the “Level 1” MOSFET model of This work was done by Philip G. Neudeck the bandgap of SiC. The second modifi- the NGSPICE circuit simulation pro- of Glenn Research Center. Further informa- cation consists of changing the tempera- gram reasonably approximates the tion is contained in a TSP (see page 1). ture dependence of MOSFET transcon- measured high-temperature behavior of Inquiries concerning rights for the commer- ductance and saturation parameters. experimental SiC JFETs properly oper- cial use of this invention should be addressed The unmodified NGSPICE source code ated with zero or reverse bias applied to to NASA Glenn Research Center, Innovative implements a T–1.5 temperature depend- the gate terminal. Modification of addi- Partnerships Office, Attn: Steve Fedor, Mail ence for these parameters. In order to tional silicon parameters in the Stop 4–8, 21000 Brookpark Road, Cleve- mimic the temperature behavior of ex- NGSPICE source code was not neces- land, Ohio 44135. Refer to LEW-18342-1.

TDR Using Autocorrelation and Varying-Duration Pulses Signal-to-noise ratios may be increased. John F. Kennedy Space Center, Florida

In an alternative to a prior technique edge of an excitation pulse generates a can be used as a means of identifying a of time-domain-reflectometry (TDR) in reflection from a defect, so that a unique leading-edge/trailing-edge reflection pair. which very short excitation pulses are pair of reflections is associated with each For a given spatial interval, measure- used, the pulses have very short rise and defect. In the present alternative tech- ments are made and R(τ) computed, as fall times and the pulse duration is var- nique, the processing of the measured described above, for pulse durations T ied continuously between a minimum reflection signal includes computation ranging from the minimum to the maxi- and a maximum value. In both the pres- of the autocorrelation function mum value. The advantage of doing this ent and prior techniques, the basic idea R(τ)≡∫x(t)x(t – τ)dt is that the effective signal-to-noise ratio is to (1) measure the times between the where t is time, x(t) is the measured reflec- may be significantly increased over that generation of excitation pulses and the tion signal at time t, and τ is the correla- attainable by use of a fixed pulse dura- reception of reflections of the pulses as tion interval. The integration is per- tion T. indications of the locations of one or formed over a measurement time interval This work was done by Angel Lucena, Pam more defects along a cable and (2) short enough to enable identification and Mullinex, PoTien Huang, and Josephine Santi- measure the amplitudes of the reflec- location of a defect within the correspon- ago of Kennedy Space Center and Pedro Medelius, tions as indication of the magnitudes of ding spatial interval along the cable. Typi- Carlos Mata, Carlos Zavala, and John Lane of the defects. cally, where there is a defect, R(τ) exhibits ASRC Aerospace Corp. Further information is In general, an excitation pulse has a a negative peak having maximum magni- contained in a TSP (see page 1). duration T. Each leading and trailing tude for τ in the vicinity of T. This peak KSC-12856

Update on Development of SiC Multi-Chip Power Modules Modules and a modular power system have been built and tested. John H. Glenn Research Center, Cleveland, Ohio

Progress has been made in a continuing (SOI) control integrated-circuit chips. tem can be electrically connected in se- effort to develop multi-chip power mod- SiC MCPMs are being developed as build- ries, parallel, or a series/parallel combi- ules (SiC MCPMs). This effort at an earlier ing blocks of advanced expandable, re- nation to increase the overall power- stage was reported in “SiC Multi-Chip configurable, fault-tolerant power-supply handling capability of the system. In Power Modules as Power-System Building systems. Exploiting the ability of SiC semi- addition to power connections, the Blocks” (LEW-18008-1), NASA Tech Briefs, conductor devices to operate at tempera- modules have communication connec- Vol. 31, No. 2 (February 2007), page 28. tures, breakdown voltages, and current tions. The SOI controllers in the mod- The following unavoidably lengthy reca- densities significantly greater than those ules communicate with each other as pitulation of information from the cited of conventional Si devices, the designs of nodes of a decentralized control net- prior article is prerequisite to a meaningful SiC MCPMs and of systems comprising work, in which no single controller ex- summary of the progress made since then: multiple SiC MCPMs are expected to af- erts overall command of the system. • SiC MCPMs are, more specifically, elec- ford a greater degree of miniaturization Control functions effected via the net- tronic power-supply modules containing through stacking of modules with re- work include synchronization of switch- multiple silicon carbide power integrated- duced requirements for heat sinking. ing of power devices and rapid recon- circuit chips and silicon-on-insulator • The stacked SiC MCPMs in a given sys- figuration of power connections to

10 NASA Tech Briefs, December 2008