Section 3 ASIC Industry Trends

3 ASIC INDUSTRY TRENDS

INTRODUCTION

The term ASIC (Application Specific IC) has been a misnomer from the very beginning. ASICs, as now known in the IC industry, are really customer specific ICs. In other words, the gate array or standard cell device is specifically made for one customer. ASIC, if taken literally, would mean the device is created for one particular type of system (e.g., a disk-drive), even if this device is sold to numerous customers and/or is put in the IC manufacturerÕs catalog.

Currently, a device type that is sold to more than one user, even if it is produced using ASIC technology, is considered a standard IC. Thus, we are left with the following nomenclature guidelines (Figure 3-1).

ASIC: A device produced for only one customer. PLDs are included as ASICs because the customer “programs” that device for its needs only.

CSIC: What ASICs should have been called from the beginning. Some companies differentiate an ASIC from a CSIC by who completes or is responsible for the majority of the IC design effort. If it is the IC producer, the part is labeled a CSIC, if it is the end-user, the device is called an ASIC. This term is not currently used very often in the IC industry.

ASSP: A relatively new term for ICs targeting specific types of systems. In many cases the IC will be manufactured using ASIC technology (e.g., gate or linear array or standard cell techniques) but will ultimately be sold as a standard device type to numerous users (i.e., put into a product catolog). If the end-user helped the IC producer design the ASSP, that user is typically given a market leadtime (i.e., window of opportunity) to use the device before it is made available to its competitors.

CSP: Customizable Standard Products are 70 to 90 percent standard with 10 to 30 percent of the chip available for user-specified logic, memory, or peripheral functions. A CSP can be an ASIC device if it is sold to only one customer.

Source: ICE, "Status 1997" 19181B

Figure 3-1. ASIC Industry Terminology

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One problem many IC producers have run into while producing ASSPs is that in order to provide the optimum part, the IC producer must understand the system application at least as well as the end-user. Because this system-level expertise is not easy to acquire, most ASSP vendors have formed close relationships or partnerships with end-users. In this way, the IC vendor and end-user work closely together early in the system design cycle in order to properly define the ASSP device.

In general, as standard ICs take aim at ever finer segments of the marketplace, they ultimately evolve into ASSPs. In other words, at some point in time there could be very few standard ICs; most devices produced would be aimed at specific system needs. An example would be certain DRAMs architecturally optimized for a hand-held telecom system, laptop PC, or HDTV set. This is precisely the direction the IC industry is heading.

As IC producers customize their devices for specific system needs, the list of ICs labeled as ASSPs continues to expand. In 1996, VLSI Technology introduced a two-chip ASSP product based upon the ARM6 RISC 32-bit MPU core (Figure 3-2). The GSM communications chips are produced using VLSIÕs 0.6µm CMOS cell-based technology. It doesnÕt take too much imagination to visual- ize a one-chip ASSP solution sometime in the near future. As was mentioned earlier, 20 years from now there may be few ÒstandardÓ ICs produced.

Layers 2 and 3 GSM Protocol Layer 1 Software

VP22002 GSM Kernel VP22020 GSM Vocoder Adaptive Channel Speech Radio A/D D/A Speaker Equalizer Decoder Decoder

Rx Decrypt

Comfort Control VAD Noise µcontroller Synthesis Timer Speech A/D Microphone Encoder

Channel Display Echo Tx Coder D/A GMSK Canceller Decrypt Keyboard Speech Smart Card Recognition

Source: VLSI Technology/ICE, "Status 1997" 21033

Figure 3-2. A Two-Chip GSM ASSP Chip-Set From VLSI Technology

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In mid-1995, Motorola introduced the concept of the CSP (Figure 3-3). As was shown in Figure 3- 1, the CSP product allows a small portion of user-specific logic to be introduced into a standard product design. The customized logic can be CFBÕs (complex function blocks; e.g., an ATM cell processor) or other circuitry from MotorolaÕs standard cell or gate array libraries.

ASSP Application MC92xxx Specific Standard CFB Product CSP Customizable Platform Diffused Memory Customizable Architectures Standard Standard Product User-Specific Logic

CFB-Library CFBs- CSP Elements Application Customizable Driven Standard USL Product

Source: Integrated System Design/Motorola/ICE, "Status 1997" 21034

Figure 3-3. MotorolaÕs CSP Design Flow

Basically, an ASSPÕs circuitry is entirely designed by the IC producer. A CSP device always contains some of the end usersÕ unique circuit design or circuit interconnection.

A CSP is usually classified as an ASIC device because it is sold only to the customer that defined the unique circuitry portion of the chip. Moreover, like an ASIC device, MotorolaÕs CSP program has NREÕs (starting at $100K) and design cycle times that are typically about 90 days.

Although the 1996 ASIC market was about $17 billion, the ASSP-type products (which are part of the special purpose MOS Logic category) are taking away some of its momentum (Figure 3-4). Overall, the ASIC market (not including full custom) is forecast to follow total IC industry growth rates fairly closely.

Does the proliferation of ASSPs and more customer-specific standard products mean an end to the ASIC market? No. This is because most of the pros and cons of ASICs versus ASSPs or standard products still exist.

The primary advantage of ASSPs or standard products is the ability to immediately (most of the time) purchase the ICs and get the system to market quickly. However, ASIC devices allow the system producer to differentiate its product from the competition. The result is that many times the system producer is able to gain marketshare and/or better profit margins.

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8 7.39 Ð13% 7 24% 6.47 5.98 6 26%

5 4.74 26% 4 3.75

3 Billions of Dollars

0 1992 1993 1994 1995 1996 Year (EST) Source: ICE, "Status 1997" 20204C

Figure 3-4. Special Purpose MOS Logic Market (1992-1996)

In some cases standard products and ASICs are merging in an attempt to offer the benefits of both approaches. In 1993, TI announced that it was merging an enhanced version of its standard fixed- point TMS320C25 DSP chip and 15,000 usable and customizable 0.8-micron CMOS gate-array gates on one device. Thus, the user is able to take advantage of well characterized high-performance DSP circuitry while at the same time adding unique features to give its system a differential advantage over its competitors. It is estimated that about 35 percent of TIÕs total DSP IC sales in 1996 were in a customizable version. This percentage is expected to rise to over 50 percent in 2001.

Another gray area is where Cirrus Logic takes one of its ASSP ICs and customizes a portion of it for one of its customers. Typically only about 5-10 percent of the new design is customized for the end-user. This ÒtweakedÓ device is still normally classified as an ASSP since the majority of the circuitry is still ASSP-based.

There is no question that the IC industry will continue to evolve toward devices that are specifically suited for the customersÕ needs. ICE believes that various versions of ASICs (e.g., CSPs) and ASSPs will co-exist to help serve those needs in the most economical and efficient manner possible.

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ASIC Definitions

Some basic definitions and classifications are shown below in order to define what ICE means when using the various terms used to describe todayÕs ASIC devices. ASIC stands for Application Specific Integrated Circuit and according to ICEÕs definition includes gate arrays, standard cells (sometimes called cell-based), full custom, and programmable logic devices (PLDs). These devices are classified as either semicustom, custom, or PLDs. Formal definitions are given in Figure 3-5.

ICE does not include ASSPs in its ASIC market figures. An example of an ASSP part that is not classified as an ASIC by ICE is HitachiÕs H8/300H Series of microcontrollers. Although the H8/300H user is able to customize this MCU using an extensive Hitachi cell library, the finished devices are almost always allowed to be sold to other Hitachi customers after a certain period of time (Motorola has a similar program using its 68HC05 MCUs).

Motorola also has its ÒFlexCoreÓ program that allows the end-user to use its 32-bit MPUs as cores in cell-based designs. This program is significantly different from its, and HitachiÕs, MCU ASSP offerings in that the finished devices will most likely stay proprietary to the original customer. Thus, these devices are considered to be standard cell ASICs.

The FlexCore- and CSP-type ASIC programs* are prime examples of why ASSPs will not eliminate the market for ASICs. As was mentioned earlier, ASSPs will still hold an advantage in time-to- market, but they will never be able to compete with the product differentiation capability of robust ASIC offerings such as FlexCore and CSP.

Another ASIC segment that needs additional clarification and discussion is the PLD category. ICE includes under the generic term PLD the simple bipolar fuse-programmable PAL devices (e.g., the 22V10) produced by AMD and TI, the complex programmable (CPLD) devices (that typically have configurable macrocells, multiple feedback paths, etc.) that are usually MOS memory cell-based, and what are called field programmable gate arrays (FPGAs).

The FPGAs are produced using MOS memory cell (and thus are usually reprogrammable) or antifuse technology. The physical (e.g., line lengths) and electrical characteristics of the interconnects are unknown before programming, just like a gate array.

As was shown, the PLD classification now encompasses a broad range of products and most people in the IC industry are aware that the term PLD is no longer synonymous with the obsolete bipolar fuse-programmable PAL.

* Zilog has a similar program for its Z80 MCU devices.

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I. ASIC Semicustom IC - A monolithic circuit that has one or more customized mask layers, but does not have all mask layers customized, and is sold to only one customer.

Gate Array - A monolithic IC usually composed of columns and rows of transistors (organized in blocks of gates). One or more layers of metal interconnect are used to customize the chip. Sometimes called an uncommitted logic array (ULA).

Linear Array - An array of transistors and resistors that performs the functions of several linear ICs and discrete devices.

II. ASIC Custom IC - A monolithic circuit that is customized on all mask layers and is sold to only one customer. "System-on-a-chip" devices are typically custom ICs.

Standard Cell IC - A monolithic IC that is customized on all mask levels using a cell library that embodies pre-characterized circuit structures. ICs that are designed with a silicon compiler are included in this category. Most "embedded" arrays are included in this category because all mask layers are customized.

Full Custom IC - A monolithic IC that is at least partially "handcrafted". Handcrafting refers to custom layout and connection work that is accomplished without the aid of a silicon compiler or standard cells.

III. ASIC Programmable Logic Device (PLD) - A monolithic circuit with fuse, antifuse, or memory cell-based circuitry that may be programmed (customized), and in some cases, reprogrammed by the user (in-system or prototype form).

Simple PLD (SPLD) - Usually a PAL or PLA, typically contains less than 750 logic gates.

Complex PLD (CPLD) - A hierarchical arrangement of multiple PAL-like blocks.

Field Programmable Gate Array (FPGA) - A PLD that offers fully flexible interconnects, fully flexible logic arrays, and requires functional placement and routing.

Electrically Programmable Analog Circuit (EPAC) - A PLD that allows the user to program and reprogram basic analog functions.

IV. ASSP - A relatively new term for ICs targeting specific types of systems. In many cases the IC will be manufactured using ASIC technology (e.g., gate or linear array or standard cell techniques) but will ultimately be sold as a standard type to numerous users (i.e., put into a product catalog). If the end-user helped the IC producer design the ASSP, that user is typically given a market leadtime (i.e., window of opportunity) to use the device before it is made available to its competitors. Source: ICE, "Status 1997" 13660H

Figure 3-5. ASIC/ASSP Definitions

3-6 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Industry Trends

Another definitional clarification that should be mentioned is in the standard cell category. Many of the standard cell designs produced in the ASIC industry use a combination of pre-characterized and ÒhandcraftedÓ circuit structures. ICE categorizes an ASIC that has 50 percent or more of its circuitry composed of cells as a standard cell IC. If less than 50 percent of the circuitry is from pre- characterized cells (with the majority of the design being handcrafted), the IC is considered a full custom ASIC.

Another device that deserves some further discussion is the embedded array ASIC. When design- ing with this device, the customer first identifies any megacell functions that will be needed. The ASIC producer optimizes the layout of the cell-based design and then begins producing base wafers. While the base wafers are being fabricated, the customer is finishing design work for the uncommitted random logic area (gate array portion) that was set aside in the initial design. After the base wafer is finished being processed, the gate array area of the base wafer is metallized.

The ultimate goal of the parallel random logic design and cell-based wafer fabrication efforts of the embedded array program is to shorten the turnaround time encountered with standard cell devices. Many embedded array producers are achieving turnaround times very close to those of gate arrays.

Although both standard cell and gate array design and fabrication techniques are used on the embedded array, because all of the mask layers of the device are customized for the user, ICE will classify the embedded array ASICs (e.g., VLSI TechnologyÕs Flex-Arrays) as standard cells.

Throughout ÒStatus 1997Ó ICE uses terms such as available, total, raw, and usable when referring to gate densities. Figure 3-6 shows the definitions followed by ICE in regard to gate count. Typical usable gate counts for various ASICs are shown in Figure 3-7.

AVAILABLE, TOTAL OR RAW GATES The number of unconnected gates on a device.

USABLE OR WIREABLE GATES The number of gates that can typically be interconnected implementing an "average" design. Usable gate count will always be less than the number of available, total, or raw gates.

Source: ICE, "Status 1997" 16779A

Figure 3-6. Gate Count Definitions

As total gate densities have increased, the IC manufacturer has had to go to a greater number of interconnect levels (i.e., metal layers) to keep die size and usable gate count percentages reasonable. This has been especially evident with the new triple-level metal PLDs. The new PLD technologies are helping reduce PLD die size dramatically, and in turn, significantly reduce manufacturing costs.

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Usable Gate ASIC Type Percentage

Double-Level Metal MOS PLD 30 - 50

Triple-Level Metal MOS PLD 60 - 70

Double-Level Metal Channelled Gate Array 85 - 95

Double-Level Metal Channelless Gate Array 40 - 50

Triple-Level Metal Channelless Gate Array 60 - 70

Four-Layer Metal Channelless Gate Array 40 - 60*

Five-Layer Metal Channelless Gate Array 60 - 70*

Standard Cell 85 - 95

Full Custom 100

*For devices with more than one million total gates

Source: ICE, "Status 1997" 16780C

Figure 3-7. Sampling of Usable Gate Counts

Of course the move to a greater number of metal layers comes with cost and complexity problems. With an increasing number of ASIC designs being pad limited (i.e., the die size is dictated by the number of I/O pads rather than the logic gate area) the move to more layers of metal has pro- ceeded very slowly in the ASIC user base.

ASIC PRODUCT LIFECYCLE

Figure 3-8 shows the 1996 location of each of the major ASIC families on the product lifecycle curve. It is interesting to note that most of the classifications still reside on the growth side of the curve. As the ASIC market matures, the majority of the ASIC product types will be in or approaching the maturity stage of their lifecycles in the late 1990Õs.

Low density (i.e., less than 10,000 gates) gate arrays are considered to be in the saturation/decline stage. In 1995 and 1996, many gate array vendors were shying away from accepting designs for low gate count arrays. As veteran IC buyers know, once products enter the latter stages of the lifecycle, price becomes a secondary concern to availability. Likewise, bipolar TTL PALs are quickly losing marketshare and are now entirely in the decline stage. As shown, replacement products for the bipolar TTL PAL and low-density gate array, such as MOS PLDs, are currently in the introduction or growth/maturity stage.

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Introduction Growth Maturity Saturation Decline and Obsolescence

PLD W/Memory Bipolar PLDs EPLD EPAC EEPLD Flash-PLD SRAM-PLD Antifuse PLD Full CMOS Gate Array CMOS Gate Array Custom (≥500,000 Gates) (≥100,000 and <500,000 Gates) CMOS Gate Array (≥20,000 and <100,000 Gates) Mixed CMOS Gate Array Analog/Digital (≥10,000 and <20,000 Standard Cell Gates) Digital CMOS Gate Array Standard Cell (<10,000 Gates) ECL Gate Array Embedded (≥20,000 Gates) Arrays ECL Gate Array (≥5,000 and <20,000 Gates) GaAs Gate Array ECL Gate Array BiCMOS Analog (<5,000 Gates) Gate Array Arrays GaAs Standard Cell Mixed Analog Digital Arrays

Source: ICE, "Status 1997" 11642S

Figure 3-8. 1996 ASIC Products Lifecycle

THE LOGIC MARKET

Similar to the total IC marketplace, the use of MOS logic (including ASICs) has increased significantly in the computer and communications segments (Figure 3-9). ICE believes that this trend will continue for the rest of the decade as Òsystem-on-a-chipÓ standard cell devices become more prevalent in the ASIC industry.

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Auto Military Auto Military 4% 3% Industrial 3% 1% Industrial 9% 9%

Communications 21% Computer Consumer Computer 1991 34% 1996 (EST) 40% $10.0B 22% $22.2B

Consumer Communication 29% 25%

Source: WSTS/ICE, "Status 1997" 21718

Figure 3-9. MOS Logic Usage by System Type

An analysis of the logic market provides a good background to the study of the ASIC market since a vast majority of ASIC products perform some basic logic function within a system. Figure 3-10 shows the logic trends by technology. The most obvious trend shown on the graph is the tremendous growth of CMOS logic. In the time span shown, CMOS technology has grown from a minor- ity process to the dominant process used in making logic devices.

100

90 23%

70 18% 55% 88%* CMOS 60 NMOS 91%* 8% 50 93%* 51% ECL 40 10%

30 8% Percent of Total Logic Market 4% 20 27% TTL and Other Bipolar 2% 10 6% 4% <1% BiCMOS <1% 3% 5% 0 3% <1% 1982 1987 1996 2001 $3.3B $11.6B $24.0B $54.1B (EST) (FCST) 1997 $26.7B *Includes 1% for GaAs (FCST) Source: ICE, "Status 1997" 12875Q

Figure 3-10. Logic Market Trends By Technology

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On the other hand, older technologies such as NMOS and bipolar have been phased out. Also, ECL technology, after maintaining about eight percent of the logic marketshare for several years, is forecast to account for a very small percentage of the logic market by the year 2001. Many of the excellent performance characteristics of ECL and other older technologies have been replicated in CMOS and BiCMOS technologies in recent years. These two technologies will dominate not only the logic market, but all digital IC production in the foreseeable future.

Displayed in Figure 3-11 is the average selling price (ASP) for logic devices during the past several years. The TTL SSI/MSI segment of logic devices has remained essentially flat since the late- 1980Õs. Meanwhile, MOS logic ASPs swelled in the mid-1980Õs, stayed flat for several years, then took off again beginning in 1994 due to increased sophistication and greater implementation of logic products in systems. The declining ASPs for the total logic market in 1996 reflected the inventory adjustment that was occurring at system houses throughout most of the year.

2.0

1.8 TTL SSI/MSI MOS Logic 1.6 Total Logic

1.4

1.2

1.0 ASP ($)

0.8

0.6

0.4

0.2

0.0 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 Year (EST)

Source: WSTS/ICE, "Status 1997" 20197C

Figure 3-11. Average Selling Price for Logic Devices

As shown in Figure 3-12, ASICs are typically high ASP devices. Considering that the total IC ASP in 1996 was $2.40, the overall ASIC ASP was over three times as much at $8.33.

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10.00 10.00 9.55

9.00 8.70 8.00 8.00

7.00

6.00 5.25 5.00 5.00 ASP ($) 4.00

3.00

2.00 1.77

1.00

0 Bipolar Linear MOS MOS Bipolar MOS Full PLD Arrays PLD Gate Array* Gate Array Std. Cell* Custom* and Std. Cell*

* Not including NRE charges ASIC Product Category Source: ICE, "Status 1997" 21742

Figure 3-12. 1996 ASIC ASPs

Unit volumes for ASIC devices shipped in 1996 are shown in Figure 3-13. While the ASIC marketplace in dollars represents 15 percent of the total IC industry, ASIC unit volume shipments (1.8 billion units) were only about four percent of the total 49 billion IC units sold in 1996.

Bipolar ASIC and Linear Arrays 4% Full Custom 14%

MOS Gate Array 34% 1.8B MOS PLD Units 19% MOS Standard Cell 29%

Source: ICE, "Status 1997" 21741

Figure 3-13. Estimated 1996 ASIC Unit Volume Shipments

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ASIC MARKET FORECAST

ICE segments the ASIC market into three areasÑsemicustom (MOS and bipolar gate arrays and linear arrays), custom (MOS and bipolar cell-based and full custom devices), and programmable logic devices (including FPGAs).

Recent ASIC market history is shown in Figure 3-14. ICE believes that in 1997, the ASIC market will grow 12 percent (Figure 3-15). The catalyst for ASIC growth will be strong PLD and MOS standard cell sales. In fact, 1996 was the first year MOS standard cell sales surpassed MOS gate array revenues. Figure 3-16 shows that the actual crossover occurred in late summer of 1996.

1992/1991 1993/1992 1994/1993 1995/1994 1991 1992 1993 1994 1995 1991-1995 Segment Percent Percent Percent Percent ($M) ($M) ($M) ($M) ($M) CAGR (%) Change Change Change Change MOS Gate Arrays 2,845 2% 2,915 22% 3,555 26% 4,480 23% 5,510 18% Bipolar Gate Arrays 1,000 Ð10% 905 Ð13% 790 Ð20% 635 2% 650 Ð10% Total Gate Arrays 3,845 Ð1% 3,820 14% 4,345 18% 5,115 20% 6,160 13% Linear Arrays 165 12% 185 11% 205 7% 220 7% 235 9% Total Semicustom 4,010 0% 4,005 14% 4,550 17% 5,335 20% 6,395 12% MOS Standard Cell 2,065 10% 2,280 20% 2,745 31% 3,585 36% 4,860 24% Bipolar Standard Cell 55 18% 65 15% 75 20% 90 Ð6% 85 11% Total Standard Cell 2,120 11% 2,345 20% 2,820 30% 3,675 35% 4,945 24% Full Custom 2,625 1% 2,650 2% 2,700 1% 2,725 1% 2,750 1% Total Custom 4,745 5% 4,995 11% 5,520 16% 6,400 20% 7,695 13% Bipolar PLDs 335 Ð16% 280 Ð18% 230 Ð33% 155 Ð26% 115 Ð23% Simple MOS PLDs 310 0% 310 27% 395 Ð9% 360 7% 385 6% Complex MOS PLDs 90 44% 130 69% 220 36% 300 83% 550 57% FPGAs 170 32% 225 53% 345 33% 460 55% 715 43% Total MOS PLDs 570 17% 665 44% 960 17% 1,120 47% 1,650 30% Total PLDs 905 4% 945 26% 1,190 7% 1,275 38% 1,765 18% Total ASIC 9,660 3% 9,945 13% 11,260 16% 13,010 22% 15,855 13% WW IC Market 46,315 12% 51,875 31% 67,950 33% 90,295 43% 128,680 29% ASIC % of WW IC Mkt 21% 19% 17% 14% 12% Source: ICE, "Status 1997" 20198B

Figure 3-14. 1991-1995 ASIC Market

As is evident, the mainstream IC market has moved away from bipolar-based ICs toward MOS- based technology. As a result, bipolar gate arrays, bipolar standard cells, and bipolar PLDs are forecast to be the poorest performing of all ASIC segments.

Even with the forecast calling for sustained growth, the ASIC market will decline to represent 14 percent of the worldwide IC market in the year 2001. Fast growth in other IC segments such as DRAMs and microprocessors will outpace growth in the ASIC market in the long run. Therefore, even as the ASIC market increases, its percentage of the overall IC market will slightly lessen.

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1996/1995 1997/1996 1998/1997 1999/1998 2000/1999 2001/2000 1996 1997 1998 1999 2000 2001 1991-2001 1991-1996 1996-2001 Segment Percent Percent Percent Percent Percent Percent ($M) ($M) ($M) ($M) ($M) ($M) CAGR (%) CAGR (%) CAGR (%) Change Change Change Change Change Change MOS Gate Arrays 1% 5,550 5% 5,800 12% 6,500 14% 7,400 14% 8,400 15% 9,700 13% 14% 12% Bipolar Gate Arrays Ð31% 450 Ð37% 285 Ð26% 210 Ð21% 165 Ð21% 130 Ð19% 105 Ð20% Ð15% Ð25% Total Gate Arrays Ð3% 6,000 1% 6,085 10% 6,710 13% 7,565 13% 8,530 15% 9,805 10% 9% 10% Linear Arrays 2% 240 2% 245 4% 255 4% 265 4% 275 4% 285 6% 8% 3% Total Semicustom Ð2% 6,240 1% 6,330 10% 6,965 12% 7,830 12% 8,805 15% 10,090 10% 9% 10% MOS Standard Cell 30% 6,300 25% 7,900 26% 9,950 27% 12,600 28% 16,100 30% 20,930 26% 25% 27% Bipolar Standard Cell Ð6% 80 Ð6 75 Ð7% 70 Ð7% 65 Ð8% 60 Ð8% 55 — 8% Ð7% Total Standard Cell 20% 6,380 25% 7,975 26% 10,020 26% 12,665 28% 16,160 30% 20,985 26% 25% 27% Full Custom 2% 2,800 2% 2,850 2% 2,900 2% 2,950 2% 3,000 2% 3,075 2% 1% 2% Total Custom 19% 9,180 18% 10,825 19% 12,920 21% 15,615 23% 19,160 26% 24,060 18% 14% 21% Bipolar PLDs Ð50% 57 Ð49% 29 Ð28% 21 Ð19% 17 Ð24% 13 Ð31% 9 Ð30% Ð30% Ð31% Simple MOS PLDs Ð6% 360 Ð3% 350 Ð6% 330 Ð6% 310 Ð8% 285 Ð9% 260 Ð2% 3% Ð6% Complex MOS PLDs 15% 635 27% 805 32% 1,060 30% 1,380 31% 1,805 33% 2,400 39% 48% 30% FPGAs 13% 805 25% 1,005 30% 1,310 29% 1,685 30% 2,195 33% 2,915 33% 36% 29% Total MOS PLDs 9% 1,800 20% 2,160 25% 2,700 25% 3,375 27% 4,285 30% 5,575 26% 26% 25% Total PLDs 5% 1,857 18% 2,189 24% 2,721 25% 3,392 27% 4,298 30% 5,584 20% 15% 25% Total ASIC 9% 17,277 12% 19,344 17% 22,606 19% 26,837 20% 32,263 23% 39,734 15% 12% 18% WW IC Market Ð9% 116,920 12% 130,380 18% 154,260 21% 186,035 23% 228,215 24% 283,500 20% 20% 19% ASIC % of WW IC Mkt 15% 15% 15% 14% 14% 14% Source: ICE, "Status 1997" 20199C

Figure 3-15. 1996-2001 ASIC Market Forecast

510

480

450 Gate Array 420 e Sales ($M) g

vera 390

Standard 360 Cell 3-Month A

330

300 Jan. Feb. March April May June July April Sep. Oct. Month

Source: WSTS/ICE, "Status 1997" 21724

Figure 3-16. 1996 Worldwide MOS Gate Array Versus Standard Cell Sales

A closer look at the cumulative annual growth rates of specific segments is displayed in Figure 3- 17. Here, the "hot" markets such as complex PLDs, FPGAs, and MOS standard cells are exposed. At the same time, the demise of bipolar ASICs is evident as well.

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1991-2001 1991-1996 1996-2001 Product CAGR (%) CAGR (%) CAGR (%)

Complex PLDs 39 48 30 FPGAs 33 36 29 MOS Standard Cell 26 25 27 Total ASIC 15 12 18 MOS Gate Arrays 13 14 12 Linear Arrays 6 8 3 Full Custom 2 1 2 Simple PLDs Ð2 3 Ð6 Bipolar Standard Cell 0 8 Ð7 Bipolar Gate Arrays Ð20 Ð15 Ð25 Bipolar PLDs Ð30 Ð30 Ð31

Source: ICE, "Status 1997" 20195C

Figure 3-17. ASIC Product CAGRs

As was shown, the total ASIC market is forecast to grow at a healthy 18 percent CAGR through the end of the decade, with three categories equaling or bettering that performance and seven categories not growing at the same rate as the overall ASIC market.

In 1986, full custom products accounted for more than half of ASIC marketshare. Now, though this segment is growing ever so slightly in terms of dollars, it is continuing to lose marketshare to devices such as standard cells (Figure 3-18). Full custom ASICs are forecast to represent only eight percent of total ASIC product marketshare in the year 2001. Supercomputer manufacturers and the military are the best examples of full custom users. Since overall military spending is down and with supercomputer power available in desktop systems, it stands to reason that there will be less demand for full custom devices. Meanwhile, standard cell devices, which held 37 percent ASIC marketshare in 1996, are forecast to account for 53 percent in the year 2001.

Figure 3-19 forecasts the market for several logic technologies. By the size of the various markets shown in the graphs, it is evident that most designers (and users) have made the switch to MOS technologies to achieve the desired performance from their ASIC devices. As shown, the only device type listed forecast to show significant growth in 1997 is the MOS standard cell segment.

Quarterly market size for the MOS gate array, MOS standard cell, MOS PLD, and bipolar PLD segments are displayed in the next several charts. In Figure 3-20 the MOS gate array market is shown peaking in the 1990-1996 time period in 4Q95. A moderate 12 percent CAGR is forecast for this segment from 1996-2001 as the ASIC market moves more and more to using cell-based designs.

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PLDs PLDs 9% 11% Standard Gate and Full Custom Standard Cell Cell 22% 1991 Linear Arrays 16% 1996 (EST) 37% $9.7B 42% $17.3B Gate and Full Custom Linear Arrays 27% 36%

Full Custom 8%

PLDs 14% 2001 (FCST) Standard Cell Gate and $39.7B 53% Linear Arrays 25%

Source: ICE, "Status 1997" 16278L

Figure 3-18. ASIC Product Marketshare

The MOS standard cell market is shown on a quarterly basis in Figure 3-21. While the market for MOS standard cells dipped in 1Q95, overall it has been characterized by tremendous growth during the past few years. Besides being in used in a broad range of applications, the sizable market increase for standard cells might be explained by the fact that in recent years, many companies have reclassified their full custom devices as standard cell products.

Figure 3-22 portrays the rise in quarterly MOS PLD sales dating back to 1989. Flexibility and quick time-to-marketÑtwo key issues for systems designersÑhave helped propel the MOS PLD market. In 1996, the MOS PLD market was not immune to the Òinventory correctionÓ by the system houses. ICE believes however, that 4Q96 began another upward trend for the MOS PLD market that will extend into 1997.

Meanwhile, the trend for bipolar PLDs is shown in Figure 3-23. Since 2Q90, the bipolar PLD market has dropped steeply. This market shows a tendency to rebound slightly in the first or second quarter of each year compared to the previous fourth quarter, but overall, the trend is still down.

ASIC VENDOR SALES

Top Ten

Before listing any ASIC vendor sales, it should be noted that ICEÕs ASIC sales figures do not include standard products designed from standard cell libraries or with silicon compilers. Only gate and linear arrays, full custom, and standard cell devices sold to only one customer, as well as PLDs, are considered ASICs.

3-16 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Industry Trends

1,000 2,000 1,000 905 1,730 Ð10% 1,630 1,575 790 1,505 1,455 Ð6% 800 Ð13% 1,500 19% Ð3% Ð3% 635 650 1,070 600 Ð20% 2% 1,000 Ð32% 450 840 Ð31% Ð21% 400 285 500 Ð37% Millions of Dollars

Millions of Dollars 200

0 0 1991 1992 1993 1994 1995 1996 1997 1991 1992 1993 1994 1995 1996 1997 (EST)(FCST) (EST) (FCST) Year Year TTL/Other Standard Logic Market Bipolar Gate Array Market

400 100 90 335 85 Ð6% 80 80 75 Ð6% 75 300 280 20% Ð7% Ð16% 65 15% 230 60 55 Ð18% 200 18% 155 Ð33% 40 115 100 Ð26% Millions of Dollars

Millions of Dollars 57 20 Ð50% 29 Ð49% 0 0 1991 1992 1993 1994 1995 1996 1997 1991 1992 1993 1994 1995 1996 1997 (EST)(FCST) (EST)(FCST) Year Year Bipolar PLD Market Bipolar Standard Cell Market

7,900 7000 8000 5,800 6000 5,510 5,550 7000 6,300 5% 1% 6000 25% 5000 4,480 23% 4,860 5000 30% 4000 3,555 26% 4000 3,585 2,845 2,915 36% 3000 22% 2% 3000 2,745 2,065 2,280 31% 2000 20% 2000 10% Millions of Dollars Millions of Dollars 1000 1000 0 0 1991 1992 1993 1994 1995 1996 1997 1991 1992 1993 1994 1995 1996 1997 (EST) (FCST) (EST)(FCST) Year Year MOS* Gate Array Market MOS* Standard Cell Market *Includes BiCMOS and GaAs Source: ICE, "Status 1997" 18928F

Figure 3-19. Selected 1991-1997 Logic Markets

Figure 3-24 provides a list of the top 10 ASIC (not including full custom) suppliers for 1996. With total ASIC sales of about $1.3 billion, NEC retained its position as the leading supplier of ASIC devices. In doing so, it captured almost nine percent of the total ASIC market.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 3-17 ASIC Industry Trends

1,600

1,500

1,400

1,300

1,200

1,100

1,000

900 Dollars (Millions) 800

700

600

500 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q (EST) 1990 1991 1992 1993 1994 1995 1996 Year Source: WSTS/ICE, "Status 1997" 17778L

Figure 3-20. Quarterly MOS Gate Array Market (1990-1996)

1,450 1,350 1,250 1,150 1,050 950 850 750

Dollars (Millions) 650 550 450 350 250 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q (EST) 1992 1993 1994 1995 1996

Source: WSTS/ICE, "Status 1997" Year 18930G

Figure 3-21. Quarterly MOS Standard Cell Market (1992-1996)

3-18 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Industry Trends

550

500

450

400

350

300

250

Dollars (Millions) 200

150

100

0 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q (EST) 1990 1991 1992 1993 1994 1995 1996 Year

Source: WSTS/ICE, "Status 1997" 18929G

Figure 3-22. Quarterly MOS PLD Market (1990-1996)

130 120 110 100 90 80 70 60 50 Dollars (Millions) 40 30 20 10 0 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q (EST) 1990 1991 1992 1993 1994 1995 1996 Year Source: WSTS/ICE, "Status 1997" 17777M

Figure 3-23. Quarterly Bipolar PLD Market (1990-1996)

INTEGRATED CIRCUIT ENGINEERING CORPORATION 3-19 ASIC Industry Trends

Total Gate and Standard Percent Of 1996 PLD** Sales Company ASIC Sales Linear Array Cell Sales Total ASIC Rank ($M) ($M) Sales ($M) ($M) Market*

1 NEC 1,290 890 400 — 8.9

2 LSI Logic 1,205 575 630 — 8.3

3 Lucent (Ex AT&T) 1,065 35 960 70 7.4

4 Fujitsu 1,050 785 265 — 7.3

5 Toshiba 975 675 300 — 6.7

6 TI 955 490 450 15 6.6

7 Hitachi 615 475 140 — 4.2

8 Xilinx 530 — — 530 3.7

9 VLSI Technology 480 110 370 — 3.3

10 Altera 460 — — 460 3.2

Top Ten Total 8,625 4,035 3,515 1,075 59.6

Other Suppliers 5,852 2,205 2,865 782 40.4

Total Market 14,477 6,240 6,380 1,857 100.0

Top Ten Marketshare 60% 65% 55% 58% 60%

*Not including full custom **Includes FPGA Sales Source: ICE, "Status 1997" 20194C

Figure 3-24. 1996 Top Ten ASIC* Sales Leaders

LSI Logic, the number two supplier in 1996, has been the preeminent North American gate array vendor for many years. However, it is now a world leader in sales of standard cell devices as well. It is estimated that 1996 was the first year that LSI LogicÕs cell-based ASIC sales were greater than its gate array sales.

Lucent and TI were members of the top ten list due to their strong sales of standard cell devices. They are number one and three, respectively, in worldwide sales of standard cell devices. Xilinx, the leading supplier of PLDs, was at the number eight position for total ASIC sales in 1996 while Altera captured the number 10 spot. Overall, the top ten ASIC suppliers had sales that accounted for 60 percent of the total ASIC market in 1996.

Gate Array Suppliers

The top ten gate array suppliers for 1996 are shown in Figure 3-25. The listing contains five Japanese companies, four U.S. companies, and one Korean company.

The double digit declines of Fujitsu and Hitachi can be attributed to two factors. The first is the steep decline of the bipolar gate array market. The second is the weak yen/dollar exchange rate in 1996, which served to lower the Japanese sales figures when reported in dollars (see Section 1).

3-20 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Industry Trends

1996/1995 1996 1996 1995 1996 (EST) COMPANY PERCENT PERCENT RANK MOS BIPOLAR TOTAL MOS BIPOLAR TOTAL CHANGE MARKETSHARE

1 NEC 830 65 895 800 55 855 Ð4 14 2 Fujitsu 645 295 940 600 185 785 Ð16 13 3 Toshiba 678 — 678 675 — 675 — 11 4 LSI Logic 605 — 605 575 — 575 Ð5 10 5 TI 440 — 440 490 — 490 11 8 6 Hitachi 375 163 538 360 115 475 Ð12 8 7 Motorola 195 55 250 195 45 240 Ð4 4 8 Mitsubishi 200 — 200 230 — 230 15 4 9 IBM 160 — 160 200 — 200 25 3 10 Samsung 155 — 155 185 — 185 19 3 Others 1,227 72 1,299 1,240 50 1,290 Ð1 22 Total 5,510 650 6,160 5,550 450 6,000 Ð3 100

Source: ICE, "Status 1997" 21744

Figure 3-25. 1996 Top Ten Gate Array Suppliers

Two relative newcomers to the merchant gate array market made the top ten in 1996 Ñ IBM and Samsung. Both companies have been very aggressive and successful in their quest for a larger share of the ASIC industry.

Gate arrays continue to infiltrate the market for small, electronic systems with advanced functions. Speed and low power, two of the most preferred performance characteristics in ICs, are especially desired in gate arrays. Manufacturers have been quick to respond these needs while adding density as well. Typically, 0.5-0.8-micron technology is used to manufacture the majority of gate arrays. However, 0.35-micron technology has been used for several of the million-plus gate arrays that have been built in limited production.

As recently as five years ago, the average gate array density was in the 10,000-gate range. In 1996, ICE believes that about 90 percent of all gate arrays had at least 10,000 gates. More specifically, ICE believes that 44 percent of the gate array market was represented by devices with between 20,000 and 50,000 gates in 1996 (Figure 3-26). By the year 2001, ICE anticipates that MOS gate arrays will have an average usable gate count of at least 60,000 gates (up from about 20,000 in 1996).

Placing large numbers of gates on a gate array has not been an insurmountable hurdle. IBM, LSI Logic, and Mitsubishi are a few of the firms that have developed gate arrays with over one million available gates. At these densities, it becomes increasingly possible to incorporate large-scale circuitry on a single chip. Circuit density and manufacturing have brought gate arrays to a higher level of acceptance and integration. The biggest challenges facing designers of these ÒmegaÓ gate arrays are test and packaging issues.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 3-21 ASIC Industry Trends

≤10K Gates 9%

>50K Gates 11% >50K Gates ≤10K Gates 10K - 20K 3% 10K - 20K Gates 25% 1996 1996 Gates 36% 39% 20K - 50K $5.6B 610M Units Gates 20K - 50K 44% Gates 33%

Source: ICE, "Status 1997" 18931F

Figure 3-26. Estimated 1996 MOS Gate Array Market and Unit Shipments by Gate Count (Usable)

The gate array market by geographic sector is shown in Figure 3-27. Japan continues to lead as the largest consuming region of both bipolar and MOS gate arrays. In 1996, ICE estimates Japan captured 43 percent of the total gate array market, while the North American region is estimated to have represented 35 percent of the market in 1996.

ROW 5%

Europe 13%

North 1996 America Japan 31% 51%

Total Bipolar Market = $450M

ROW ROW Europe Europe 7% 6% 16% 16%

Japan North 1996 North 1996 Japan 42% America America 43% 35% 35%

Total MOS Market = $5.55B Total Market = $6.0B

Source: ICE, "Status 1997" 8881Z

Figure 3-27. Estimated Worldwide Digital Gate Array Market by Region

3-22 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Industry Trends

The worldwide gate array market by end-use is segmented in five categories and shown in Figure 3-28. Data processing applications are where most gate arrays were used in 1996. ICE does not anticipate much of a change by the year 2001. Data processing and telecom applications will expand slightly, while other applications decline. The military segment will be a smaller player despite the fact the Defense Department is very encouraged about further incorporating gate arrays into its systems.

Telecom Telecom 19% 21% Data Data 1996 Industrial 2001 Processing Processing Industrial (EST) 13% (FCST) 55% 57% 11%

Consumer Consumer 10% 9% Military Military 2% 3%

Total Market = $6.0B Total Market = $9.8B Source: ICE, "Status 1997" 9933V

Figure 3-28. Gate Array Market by Application

Standard Cell Suppliers

The major standard cell suppliers in 1996 are shown in Figure 3-29. The companies occupying the first eight positions remained the same in 1996 as in 1995. However, IBM more than doubled its standard cell sales in 1996 and jumped from ranking twelfth in 1995 to ninth in 1996. In general, the Japanese companies put a lot of emphasis on the standard cell segment when the memory market retreated.

The worldwide standard cell market by geographic sector is displayed in Figure 3-30. In 1996, JapanÕs share of the standard cell market was 35 percent; 38 percent for the North American region. In 1996, North AmericaÕs share of the market increased four percentage points. The Japanese market lost one point due mostly to the weak Japanese yen.

The 1996 and 2001 standard cell markets by application are provided in Figure 3-31. Much like the gate array market, data processing and telecom will continue to be the leading consuming segments for standard cell devices over the next five years. Some expansion is forecast for the consumer/auto sector. Automobiles are incorporating ever-increasing electronic sophistication into their systems and standard cells will be a big part of that business. Meanwhile, the industrial and military segments will decline to account for slightly more than three percent of the total by the year 2001.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 3-23 ASIC Industry Trends

1996/1995 1996 1996 1995 1996 (EST) COMPANY PERCENT PERCENT RANK MOS BIPOLAR TOTAL MOS BIPOLAR TOTAL CHANGE MARKETSHARE

1 Lucent (Ex AT&T) 650 — 650 960 — 960 48 15 2 LSI Logic 575 — 575 630 — 630 10 10 3 TI 315 — 315 450 — 450 43 7 4 NEC 340 — 340 400 — 400 18 6 5 VLSI Technology 310 — 310 370 — 370 19 6 6 Symbios 292 — 292 330 — 330 13 5 7 Toshiba 243 — 243 300 — 300 23 5 8 Fujitsu 220 5 225 260 5 265 18 4 9 IBM 100 — 100 210 — 210 110 3 10 LG Semicon 150 — 150 200 — 200 33 3 Others 1,665 80 1,745 2,190 75 2,265 30 36 Total 4,860 85 4,945 6,300 80 6,380 29 100

Source: ICE, "Status 1997" 21743

Figure 3-29. 1996 Top Ten Standard Cell Suppliers

ROW 8% Europe North 19% America 1996 38% (EST)

Japan 35%

Total Market = $6.4B Source: ICE, "Status 1997" 10403X

Figure 3-30. Worldwide Standard Cell Market by Region

PLD Suppliers

The top players in the 1996 PLD market and their sales are shown in Figure 3-32. Sales figures do not include software and development system sales. There are several small-to-medium size companies that vigorously compete for PLD marketshare. Firms such as Xilinx (which took over the leadership position in 1994), Altera, Lattice, and Actel have all displayed leadership in this fast growing market.

One of the major benefits driving PLD usage continues to be fast time-to-market. Of three prof- itability factors (rapid time-to-market, production costs, and development cost overrun), time-to- market is often the most critical in an electronics industry where market windows seem to be continuously shrinking.

3-24 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Industry Trends

Telecom Telecom Data 1996 33% Data 2001 36% Processing (EST) Processing (FCST) 48% 45% Industrial 4% Industrial 3% Consumer/Auto Consumer/Auto 14% Military Military 16% 1% <1% Total Market = $6.4B Total Market = $21.0B Source: ICE, "Status 1997" 12906Q

Figure 3-31. Standard Cell Market by Application

1996/1995 1996 1996 1995 1996 (EST) COMPANY PERCENT PERCENT RANK MOS BIPOLAR TOTAL MOS BIPOLAR TOTAL CHANGE MARKETSHARE

1 Xilinx 495 — 495 530 — 530 7 29 2 Altera 382 — 382 460 — 460 20 25 3 AMD 260 63 323 275 30 305 Ð6 16 4 Lattice 158 — 158 175 — 175 11 9 5 Actel 98 — 98 135 — 135 38 7 6 Lucent (Ex AT&T) 55 — 55 70 — 70 27 4 7 Cypress 55 — 55 50 — 50 Ð9 3 8 Philips 5 18 23 30 12 42 83 2 9 QuickLogic 12 — 12 21 — 21 75 1 10 Atmel 18 — 18 20 — 20 11 1 Others 112 34 146 34 15 49 Ð66 3 Total 1,650 115 1,765 1,800 57 1,857 5 100 *Does not include software and development system sales.

Source: ICE, "Status 1997" 13601R

Figure 3-32. PLD Sales Leaders*

Lively competition in the PLD market has resulted in several "marginal" players exiting the market in recent years. National Semiconductor announced that it stopped taking new orders for programmable logic. Intel sold its programmable logic business to Altera for $50 million in cash and stocks. Actel declared that it purchased the FPGA business of its second-source partner, Texas Instruments. IBM announced in 3Q96 it would not enter the PLD market with its own line of SRAM-based FPGAs. And, although they have no plans to exit the PLD market, AMD and Philips turned their respective PLD divisions into wholly-owned subsidiaries to keep up with changes in the fast-paced PLD market.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 3-25 ASIC Industry Trends

With falling prices, the MOS PLD market weakened through the first three quarters of 1996. However, compared to the overall semiconductor industry, it was a strong performer. Moreover, the forecast through the end of the decade calls for greater market expansion.

Complex PLDs (CPLDs) and FPGAs will contribute the most to the expected growth of the programmable logic sector. CPLDs and FPGAs often target the same applications, including data communications and telecommunications equipment, PC peripherals and add-in cards, and electronic games.

CPLDs are being turned to more often because of their low cost, compared with less-dense simple PLDs. For essentially no added expense, designers can consolidate several simple PLD designs into one complex PLD.

Why havenÕt simple PLD prices dropped as well? As small process geometries reduce die size and cost, PLD prices are more influenced by the package. This means that, for a simple PLD, a customer may pay more for the package than the silicon. With smaller process geometries reducing costs, designers can save board space and lower the total system cost by using CPLDs.

PLD marketshare for 1996 is displayed in Figure 3-33. Xilinx, which took over as the leading PLD supplier in 1994, increased its PLD marketshare from 24 percent in 1994 to 29 percent in 1996. Xilinx's growth has come through aggressive market introduction of many, very well accepted new products.

AMD, which held 46 percent of the total PLD marketshare in 1988, secured only 16 percent in 1996. Its grip on the PLD market loosened quickly due to aggressive competition from many smaller, but very aggressive suppliers. In addition, up until around 1990, AMD emphasized bipolar PLDs. In fact, 1993 was the first year AMD produced a greater percentage of CMOS PLDs than bipolar PLDs. AMD is still the leading bipolar PLD supplier, but that segment is dwindling. AMD now vigorously pursues CMOS technology. Its CMOS-based complex PLDs, fast, low-voltage PLDs, and PLDs characterized for the "green computerÓ environment have been successful.

It is interesting to note that only 20 percent of PLD consumption came from the combined regions of Japan and the ROW (Figure 3-34). In general, the Japanese and ROW regions have been slow to adopt PLDs into system designs because of their emphasis on high-volume consumer electronics. Most of the current usage of PLDs in these regions is for prototyping eventual gate array and standard cell designs.

3-26 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Industry Trends

Other Cypress 7% 3% Lucent 4% Actel 7% Xilinx 29%

Lattice $1,857M 9%

AMD Altera Other 16% 25% Cypress 5% 3% Lucent 4% TOTAL PLD Actel MARKET 8% Philips Xilinx 21% 29% Lattice AMD 10% $1,800M $57M 53% TI AMD 26% Altera 15% 26%

CMOS BIPOLAR Source: ICE, "Status 1997" 13602R

Figure 3-33. Estimated 1996 PLD Marketshare

ROW 7%

Japan 13% North $1,800M America Europe 57% 23%

ROW MOS PLD Market ROW 7% 7%

Japan Japan 14% 13% North North $57M $1,857M Europe America Europe America 24% 55% 23% 57%

Bipolar PLD Market Total PLD Market Source: ICE, "Status 1997" 19513D

Figure 3-34. Estimated 1996 PLD Markets by Region

INTEGRATED CIRCUIT ENGINEERING CORPORATION 3-27 ASIC Industry Trends

ASIC TECHNOLOGY TRENDS

Overview

It is becoming increasingly difficult to distinguish between each of the ASIC product categories. Until recently, the ASIC industry could be divided up into the three well-defined product groups: semicustom ICs (gate arrays and linear arrays), custom ICs (standard cells and full custom devices), and programmable logic devices (simple and complex PLDs, FPGAs, and EPACs). However, the lines separating those three categories are getting blurry. The best features of products from one category are increasingly showing up in products of other categories.

Take, for example, embedded arrays, which are based on a gate array structure but have large megacells such as compiled memories or microprocessor cores embedded in them (Figure 3-35). The cores provide a higher level of integration than a pure gate-array structure, but can lead to longer prototype leadtimes, though, still shorter than the leadtimes for pure cell-based ASICs.

RAM ROM

Sea of Gates Array

Special Function Serial I/O

Source: EDN/ICE, "Status 1997" 19190B

Figure 3-35. Typical Embedded Array ASIC

Another example of the convergence of ASIC technologies is ActelÕs (co-developed with Synopsys) so-called SPGA (system-programmable gate array) that was announced in 4Q96 (Figure 3-36). Figure 3-37 describes some of the details of the Actel device. Ultimately, Actel will be using combinations of antifuse-, SRAM-, and/or flash-based PLD circuitry, mask-programmable gate array logic, and cell-based cores to serve the diverse ASIC customer base.

3-28 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Industry Trends

(a) (b)

Field - Field - Programmable Programmable Logic Logic

66MHz Mask PCI Core Programmable ASIC

Datacom Computer Instrumentation ¥ Router ¥ DMA ¥¥¥ ¥ Data Acquisition ¥ Bridge ¥ Graphics ¥ Image Processing

An SPGA could either be standard Ð an FPGA with widely used cells on chip (a) or customer specific Ð a combination FPGA and gate array (b). Source: Electronic Products/ICE, "Status 1997" 21735

Figure 3-36. ActelÕs System-Programmable Gate Array (SPGA)

Density: 100K gates; 400K gates in 1998 Part Number: A65ES100 Volume Production: 1Q97 Volume Price: $348 Packaging: 240-pin PQFP, 432-pin SBGA PLD Circuitry: SRAM-based; antifuse and flash planned Process Technology: CMOS 0.35µm 3-layer metal* Die Size: 103mm2

* Initially fabricated by Chartered Semiconductor

Source: Actel/ICE, "Status 1997" 21736

Figure 3-37. ActelÕs SPGA Characteristics

The increase in the functionality of ASICs has been realized by the industryÕs quick migration to deep-submicron process technologies. Figure 3-38 lists several ASIC producers that have discussed their advanced ASIC technologies. Note that the companies offering this leading-edge technology are all major ASIC producers. The rapid advancement in ASIC technology, however, has not come without challenges or compromises.

Design Productivity Issues

One of the most significant challenges facing the ASIC industry is design productivity. Although great strides have been made in ASIC software design tools and design productivity (Figure 3-39), the improvements have not been able to keep pace with the increases in gate density (Figure 3-40). Figure 3-41 shows how far design productivity has lagged IC density since 1981.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 3-29 ASIC Industry Trends

Feature Metal Gate Company Year Series Voltage Size (Leff) Layers Oxide (Å) IBM 1995 CMOS 5S 0.25µm 6 90 3.3V Microelectronics 1996 CMOS 5X 0.4µm 5 70 2.5V

1997 CMOS 6S 0.18µm 6 — 2.5V

Hitachi/ 1996 HG73C 0.35µm* 5 60 2.5V VLSI Technology

NEC 1995 CMOS-9 0.27µm 4 — 2.5V/3.3V

Toshiba 1994 TC200 0.36µm 3 — 3.3V

Oki 1995 MSM98R 0.4µm 3 — 3.3V/5V

LSI Logic 1995 G10 0.25µm 5 — 2.5V/3.3V

Lucent 1996 System- 0.32µm 4 50/65 2.5V/3.3V Technologies ASIC

Texas 1996 Timeline 0.18µm 6 — 2.5V/3.3V Instruments

SGS-Thomson 1996 CB4500 0.35µm 5 — 3.3V

* Drawn gate length Source: ICE, "Status 1997" 19177D

Figure 3-38. Sampling of Leading-Edge ASIC Technologies

3,000 3,000

2,500

2,000

1,500 1,500

Gates/Person/Month 1,000 750

500 500

150

0 Early 1980's Mid 1980's Late 1980's Early 1990's Mid 1990's

Source: ICE, "Status 1997" 17667B

Figure 3-39. Increasing Design Productivity

3-30 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Industry Trends

10M

Memory Density MPU Density (Bits) (Transistors) 1M

ASIC Density (Usable Gates) 100K

10K 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 Year

Source: ICE, "Status 1997" 21019

Figure 3-40. IC Density Increases

Memory Density (Bits) 250x

ASICs (Usable Gates) 100x

MPUs (Transistors) 75x

Design Productivity* 20x

*(Gates/Person/Month)

Source: ICE, "Status 1997" 21020

Figure 3-41. 1981-1996 IC Industry Improvements

INTEGRATED CIRCUIT ENGINEERING CORPORATION 3-31 ASIC Industry Trends

Overall, CAD tools are going to be a key issue in producing high-density sub-0.35µm ASICs. As will be discussed later in this section, the move to using core cells (e.g., DSPs, MCUs, etc.) in an ASIC design is one way to help offset the lag in design productivity.

ASIC Process Technology Issues

In the mid-1980Õs, ASIC devices were typically using process technology that was 2-3 years behind high-volume memory part types (Figure 3-42). Today, however, processes rivaling the technolog- ical advancement of state-of-the-art memory devices are being developed specifically for ASICs (Figure 3-43). Notice in Figure 3-44 how MitsubishiÕs ASIC process roadmap parallels its DRAM development.

10.0

5.0 4.0 1.67 MOS Gate Array 3.0 64K 1.5 2.0

m) 256K µ 1.33

1.0 DRAM 1M 1.25

Feature Size ( 1.00 0.5 0.4 16M 1.00

0.3 64M

0.2

0.1 '83 '84 '85 '86 '87 '88 '89 '90 '91 '92 '93 '94 '95 '96 '97 Year = Gate Array/DRAM Feature Size Ratio Source: ICE, "Status 1997" 18531A

Figure 3-42. ASICs Narrow Technology Gap

While deep-submicron integration has allowed for unprecedented performance and economies of scale, it has also brought with it a new set of design challenges. With larger geometry chips, circuit timing is limited primarily by gate delays. However, as geometries shrink, delay from the resistance and capacitance of the wiring interconnect between transistors begins to dominate (Figure 3-45). Interconnect delays have increased, as a percent of total delay, from 15-30 percent at the 1.0µm level to 50-75 percent at the 0.35µm level.

3-32 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Industry Trends

Volume Process Generation Gate Density Manufacturing (Drawn, µm) (Gates/mm2) Start 2.0 100 to 200 1986 1.2 300 to 500 1989 0.7 1,250 to 1,500 1992 0.5 5,000 to 6,000 1994 0.35 15,000 to 20,000 1996 0.25 30,000 to 40,000 1998 0.18 45,000 to 60,000 2001

Source: SGS-Thomson/ICE, "Status 1997" 21734

Figure 3-43. Roadmap: CMOS Logic Technology Platforms for ASICs

4 Meg DRAM 16 Meg DRAM 64 Meg DRAM 256 Meg DRAM

0.8µm drawn, Micro Power 0.35µm, 3V 5V 0.5µm drawn, 3V 250K usable gates 500K usable gates 2000K usable gates 215ps 200ps 4 layer metal 101ps

0.8µm, 3V 5 Volt 0.30µm, 2.5V 0.6µm, 5V 250K usable gates 400K usable gates 3000K usable gates 370ps 190ps 82ps

Ultra Performance 0.25µm, 2.5V 0.5µm, 3V 700K usable gates 145ps

Source: Mitsubishi/ICE, "Status 1997" 21199

Figure 3-44. MitsubishiÕs ASIC Process Roadmap

In battling the effects of increased resistance and capacitance associated with increasingly thinner, narrower, and more closely spaced interconnects, ASIC designers are having to spend more and more design iterations identifying and solving timing errors; or else, settle for a design that does not use the full speed potential of the silicon to get a functional chip.

Other challenges intensified by shrinking circuit geometries include limiting crosstalk between interlayer and adjacent wires, managing I/O issues like simultaneously switched outputs, and minimizing clock skews.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 3-33 ASIC Industry Trends

Typical Gate Delay

1 Delay, ns

0.1

Average Wiring Delay

Feature Size: 1.5µm 1.2µm 1.0µm 0.8µm 0.5µm 0.3µm Circuit Size: 20 30 60 150 500 1,000 (thousands of gates) Source: OKI Semiconductor/ICE, "Status 1997" 20407A

Figure 3-45. Wiring (Interconnect) Delay Versus Gate Delay

Business Issues

The ASIC/ASSP industry is not only challenged by technical issues (e.g., processing, packaging, design, and test) but also by business considerations. One such consideration is ASIC industry standards. In general, the high-density ASIC/ASSP marketplace will continue to expand regard- less of whether a framework of standards exists or not. However, some type of Òopen-industryÓ organization could help facilitate a less cumbersome path for companies to follow into the future.

In response to the surge toward the Òsystem-on-a-chipÓ ICs, the Virtual Socket Interface (VSI) alliance was formed in 3Q96. As of 4Q96 VSI had brought together 50 companies (Figure 3-46) including EDA vendors, intellectual-property (IP) vendors, semiconductor producers, and system manufacturers.

The goal of VSI is to allow a chip designer to use IP information (e.g., core cells of an ASIC) sourced from numerous companies to create an IC design that could be produced by any one of a number of semiconductor manufacturers. Of course for this to happen, IC design and process compatibility standards must be created by VSI*. Licensing and royalty issues of IP must also be addressed.

* Version 1.0 of the VSI standard is due out in early 1997.

3-34 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Industry Trends

EDA VENDORS SEMICONDUCTOR VENDORS Aspec Actel Cadence Alcatel-Mietec Compass Altera Escalade Chip Express Exemplar Logic Cirrus Logic Ikos Systems Cypress Semiconductor Mentor Graphics Fujitsu Quickturn Design Systems GEC Plessey Semiconductor Smartech Oy Hitachi Summit LG Semicon Synopsys LSI Logic Technical Data Freeway Matsushita Viewlogic National VLSI Libraries NEC INTELLECTUAL-PROPERTY VENDORS Oki Advanced Logic Philips Semiconductors ARM Sharp CompCore Multimedia Symbios Logic DSP Group Texas Instruments Excellent Design Toshiba Integrated Silicon Systems TSMC iReady VLSI Technology NEuw Intellectual Property Xilinx Object Oriented Hardware SYSTEMS VENDORS Palmchip Alcatel Phoenix Technologies Silicon Graphics Prairie Comm Sun Rapid* Sony Sand Sierra Research Sun/Java Technical Data Freeway 3Soft VLSI Libraries *Rapid is a consortium of intellectual-property vendors Source: EE Times/ICE, "Status 1997" 21719

Figure 3-46. Virtual Socket Interface (VSI) Brings in Multiple Vendors

Gate Array, Embedded Array, and Cell-Based ASICs

The primary ASIC methodologies in use today are CMOS gate array, embedded array, and standard cell. Which methodology to use depends on the particular application.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 3-35 ASIC Industry Trends

As already mentioned, ASICs are increasingly being used to build systems on a chip, which requires blocks (or cores) of high-performance memory, processor, and special I/O functions. This rise in complexity is the reason behind the prediction that standard cell and embedded array ASICs will dominate over gate arrays before the end of the decade. The transistors in gate arrays are generally not laid out conveniently for some of the more complex logic functions, resulting in a mess of wires (and a large chip).

Cores may be selected from a vendorÕs core library and ordered, like a product off the shelf, for design into a standard cell or embedded array ASIC. Advanced cores featured in some core libraries include high-performance RISC or CISC microprocessors (Figure 3-47), MPEG coder/decoders, network communications controllers, high-density memories, and high-performance analog functions. Shown in Figure 3-48 is a macrocell/core roadmap for Lucent Technologies, the worldÕs largest standard cell ASIC supplier in 1996.

Power Dissipation Vendor Processor Core Size Clock (MHz) Cache (bytes) Volts Process Typical (mW)

Advanced RISC Machines ARM 610 26mm2 33 495 4K 5 0.6µ ARM 710 34mm2 45/25 424/50 8K 5, 3 0.6µ ARM 810 55mm2 72 500 8K 3 0.6µ StrongARM 50mm2 200 900 32K 2 0.35µ

Hitachi America SH-1 5.9mm2 20 400 — 5, 3 3 LM/0.5µ

IBM Microelectronics 401 4.5mm2 50 10 2K 2.7 0.5µ 602 (w/cache, FPU) 350K 66 1,200 8K I cache, — 3 LM 8K D cache

LSI Logic MiniRISC 4001 11.8mm2 60 120 — 3.3 0.5µ 4002 11.9mm2 40 80 — 3.3 0.6µ 4003 1.28 x 1.28mm2 85 85 — 3.3 0.35µ 4010 13.3mm2 80 400 — 3.3 0.5µ 4011 12.7mm2 100 350 — 3.3 0.6µ 4020 12.7mm2 133 465 — 3.3 0.35µ

Mitsubishi Electronic Device Group M32R/D 5.7mm2 66.7 270 2K & 1K DRAM* 3.3 0.45µ/2 LM

Motorola Flex Core 17K 20 150 — 2.7-5.5 0.65µ/3 LM 68000 68020 67K 33 370 256 I cache same same 68030 96K 33 485 256 I & D cache same same ColdFire M2 45K 33 60 2K same same

NEC Electronics R4100 25mm2 33 250 — 2.2/3.3 —

SGS-Thomson Microelectronics ST20 25mm2 33 60 — 5, 3.3 0.5µ/3 LM 486 51mm2 50 — 8K 3.3 0.3µ/4 LM

Toshiba America R3900 26mm2 50 400 4K I cache 1.8-3 0.6µ/2 LM (15 w/o cache) 1K D cache

* = added to core; LM = number of layers of metallization Source: Computer Design/ICE, "Status 1997" 21732

Figure 3-47. Sampling of 32-bit MPU ASIC Cores

3-36 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Industry Trends

Application 1995 1996 1997

PC MPEG Decoder Video Scaler Multimedia, PLL PCI Controller Video Decoder Extensions Fast SRAM Video-DAC 120-200MHz PLL Audio DAC/ADC Card Bus Interface I2C Bus Interface

Office 960-RISC 68K RISC RISC Core Extensions Automation Z80 µC SPARCDSP P1394 Serial Port LCD Controller Z180 µC USB Interface

Data C2XLP DSP C5x DSP DSP Core Extensions Communications 12-bit DAC/ADC Fiber Channel Transceiver Fiber Channel Controller

Telecom 10 Base-T MAC updates ISDN-S Interface ATM Interface 10/100 Base-T MAC TI/EI Framer RAMBUS Interface 6-port SRAM FDDI/Tx Transceiver HDLC Controller 1627 DSP

Source: Lucent Technologies/ICE, "Status 1997" 21200

Figure 3-48. Lucent TechnologiesÕ Macrocell Roadmap

Demand for DSP-core (Figure 3-49) based ASICs is surging in high-volume, cost-sensitive applications such as wireless and wireline communications, consumer electronics, and multimedia computers. Depending on the vendor, orders for ASICs with embedded DSP cores are being accepted only if annual production volumes are anticipated to be anywhere from at least 50,000 units in some cases to more than 500,000 units in others.

Where Code Development Company Architecture Design Tools Manufactured Tools

Analog Devices ADSP2171 ADI foundries Mentor Standard for 2171 ADSP2171 Mentor foundries Mentor Standard for 2171 ADSP2171 Any Mentor Standard for 2171

DSP Group Pine/Oak Any Verilog PC-based assembler Synthesis and simulator

Motorola DSP56300 Motorola Cadence--Alta PC-based EVM Group SPW and software tools

SGS Thomson ST18 SGS Thomson VHDL Mentor GNU-based C compiler and Synopsys and assembler

Tensleep Design TI compatible Any — —

Texas Instruments TMS320C25 TI foundries Proprietary Standard TI TMS320C5x worldwide TMS320C54x TMS320C2xx

3Soft TMS320C25 Any — Standard TI

Source: EDN/ICE, "Status 1997" 21731

Figure 3-49. Sampling of DSP Core Cells

INTEGRATED CIRCUIT ENGINEERING CORPORATION 3-37 ASIC Industry Trends

Recent notable announcements regarding gate arrays, embedded arrays, and standard cells are provided below.

¥ Hitachi began taking orders for its HG73G gate array and HG73E embedded array 0.35µm CMOS ASICs in April 1996. The triple-metal process enables designs of up to 1.5 million gates.

¥ IBM Microelectronics unveiled an extensive plan to target the cell-based ASIC marketplace using a wide range of what it calls Òsystem building blocksÓ (Figure 3-50). IBMÕs most advanced ASIC family dubbed the System ASIC-12 (SA-12) was unveiled in May 1996. Details concerning the SA-12 architecture are provided below.

Production Volumes: 2Q97 (netlists accepted in 4Q96) Technology: 0.25µm drawn (0.18µm effective) gate length Metal Pitch: 1.0µm Metal Layers: Up to 6 Raw Gates: Up to 5M Usable Gates: Up to 3.5M I/Os: Up to 1,088 Power Supply: 2.5V with power dissipation of 0.08- 0.18µW/MHz/gate Special Macros: 32-/64-bit PowerPC MPU/MCU, DSP, VGA, Rambus interface, audio compression, MPEG-2

¥ In early 1996, IBM Microelectronics began accepting netlists for its CMOS 5X processÑthe third and final derivative of the companyÕs 0.5µm ASIC process. The process uses 0.25µm effective gate lengths (0.35µm drawn) and offers up to 1.6 million usable gates and as many as 748 I/O pins. Other features of the architecture include 1.2µm metal pitch and 70• gate oxide thickness.

¥ In 2Q96, LSI Logic added the new Gigabit SeriaLinkª interface core to its CoreWare cell library. The CMOS-based Gigabit SeriaLink supports the Fibre Channel data transmission protocol, which allows for the transmission of up to 1.0625 billion bits of data per second, the equivalent of several 350-page novels a second.

¥ LSI Logic introduced its G10ª ASIC process technology in 3Q95. Figure 3-51 offers a look at some of the G10 characteristics along with a history of previous LSI Logic ASIC technologies.

3-38 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Industry Trends

Processors CISC PPC PPC PPC* Mwave* 403 586 CMC 186 602 603 401 DSP

PPC Periph. SRAM DRAM OPB DMA Serial INTRPT Ctrl Ctrl Ctrl Ctrl Port Ctrl

Tele Audio PC DSP Periph. Codec Codec Bus

Fiber I/O Ports PCI UART PCMCIA SSA SCSI ENET Channel

DATA/IMAGE Functions ATM MPEG ECC IIC NTSC/PAL Compression

Memory** ROM RAM

Volt Analog PLL DAC ADC Reg

= Available in 1995 *Available in 1996 **Researching Flash Memory

Source: IBM/ICE, "Status 1997" 20403

Figure 3-50. IBMÕs System Building Block Roadmap

LSI CMOS Process G10ª Family 500K 600K 400K 405K 300K

Drawn 0.35µm 0.5µm 0.6µm 0.7µm 0.8µm 0.6µm Effective 0.25µm 0.38µm 0.45µm 0.55µm 0.65µm 0.45µm Architectures Cell Based Cell Based Cell Based Gate Array Cell Based Cell Based Embedded Array Embedded Array Embedded Array Embedded Array Gate Array Gate Array Gate Array Gate Array Metal Interconnect 2, 3, 4, & 5 Layer 2, 3, & 4 Layer 2 & 3 Layer 2 Layer 2 Layer 2 & 3 Layer Operating Voltages 3.3 & 2.5 Volts 3.3 Volts 3.3 Volts 3.3 Volts 5.0 Volts 5.0 Volts I/O Options GTL/NTL/HSTL GTL/NTL/HSTL GTL/NTL GTL/NTL GTL/NTL GTL/NTL PECL to 622 MHz PECL to 622MHz PECL to 155MHz Universal PCI PCI PECL to 155MHz PCI PCI PCI PCI Impedance Controlled Mixed Signal Mixed Signal Mixed Signal Mixed Signal Mixed Signal LVTTL LVDS to 1.2GHz Mixed Signal Gate Capacities Usable (max) 5,000,000 1,500,000 1,200,000 165,000 250,000 600,000 Typical (used) 100K to 2,500K 60 to 500K 40 to 400K 20 to 75K 20 to 100,000K 40 to 300K Power Dissipation 0.4-0.7µW/Gate/MHz 1.0µW/Gate/MHz 1.5µW/Gate/MHz 1.4µW/Gate/MHz 5.0µW/Gate/MHz 3.2µW/Gate/MHz

Source: LSI Logic/ICE, "Status 1997" 20405

Figure 3-51. LSI LogicÕs ASIC Technology Trends

INTEGRATED CIRCUIT ENGINEERING CORPORATION 3-39 ASIC Industry Trends

¥ In May 1996, Mitsubishi introduced its 0.35 Micron ASIC architecture for gate arrays, embedded arrays, and cell-based ICs. Figure 3-52 describes the features of the 0.35 Micron series as well as MitsubishiÕs other ASIC capabilities.

Feature Size Supply Performance Gates Power Series (µm, drawn) Voltage (V) (ps) (max. usable) (µW/gate/MHz)

0.35 Micron 0.35 3 101 (1) 2,000K 0.9 (3) Ultra Performance 0.50 3 145 (1) 700K 1.3 (3) Micro Power 0.50 3 (5V I/O) 200 (1) 500K 0.8 (3) 5 Volt 0.60 5 (or 3) 190 (2) 400K 2.2 (4) M6007x/8x 0.80 5 (or 3) 215 (2) 250K 2.2 (4) (1) 2-NAND, 3.3V, F.O. =2, 2mm Al (2) 2-NAND, 5.0V, F.O. =2, 2mm Al (3) 2-NAND, 3.3V, F.O. =1 (4) 2-NAND, 5.0V, F.O. =1

Source: Mitsubishi/ICE, "Status 1997" 21201

Figure 3-52. MitsubishiÕs ASIC Capabilities

¥ In May 1996, Texas Instruments introduced what it calls its Timeline Technology (Figures 3- 53 and 3-54) for building ASICs with 0.18µm (Leff) linewidths (0.21µm drawn) and 125 million transistors on a chip. TIÕs TEC6000 gate arrays will be available for prototyping in mid-1997 while initial TSC6000 standard cell design starts will begin in 2H97. The Timeline standard cell devices have a maximum die size of 19mm x 19mm*.

TGC2000 TGC3000T TGC4000 TGC6000 Series Series Series Series; "Timeline"

Technology (Leff) 0.55µm 0.44µm 0.35µm 0.18µm

Metal Levels 2/3 3 3/4 6

Gate Count 455K 1.2M 1.7M 12M (Max Available)

Core Voltage 5V/3V 3V 3V 1.8V

Interface Capability 5V/3V 5V/3V 5V/3V 5V/3V/2.5V

I/O Frequency 105MHz 850MHz 850MHz 2.5GHz

Number of I/Os 520 704 952 1,800

CAD Tools Cadence, Mentor, Cadence, Mentor, Cadence, Mentor, Cadence, Mentor, IKOS, Synopsys IKOS, Synopsys IKOS, Synopsys IKOS, Synopsys, Viewlogic

Source: TI/ICE, "Status 1997" 21729

Figure 3-53. TIÕs Gate Array Offerings

* At 361mm2 only 60 dice would fit on a 200mm wafer.

3-40 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Industry Trends

TSC2000 TSC3000 TSC4000 TSC5000 TSC6000 Series Series Series Series Series; "Timeline"

Technology (Leff) 0.55µm 0.44µm 0.35µm 0.25µm 0.18µm

Metal Levels 3 3 3 4 6

Gate Count 600K 1M 2M 4M 16M (Max Available)

Core Voltage 5V/3V 3V 3V/2.5V/2V 3V/2.5V/2V 1.8V

Interface Capability 5V/3V 5V/3V 5V/3V/2.5V/2V 5V/3V/2.5V/2V 5V/3V/2.5V/1.8V

Power (µW/MHz/gate) 1.0/0.42 @ 5V/3V 0.33 @ 3V 0.15 @ 3V 0.06 @ 2.5V 0.025 @ 1.8V

CAD Tools Cadence, Mentor, Cadence, Mentor, Cadence, Mentor, Cadence, Mentor, Cadence, Mentor, Synopsys Synopsys Synopsys Synopsys Viewlogic, Synopsys

Source: TI/ICE, "Status 1997" 21730

Figure 3-54. TIÕs Standard Cell Offerings

¥ In 3Q96 IBM began giving its standard cell ASIC customers access to its ÒTurboÓ prototyping service. The ÒTurboÓ service offers 22-day turnaround from design sign-off to finished devices.

¥ In 2Q96 Chip Express moved to a 0.6µm three-layer metal process for its quick turnaround laser programmed gate arrays. The new technology allows gate arrays of up to 200K gates to be produced in as little time as one-day.

¥ Chip Express also began offering its Gate Array Express program. For a production com- mitment for as few as 900 units, the customer would be allowed several one-day design iterations and would not be required to pay an NRE charge.

¥ Through its acquisition of ASIC Technical Solutions, Microchip Technology began offering its QuickASIC program for converting FPGA-based designs into mask-programmable gate arrays. The arrays run in size from 6K to 72K gates; turnaround time is two to four weeks.

¥ Samsung announced in 3Q96 that it was offering 1M DRAM capability in its cell-based ASIC 0.5µm product line. The first product, the EDL60 provides 60K gates of random logic and the 1M of DRAM. A 100K logic gate 4M DRAM device is expected in 1997.

¥ In 4Q96 Symbios Logic unveiled its 0.35µm, 3.3V, five-layer metal cell-based family called SYM9. The cell library includes up to 2M of DRAM, mixed-signal circuitry, DSP cores, etc. (Figure 3-55).

INTEGRATED CIRCUIT ENGINEERING CORPORATION 3-41 ASIC Industry Trends

ARM7

DRAM

LOGIC

Analog

Data

Acquisition PCI

Source: Symbios Logic/ICE, "Status 1997" 21728

Figure 3-55. SYM9 Cell-Based ASIC Example

¥ In 4Q96 Motorola and Mitsubishi signed an agreement to exchange embedded DRAM and microprocessor cell technologies. Mitsubishi will provide Motorola with its 32-bit M32R/D processor and embedded DRAM design and process technology while Motorola will give Mitsubishi its ColdFire and 68EC000 microprocessor design to be used in MitsubishiÕs cell- library.

¥ In 4Q96, TI introduced a cell-based ASIC targeting the cellular phone marketplace (Figure 3-56). The device includes DSP and ARM RISC processor cells as well as user specified logic. The cell-based platform used for this device is TIÕs 0.25µm TSC5000 Family.

PLDs and FPGAs

The first field programmable logic devices were introduced almost 25 years ago. Basically, the benefits of using programmable logic have been shortening time to market and risk reduction. This has been true for over 20 years and will continue to be true in the foreseeable future.

Over the twenty years of programmable logic offerings, the term PLD has evolved to encompass more than just low-density bipolar products. The PLD industry has gone from using strictly bipolar technology and simple architecture to using CMOS EPROM, EEPROM, SRAM, flash, and antifuse processing with very elaborate circuit designs.

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Antenna Analog Baseband Device

TMS320C54x Receiver DSP TRF1xxx

Speech Code/Decode Audio Error Correction RF Synthesizer Power Amp Interface Channel Code/Decode Interface TRF2xxx TRF7xxx Equalization Demodulation

kplane Encryption S/W Modulator Driver TRF3xxx TRF8xxx

RF Section ARM7TDMIE (c470) User Display Op Amps Microcontroller

TSC5000 ASIC Bac Keyboard Switches Man & Machine Interface SIM Card O/S Software Regulators Speaker Microphone Radio Resource Mgmt. Short Message Service S/W

Digital Baseband Platform

Source: TI, EN/ICE, "Status 1997" 21727

Figure 3-56. TIÕs Cell-Based Cellular Phone ASIC

In an industry as dynamic as the IC industry, the natural trend has been toward high-density and high-performance technologies. In the PLD market this is very obvious as simple bipolar PLDs are now steadily losing marketshare to the more flexible and higher density CMOS PLD technologies.

As was previously mentioned, ASSPs (Application Specific Standard Products) are taking away some of the market previously served by traditional ASIC devices. Along these same lines, there are an increasing number of PLDs being tailored for specific applications. In fact, nearly every major PLD/FPGA supplier has recently announced the availability of a library of system-level cores/megacells that can be embedded in their device designs, thereby allowing PLDs to be used as system-level chips.

Overall, PLDs are moving away from being used only as peripheral logic and more toward core logic at the heart of the system. As PLD technology and capabilities increase, ICE expects the PLD logic segment to be a cornerstone of the ASIC industry.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 3-43 ASIC Industry Trends

Over the last few years the PLD market has been the most dynamic of all IC markets with regard to new product introductions. Shown below is a sampling of some of the major PLD announcements made in 1996.

¥ Actel signed an agreement with intellectual property provider Technical Data Freeway (TDF) that gives Actel a wide range of synthesizable cores to be used in Actel devices. The cores include DSPs and MCUs, as well as telecom and multimedia cores.

¥ In 3Q96 Actel announced its SPGA devices that combine PLD and mask-programmable logic on the same chip (discussed earlier in this section).

¥ Altera announced the availability of the industryÕs highest density PLD, a 100,000-usable- gate version of its FLEX 10K architecture. The FLEX 10K100 has over 10 million transistors and a die size of over 600K square mils. This device was priced at $595/100 in 4Q96 with 1997 volume (5,000 units) pricing expected to be $295. A 250K-gate PLD is expected to be produced in 2H97 using 0.35µm technology. Figure 3-57 shows that along with the large increases in PLD gate density come some of the same Òdesign productivityÓ issues that the gate array and cell-based suppliers must deal with.

1,000,000

PLD Integration Capability Design Productivity PLD Designer Gap 100,000 Productivity (Gates/month)

10,000 Gates

HDL Impact

1,000

100 1985 1990 1995 2000 Year Source: Altera/ICE, "Status 1997" 21202

Figure 3-57. PLD Design Productivity Gap

3-44 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Industry Trends

¥ Altera announced its MegaCore function library of pre-verified system-level building blocks (Figure 3-58). The company also launched OpenCore, a program that allows designers to Òtest driveÓ the megafunctions before licensing them. The MegaCore library complements the Altera Megafunctions Partners Program (AMPP), launched in late 1995.

Initial MegaCore Functions ¥ DMA Controller ¥ 8-bit Processor ¥ UART ¥ Asynchronous Communications Interface Adapter ¥ Interrupt Controller ¥ Parallel I/O controller

Functions Added in 1996 ¥ PCI Initiator/Target ¥ FIFO ¥ Microperipherals ¥ DSP

Source: Altera/ICE, "Status 1997" 21203

Figure 3-58. Altera Announces Megacore Functions Library

¥ Altera revealed in 3Q96 that it was using laser-enacted redundant circuitry (for the last three years) to help improve yields on it high-density PLDs. The added circuitry increased yield up to 40 percent on some of its leading-edge PLDs (Figure 3-59).

¥ AMD formed a separate subsidiary for its PLD product line. In 3Q96 AMD had formed a North American sales force for the PLD unit.

¥ Atmel unveiled the AT6010, a member of its AT6000 FPGA family, which is based on the companyÕs Cache Logic architecture. The 20,000-gate AT6010 features 6,400 registers and supports system speeds of 100MHz, making it well suited to process DSP functions. Atmel is, in fact, marketing the device as a DSP coprocessor.

¥ Crosspoint Solutions unveiled its CP100K family of CrossFireª FPGAs having densities up to 100,000 gates. CrossFire is a proprietary sea-of-gates architecture that allows 60-80 percent gate utilization. The FPGAs will initially be implemented in a 0.5µm 3-/4-layer metal CMOS process, with plans for a migration to 0.25µm technology resulting in chips at 250K-and- beyond gate levels.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 3-45 ASIC Industry Trends

30 e g vement o 25 centa er

P 20 Yield Impr 15

0 10,000 100,000 Gates Source: Altera/ICE, "Status 1997" 21726

Figure 3-59. PLD Redundancy Yield Improvements

¥ IBM cancelled its SRAM-based PLD program in 4Q96. There are no further plans for IBM to target the PLD segment.

¥ IMP introduced the second member of its electrically programmable analog circuit (EPACª) family. The new chip integrates the functions of over 18 discrete analog and digital CMOS IC components, providing user-configurable monitoring, diagnostic, and data acquisition features.

¥ In 4Q96 Lucent Technologies revealed that it plans to merge its mask-programmable gate array technology and its SRAM-based PLD circuitry into what it calls Field Programmable System Chips (FPSCs). The first FPSC will contain 40K PLD gates and 85K mask-programmable gates.

¥ Lucent also described its four-layer metal 3C (0.35µm) and 3T (0.25µm) PLD families that will be available in 1997 and 1998, respectively. The 3C family will support up to 175K total gates (125K usable), while the 3T family will contain 320K total gates (225K usable).

¥ Motorola announced its long-anticipated entry into the programmable logic market in April 1996, with the introduction of new FPGAs based on technology licensed from EnglandÕs Pilkington Micro-Electronics. The first devices in the Motorola Programmable Array (MPA)

3-46 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Industry Trends

family are available with as many as 14,200 gates. They are reprogrammable SRAM-based products manufactured on a standard 0.6µm triple-layer metal CMOS process. Motorola also announced it had also licensed PilkingtonÕs field-programmable analog array (FPAA) technology.

¥ Long-time simple PLD player, Philips Semiconductors announced its entrance into the complex PLD market in April 1996, by forming a new CPLD business unit to sell its new high- performance, low-power 3.3V devices. The new ÒCoolRunnerÓ CPLDs are an extension of the PLA architecture called eXtended Programmable Logic Array (XPLA). They feature a design technique called Fast Zero Power (FZP), which provides low static (²100µA) and dynamic power (50mA @>100MHz).

¥ Xilinx inaugurated its LogiCore program, which offers a PCI module as well as third-party software including DSP filters, bus interfaces, UARTs, and DMAs for various Xilinx PLDs.

¥ Xilinx unveiled its XC4000EX family of FPGAs, which feature between 28,000 and 62,000 nominal gates. The high density is accomplished through the use of a 0.5µm process and significant architectural changes. The density of the 4000EX FPGAs will increase to 125,000 gates in 1997 when Xilinx moves to a 0.35µm process.

¥ Xilinx discontinued its antifuse-based PLDs and will concentrate on SRAM and flash technology for its FPGAs.

Dynamically Reconfigurable Hardware Based on PLDs

A hot topic among PLD vendors and system designers is Òdynamically reconfigurable hardwareÓ. Dynamically reconfigurable computing could use PLD devices that would be reprogrammed on- the-fly in real time while working in the electronic system. A conceptual view of how SRAM- based PLDs could be dynamically reconfigured is shown in Figure 3-60.

This dynamic reconfigurability is a separate issue from Òin-system programmabilityÓ or ISP. While most complex PLDs are programmed and tested before being attached to a PC board, ISP PLDs are programmed and tested while on the PC board* (eliminating one handling step).

Atmel describes its reconfigurable logic as Òcache logic.Ó Since much of a systemÕs hardware logic is idle at a given time, the ability to reconfigure the logic on-the-fly to optimally serve the softwareÕs immediate computational requirements can greatly accelerate the performance of the system.

* Usually using the JTAG IEEE 1149.1 interface.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 3-47 ASIC Industry Trends

SRAM "Fuses" Loaded with 0s and 1s Data Uninitialized Data SRAM "Fuses" Clock Clock Enable Enable

Primary Primary Outputs Outputs 001101101001 XXXXXXXXXXX 101101001011110100100001 XXXXXXXXXXXXXXXXXXXXXX 011001101000 XXXXXXXXXXX 000110110011 XXXXXXXXXXX 101100111101 XXXXXXXXXXX

Primary Primary Inputs Inputs

(a) Unconfigured (b) Configured

Source: EDN/ICE, "Status 1997" 21725

Figure 3-60. Conceptual View of Dynamic Reconfiguration

Some possible early system applications for reprogrammable logic include telecommunications, geophysical information processing, medical imaging, and computer architecture simulation. In the telecommunications area one can easily envision the need for a PLD device to dynamically reconfigure itself to accommodate multiple interface or telecommunications protocols and standards.

As another example of a reconfigurable application, Altera states that its reprogrammable PLDs can be configured as a display accelerator or circuit simulator as needed. Altera says Òthat by using reprogrammable logic the potential exists to configure the hardware for more direct processing of the data.Ó

Xilinx believes that dynamic reconfigurable systems will not significantly impact the PLD marketplace until at least 1998. However, it estimates that the reconfigurable systems market will grow to more than $1 billion in sales by the end of the decade with the FPGA chip portion estimated at approximately $200 million.

There is little doubt that reconfigurability will be a powerful tool to enhance a systemÕs efficiency. Still, in-system-reconfigurable PLD logic is still in its infancy. Current design tools and programs are still not sufficient to manage dynamically reconfigurable hardware efficiently. However, as system designers continue to explore ways to increase system performance, ICE expects that reconfigurable PLDs will find an increasing market to serve.

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PLD Pricing Considerations

The 1996 price-per-gate for the PLD device was only four times the price of a similar density CMOS gate array. In 1993, the PLD was 15 times the cost of a similar density CMOS gate array.

Using a total cost formula, the breakeven point for the gate array and PLD can be derived. At the 10,000 usable gate level, the PLD solution was more cost effective at unit volumes below 2,502 in 1996 (Figure 3-61). This figure was only 414 in 1991 for comparable 5,000 gate devices (Figure 3-62).

140

120

100

80 10K-Gate 75,200 1996 Gate Array 60 66,250

49,450 1996 40 Breakeven 10K-Gate Units 20 1996 2,502 Total Cost (Thousands of Dollars) PLD 8,000 0 0 200 400 600 800 1,000 1,200 1,400 1,600 1,800 2,000 2,200 2,400 2,600 2,800 3,000 Project Units Source: ICE, "Status 1997" 16723E

Figure 3-61. 1996 10,000 Usable Gate Total Cost

As shown, it does not take a large number of units for the gate array approach to amortize its large fixed cost to the point where it becomes more cost effective than the PLD. The $24 PLD unit price versus the $6.00 gate array device price assures a fairly low-volume crossover point given almost any reasonable gate array NRE charge. However, as is shown in Figure 3-62, the breakeven crossover point has become more favorable for PLDs with each passing year.

Because the NRE charge is such a small part of the total cost make-up of an FPGA, the total unit price of the 1996 10,000 usable gate device decreases only 37 percent when going from using 200 units to using 3,000 units. However, because such a large portion of the gate array total cost is NRE, the amortization of the NRE causes the 1996 10,000 usable gate array total unit price to decrease about 91 percent when going from using 200 units to 3,000 units.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 3-49 ASIC Industry Trends

3,000 2,800 2,600 2,502 2,400 2,200 2,000 1,800 1,600 olume

V 1,386 1,400

Unit 1,200 1,000 966

800 660 600 494 414 400 200 0 1991 1992 1993 1994 1995 1996 Year (EST) Source: ICE, "Status 1997" 21022

Figure 3-62. PLD Versus Gate Array Total Cost Breakeven Unit Volumes (1991-1996)

Whether at 200 or 3,000 units, a very high percentage of the gate arrayÕs cost is due to fixed (i.e., NRE) costs. When the IC industry was slumping (1989-1991) and heavily discounted NRE charges were the norm, the choice to use a gate array was very clear from the beginning. However, now that NRE charges have firmed, the PLD choice looks more attractive, especially at low unit volumes.

About 96 percent of the cost of using PLDs at 3,000 units is from variable costs (i.e., the unit price). This is the reason it is so critical for the PLD producer to reduce device costs by using advanced processes (0.6µm or less) and interconnect (3-layers of metal or more) schemes, both of which result in reduced die sizes and lower unit costs.

Since 1985, Xilinx has lowered its FPGA price per gate by at least 30 percent per year*. Assuming this trend continues, the 10,000 usable gate FPGA would cost about $4.03 in 2001. However, at $4.03, the crossover point between the FPGA and gate array is over 500,000 total units. This figure is more than 225 times the unit crossover point of 1996.

* From 1991 to 1996 the average annual decline was 37 percent.

3-50 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Industry Trends

If the FPGA and gate array price trends continue as mentioned in the previous paragraph, the relative FPGA/gate array price ratio by the end of the decade would be much less than 2:1 (Figure 3-63). Given the time-to-market benefits of FPGAs, and less than a 2x price difference, it would be safe to assume that FPGAs would serve the vast majority of low gate count (²40,000 gates) needs at that time.

10 8 6

1 1995 Actual 0.8 0.6 MOS PLD Price Per Gate 33X 0.4 Trend 1996 Actual 15X 12X 0.2 6X

Cents Per Usable Gate 4X 0.1 0.08 3X 2X 0.06 CMOS Gate Array 1.5X 0.04 Price Per Gate Trend

0.02

1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 Year Source: ICE, "Status 1997" 18551E

Figure 3-63. Relative Price Per Gate for MOS PLDs Versus Low Gate Count Gate Arrays

It is interesting to note that in most cases, the CMOS gate array supplier is not fighting the PLDÕs attack on the low-end market. Most CMOS gate array suppliers are concentrating on the high- density, high-performance, and high unit volume segment of the gate array market. With business booming from 1992 through 1995, gate array vendors were very ÒselectiveÓ of the contracts they took for gate array devicesÑoftentimes turning down business in the process! In 1996, a few vendors had changed their tune with regard to the gate array business.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 3-51 ASIC Industry Trends

What this now means as far as the trend lines shown in Figure 3-63 is that the low-end CMOS gate array price per gate may stay relatively flat in the future. With little competitive pressure, the low- end CMOS gate array price per gate could even increase in the late 1990Õs. Low gate-count arrays could even be at a higher price per gate than PLDs after the year 2000!

Figure 3-64 shows how steeply MOS PLD prices were dropping in 1996. As shown, Xilinx has also stated its aggressive PLD pricing plans will continue through the second half of 1997.

48 x 45

42 = Early 1996 Price 39 x = Late 1996 Price 36 = 2H97 Price 33 30 s 27 x

Dollar 24 21

18 x 15 12 x 9 6 x 3 0 0 2 4 6 8 10 12 14 16 18 20 Thousands of Gates Source: Xilinx/ICE, "Status 1997" 21023

Figure 3-64. XilinxÕs FPGA Price Reductions

While the 30 percent or greater decline in the PLD price per gate may be difficult to sustain into the late 1990Õs, there is little doubt that PLDs will become more competitive in price compared to low- end gate arrays. This is one reason that ICE is bullish about the future of the PLD/FPGA business.

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PLD Summary

In general, the MOS PLD market will continue to be one of the most dynamic in the entire IC industry. As PLD technology and capabilities increase, ICE expects the PLD logic segment to be a cornerstone of the ASIC industry. Some key PLD developments to watch for throughout 1997 and beyond include:

- Implementation of 0.35µm feature size technology.

- Aggressive PLD price reductions.

- Increased offerings of high-gate-count devices.

- Migration of PLD propagation delays to as low as 3.5ns (or lower) and operating frequencies as high as 200MHz.

- Further offerings of specialized core cells for PLDs.

- Additional development of in-system programmable (ISP) and dynamically reconfigurable infrastructure (hardware and software).

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