ADVANCED MICRO DEVICES, INC. (Exact Name of Registrant As Specified in Its Charter)
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Intel Corporation
US RESEARCH | PUBLISHED BY RAYMOND JAMES & ASSOCIATES INTEL CORPORATION (INTC-NASDAQ) JULY 26, 2021 | 8:27 PM EDT Semiconductors COMPANY BRIEF Chris Caso | (212) 856-4893 | [email protected] Melissa Fairbanks | (727) 567-1081 | [email protected] Underperform 4 New Names, Same Problems Suitability M/ACC Intel hosted its "Intel Accelerated" manufacturing roadmap update Monday evening, detailing their process roadmap through 2025. The presentation laid a path through which Intel hopes to MARKET DATA Current Price (Jul-26-21) $54.31 have achieved parity with TSMC (and by extension, AMD) by 2024, and a goal of process leadership Market Cap (mln) $221,802 by 2025. This is no different from the goals laid out by Intel’s new CEO when he came on board Current Net Debt (mln) $10,552 a quarter ago, but the company did provide more details about how they intend to achieve that Enterprise Value (mln) $232,354 Shares Outstanding (mln) 4,084.0 goal. Attaining leadership by 2025 requires Intel to introduce a full process node improvement 30-Day Avg. Daily Value (mln) $1,362.7 each year for the next 4 years – an aggressive assumption given the production missteps from Dividend $1.39 the past several years. What Intel didn’t disclose were the costs of this roadmap, which we Dividend Yield 2.6% 52-Week Range $43.61 - $68.49 expect them to discuss during the November analyst day. And while there is great uncertainty BVPS $14.76 about Intel’s ability to achieve these targets, what’s less uncertain is a requirement for higher Long-Term Debt (mln) $24,632 capital intensity. -
Dear Shareholders
MARCH 2020 DEAR SHAREHOLDERS: Five years ago, AMD set out on a journey. We established a clear focus on becoming a high-performance computing leader and defined an ambitious technology roadmap grounded in a series of key investments. As a company, we committed to strong execution and engaged deeply with our customers and partners, including industry leaders like Amazon, Apple, Google, HPE, Lenovo, Microsoft and Sony. 2019 was a major milestone in that journey. We introduced and successfully ramped the strongest product portfolio in our history spanning desktops, laptops, gaming and the data center, including the launches of the world’s first 7nm x86 CPUs and PC GPUs. On the strength of this portfolio and strong execution, we delivered record annual revenue of $6.73 billion, strong gross margin expansion and significant profitability growth. For the second year in a row, AMD was the best performing stock in the S&P 500. Strong customer demand for our 7nm Ryzen™ and EPYC™ processors powered by our next generation “Zen 2” processor core drove $1.5 billion in client and server processor annual revenue growth in 2019. REVENUE GROSS MARGIN OPERATING MARGIN NET INCOME $ Billions $ Millions $6.7 43% $6.5 38% 9% $337 $341 7% $5.3 34% $4.3 23% 2% 2016 2017 2018 2019 2016 2017 2018 2019 2016 2017 2018 2019 2016 2017 2018 2019 ($33) -9% Leadership Products Drive Premium Products Drive Solid Growth With ($498) Significant Growth Revenue Growth Margin Expansion OpEx Investments in Profitability Computing and Graphics segment revenue grew 14% in 2019 primarily based on strong demand for our AMD Ryzen™ desktop and mobile processors. -
Partial Reconfiguration: a Simple Tutorial
Partial Reconfiguration: A Simple Tutorial Richard Neil Pittman Microsoft Research February 2012 Technical Report MSR-TR 2012-19 Microsoft Research Microsoft Corporation One Microsoft Way Redmond, WA 98052 Partial Reconfiguration: A Simple Tutorial A Tutorial for XILINX FPGAs Neil Pittman – 2/12, version 1.0 Introduction Partial Reconfiguration is a feature of modern FPGAs that allows a subset of the logic fabric of a FPGA to dynamically reconfigure while the remaining logic continues to operate unperturbed. Xilinx has provided this feature in their high end FPGAs, the Virtex series, in limited access BETA since the late 1990s. More recently it is a production feature supported by their tools and across their devices since the release of ISE 12. The support for this feature continues to improve in the more recent release of ISE 13. Altera has promised this feature for their new high end devices, but this has not yet materialized. Partial Reconfiguration of FPGAs is a compelling design concept for general purpose reconfigurable systems for its flexibility and extensibility. Despite the significant improvements in software tools and support, the Xilinx partial reconfiguration design option has a reputation for being an expert level flow that is difficult to use. In this tutorial we will show that it can actually be quite simple. As a case study, we apply Partial Reconfiguration to the Simple Interface for Reconfigurable Computing (SIRC) toolset. Combining SIRC and partial reconfiguration makes the idea of general purpose hardware and software user systems deployed on demand on generic platforms viable. The goal is to make developers more confident in the practicality of this concept and in their own ability to use it, so that more will take advantage of what it has to offer. -
Xilinx-Solution-Brief-Bluedot.Pdf
SOLUTION BRIEF Product Name DeepField-SR – Deep Learning based Video Super Resolution Accelerator INTRODUCTION DeepField-SR is a fixed functional hardware accelerator leveraging Xilinx Alveo Cards to offer the highest computational efficiency for Video Super Resolution. Based Solution Image on proprietary Neural Network trained with real world video data from the internet and fusing spatio-temporal information in multiple frames, it produces superior high resolution video quality. BENEFITS Key Features Comparing with EDSR(NTIRE 2017) on Tesla V100 > A fixed functional hardware > 45x faster than GPU accelerator offering high throughput > Scalable architecture to support multiple FPGA cards > Low upscaling latency > Deep Neural Network suitable for resource limited FPGA > 0.03 better quality assessment in LPIPS metric than > Deep Neural Network trained EDSR with real world video data > 44x lower latency than GPU > Designed with High Level Synthesis > Easy to update and upgrade per market demands > 1x FPGA card required Adaptable. Intelligent. © Copyright 2020 Xilinx SOLUTION OVERVIEW DeepField-SR is deployable on both public cloud and on-premise with Xilinx Alveo U200/U50 Accelerator Cards. As it is designed in scalable architecture and supports multiple FPGA cards, it can flexibly respond to various resolution upscale request. Its runtime performance on single Alveo U50 is 11 ~ 14fps to upscale video up to 4K resolution. The API is integrated within an FFmpeg workflow, meaning that simple command enables DeepField-SR acceleration and upscaling user input video. TAKE THE NEXT STEP Learn more about BLUEDOT Inc. For DeepField-SR quality evaluation, please visit http://kokoon.cloud Reach out to BLUEDOT sales at [email protected] Corporate Headquarters Europe Japan Asia Pacific Pte. -
Dr Lisa Su, CEO
Welcome to Hot Chips 31! Organizing Committee John D. Davis (Barcelona Supercomputing Center) General Chair Conference Sponsor: IEEE Technical Committee on Microprocessors and Microcomputers Conference Details & Stats • WELCOME BACK TO STANFORD!!! • Registration • Record numbers!!! • Sponsorship • Intel sponsoring the conference food • 6 Platinum or better • 7 Gold • 10 Silver Intel’s Hot Wings @ Hot Chips • Free shuttle buses from 7:30 to 8 pm @ the Alumni Center Parking •Must use the parking pass • Only good in Galvez or Eucalyptus lots •Don’t have a pass? • We have spare passes in the lobby Food Details • Breakfast & Breaks in the Courtyard. • Lunch served in Dohrmann Grove • Overflow seating in East Oval Grove • Hot Chips Reception in Dohrmann Grove Presentations Available…. •Day of the presentations •http://www.hotchips.org/attendees-program/ •Password: cloudyrisc •Videos will be available in a couple of weeks •WiFi instructions printed on the back of your badge and the walls Behind the scenes • Volunteer-run conference • Steering Committee • Organizing Committee • Program Committee • Volunteers • Lost and Found is at the Registration Desk Hot Chips Then and Now Location History • HC1: Stanford: Kresge Auditorium → Demolished 2009 • HC10-23, 25: Stanford: Memorial Auditorium • HC30: De Anza College : Flint Center for the Performing Arts • HC24, HC26-30, RIP Flint…. • HC31: Stanford: Memorial Auditorium • Please excuse the dust… Sessions Then and Now • HC1 • HC31 • New SPARC CPUs • General Purpose Compute • RISC CPU Updates • Memory -
Alveo U50 Data Center Accelerator Card Installation Guide
Alveo U50 Data Center Accelerator Card Installation Guide UG1370 (v1.6) June 4, 2020 Revision History Revision History The following table shows the revision history for this document. Section Revision Summary 06/04/2020 Version 1.6 Chapter 1: Introduction Updated the information. Card Features Added new section. Chapter 2: Card Interfaces and Details Added a caution. Known Issues • Added a known issue about installing the U50 card deployment package. • Added a known issue about downgrading to a beta platform. Downgrading Packages Added information about downgrading to a beta platform. Downgrading Packages Added information about downgrading to a beta platform. 02/27/2020 Version 1.5 XRT and Deployment Platform Installation Procedures on Replaced steps 4, 6, 7, 8, and 9 to document the new RedHat and CentOS installation steps for U50. Replaced all mentions of zip files with tar.gz. XRT and Deployment Platform Installation Procedures on Replaced steps 1, 2, 3, and the log file of step 6 to document Ubuntu the new installation steps for U50. Replaced all mentions of zip files with tar.gz. Running lspci Revised log file in step 2. Running xbmgmt flash --scan Revised output, platform, and ID information in step 1. Upgrading Packages Updated step 1 to include a link to chapter 4; removed steps 2-6. Upgrading Packages Updated step 1 to include a link to chapter 4; removed steps 2-6. 01/07/2020 Version 1.4 Installing the Card Updated to add notes about UL Listed Servers and card handling. 12/18/2019 Version 1.3 General Updated output logs. -
Ipox® Portfolio Holding Analysis 02/24/2021
IPOX® PORTFOLIO HOLDING ANALYSIS 02/24/2021 To learn more, visit www.ipox.com; Email: [email protected] MARVELL TECHNOLOGY GROUP LTD (MRVL US) | AQUANTIA CORP (AQ US) Office: +1 (312) 526-3634 COMPANY DESCRIPTION Support +1 (312) 339-4114 ACQUIRER Founded in 1995, Marvell Technology Group is semiconductor company headquartered in Santa Clara, CA. Marvell provides data infrastructure semiconductor solutions for data storage, processing, networking, security and connectivity. TARGET Founded in 2004, Aquantia Corp is a fabless semiconductor company that designs, develops and markets advanced high-speed communications integrated circuits (ICs) for Ethernet connectivity. TARGET IPO HISTORY Aquantia began trading on the NYSE on 11/3/2017 led by Morgan Stanley. The ICs developer sold 6,818,000 shares at $9.00 per share, below its expected price range ($10 to $12). With the 15% greenshoe options fully exercised, Aquantia was valued at ca. $300.09 million. The shares opened at $9.31/share and closed the first day higher at $9.51 (▲5.67%). Aquantia Corp entered the IPOX® Universe on the 7th day of trading. M&A HISTORY Marvell Technology Group announced to buy Aquantia for $452 million on 5/9/2019 at $13.25 per share in cash, which represented a 38.60% premium to Aquantia’s previous close. The acquisition of the Multi-Gig Ethernet company was completed on 9/19/2019. Marvell Technology Group was included in the IPOX® 100 U.S. Portfolio (ETF: FPX) on 3/23/2020 and currently weights approximately 4.90% of the portfolio. *Marvell Technology Group was added to the Nasdaq-100 Index® on December 21, 2020. -
AMD Socket AM2 with AMD M690T Chipset Reference Schematic D D
5 4 3 2 1 AMD Socket AM2 with AMD M690T Chipset Reference Schematic D D NOTES: Page Index Page Index ------- -------------------------------------------- ------- -------------------------------------------- 1) This schematic supports the AMD Socket AM2 CPU devices. 1 Cover Page 17 SB600 PCIe, PCI, LPC, Straps, & CPU Control 2) These are "Reference Schematics" and as such they have 2 Revision History 18 SB600 ACPI, GPIO, USB, and Audio Interfaces not been verified by an actual board build. 3 Block Diagram 19 SB SATA, IDE, SPI, and HW Management Interfaces 3) This reference schematic supports AMD M960T revision 4 Clock Structure 20 SB600 Power A12 or later. If A12 or later revision is not used, please 5 Power Configuration (1) 21 CRT Connector see your customer support representative for the 6 Power Configuration (2) 22 Broadcom Ethernet Controller necessary application notes for workarounds. 7 Reset & Voltage Sequence 23 Realtek Audio Codec C 4) This reference schematic supports SB600 revision 8 Socket AM2 HT Interface 24 LPC BIOS C A21 or later. If A21 or later revision is not used, please 9 Socket AM2 DDRII Memory Interface 25 USB Power and Connectors see your customer support representative for the 10 Socket AM2 Control & Debug 26 Power Main System, SB600 PCIe, & Other necessary application notes for workarounds. 11 Socket AM2 Power & Ground 27 Standby Power & Powergood 5) Unless otherwise specified, resistors have 5% tolerance. 12 SODIMM DDR2 28 Power for CPU Core 13 M690T HT, PCI, PCIe(R), PCIe Graphics Port 29 Power for DDR2 Memory and Interface 6) Unless otherwise specified, capacitors have 20% tolerance. 14 M690T PLL and Video Interface 30 Power M690T Core, PCIe Interface 15 M690T Power and Side Port Memory Interface 31 Unused Interfaces 16 Clock Generator IMPORTANT NOTICE: B 1. -
Verisilicon and Cadence
VeriSilicon and Cadence “Using Allegro FPGA System Planner XL, we completed pin assignment in one week. A manual pin-assignment process would have been error-prone, tedious, and time-consuming—it would have taken at least one month.“ Steven Guo, Package Design and PCB Implementation Manager, VeriSilicon The Customer Business Challenges VeriSilicon Holdings Co. is a world-class IC design foundry • Meet an aggressive timeline for an FPGA- that provides custom silicon solutions and system-on-chip based ASIC prototyping project (SoC) / system-in-package (SiP) turnkey services. The company’s • Develop a scalable prototyping platform solutions combine licensable digital signal processing cores, for hardware/software integration and eDRAM, value-added mixed-signal IP, and other IP into SoC co-verification platforms that extends to sub-65nm process technologies. These platforms are used in a wide range of consumer Design Challenges electronics devices, including set-top boxes, home gateway • Accelerate the design process with devices, mobile Internet devices, cell phones, HDTV devices, automated, placement-aware pin and Blu-ray/DVD players. assignment • Optimize the physical connectivity, even as For five consecutive years, Deloitte LLP has ranked VeriSilicon it changes among the top 50 high-tech, high-growth companies in China. Red Herring named VeriSilicon one of the top 100 private • Ensure quality and reduce complexity with companies in Asia, and EE Times named the company one of reuse of interface rules and protocols 60 emerging start-ups. Headquartered in Shanghai, China, Cadence Solutions VeriSilicon has R&D centers in both China and the United States, • Allegro FPGA System Planner XL with sales and customer support offices throughout Asia, the United States, and Europe. -
Entrepreneurship and Business Leadership
SPONSOREDEntrepreneurship BY and Business Leadership Thematic Report on Chinese American Contributions: Entrepreneurship and Business Leadership 1 WRITTEN BY Entrepreneurship and Business Leadership Entrepreneurship and Business Leadership Enterprises are the lifeblood of the American economy. They fund 84% of all investments and account for roughly 85% of non-farm employment.1,2 Small and medium-sized enterprises (SMEs), in particular, are primary drivers of US innovation and competitiveness. Firms with fewer than 500 employees account for 99.9% of US businesses and employ nearly half (47%) of the private non- farm workforce.3 Chinese Americans have played an integral part in entrepreneurship and business in the US ever since the first Chinese immigrants arrived during the Gold Rush. Historically, despite various barriers, including formal and informal racial discrimination, Chinese Americans have played an important role in shaping the American economic, social and cultural fabric through diverse forms— ranging from owning and operating mom-and-pop shops to founding high-tech startups and serving as executives of publicly-listed companies. 2 Overview Americans take great pride in their entrepreneurial spirit, which is deeply rooted in the country’s history and essential to corporate success and economic and societal prosperity. Chinese Americans have shared and contributed to this central tenet of American social identity both by establishing small businesses that provide essential services and generate a vast number of jobs and by working -
Advanced Micro Devices, Inc. 2485 Augustine Drive Santa Clara, California 95054
ADVANCED MICRO DEVICES, INC. 2485 AUGUSTINE DRIVE SANTA CLARA, CALIFORNIA 95054 NOTICE OF ANNUAL MEETING OF STOCKHOLDERS You are cordially invited to attend our 2020 annual meeting of stockholders (our “Annual Meeting”) to be held on Thursday, May 7, 2020 at 9:00 a.m. Pacific Time. In light of the coronavirus/COVID-19 outbreak and governmental decrees that in-person gatherings be postponed or canceled, and in the best interests of public health and the health and safety of our Board of Directors, employees and stockholders, the Annual Meeting will be held virtually via the Internet at www.virtualshareholdermeeting.com/AMD2020. You will not be able to attend the Annual Meeting in person. We are holding our Annual Meeting to: • Elect the eight director nominees named in this proxy statement; • Ratify the appointment of Ernst & Young LLP as our independent registered public accounting firm for the current fiscal year; • Approve on a non-binding, advisory basis the compensation of our named executive officers, as disclosed in this proxy statement pursuant to the compensation disclosure rules of the U.S. Securities and Exchange Commission (the “SEC”); and • Transact any other business that properly comes before our Annual Meeting or any adjournment or postponement thereof. We are pleased to provide access to our proxy materials over the Internet under the SEC’s “notice and access” rules. As a result, we are mailing to our stockholders (other than those who previously requested printed or emailed materials on an ongoing basis) a Notice of Internet Availability of Proxy Materials (the “Notice”) instead of printed copies of our proxy materials. -
Electronics/Computers
Electronics/Computers Spaceborne Hybrid-FPGA System for Processing FTIR Data NASA’s Jet Propulsion Laboratory, Pasadena, California Progress has been made in a continu- vantage of the reconfigurable hardware in the software, it has been possible to re- ing effort to develop a spaceborne com- resources of the FPGAs. duce execution time to an eighth of that puter system for processing readout data The specific FPGA/embedded-proces- of a non-optimized software-only imple- from a Fourier-transform infrared sor combination selected for this effort is mentation. A concept for utilizing both (FTIR) spectrometer to reduce the vol- the Xilinx Virtex-4 FX hybrid FPGA with embedded PowerPC processors to fur- ume of data transmitted to Earth. The one of its two embedded IBM PowerPC ther reduce execution time has also been approach followed in this effort, ori- 405 processors. The effort has involved considered. ented toward reducing design time and exploration of various architectures and This work was done by Dmitriy L. Bekker, reducing the size and weight of the spec- hardware and software optimizations. By Jean-Francois L. Blavier, and Paula J. Pin- trometer electronics, has been to exploit including a dedicated floating-point unit gree of Caltech and Marcin Lukowiak and the versatility of recently developed hy- and a dot-product coprocessor in the Muhammad Shaaban of Rochester Institute brid field-programmable gate arrays hardware and utilizing optimized single- of Technology for NASA’s Jet Propulsion Lab- (FPGAs) to run diverse software on em- precision math library functions and a oratory. For more information, contact iaof- bedded processors while also taking ad- modified PowerPC performance library [email protected].