Electronics/Computers

Spaceborne Hybrid-FPGA System for Processing FTIR Data NASA’s Jet Propulsion Laboratory, Pasadena, California Progress has been made in a continu- vantage of the reconfigurable hardware in the software, it has been possible to re- ing effort to develop a spaceborne com- resources of the FPGAs. duce execution time to an eighth of that puter system for processing readout data The specific FPGA/embedded-proces- of a non-optimized software-only imple- from a Fourier-transform infrared sor combination selected for this effort is mentation. A concept for utilizing both (FTIR) spectrometer to reduce the vol- the Xilinx Virtex-4 FX hybrid FPGA with embedded PowerPC processors to fur- ume of data transmitted to Earth. The one of its two embedded IBM PowerPC ther reduce execution time has also been approach followed in this effort, ori- 405 processors. The effort has involved considered. ented toward reducing design time and exploration of various architectures and This work was done by Dmitriy L. Bekker, reducing the size and weight of the spec- hardware and software optimizations. By Jean-Francois L. Blavier, and Paula J. Pin- trometer electronics, has been to exploit including a dedicated floating-point unit gree of Caltech and Marcin Lukowiak and the versatility of recently developed hy- and a dot-product coprocessor in the Muhammad Shaaban of Rochester Institute brid field-programmable gate arrays hardware and utilizing optimized single- of Technology for NASA’s Jet Propulsion Lab- (FPGAs) to run diverse software on em- precision math library functions and a oratory. For more information, contact iaof- bedded processors while also taking ad- modified PowerPC performance library [email protected]. NPO-45957

FPGA Coprocessor for Accelerated Classification of Images NASA’s Jet Propulsion Laboratory, Pasadena, California An effort related to that described in phenomena such as flooding, volcanic that translates C-language programs into the preceding article focuses on develop- eruptions, and sea-ice break-up. The hardware description language (HDL) ing a spaceborne processing platform for FPGA provides hardware acceleration for files, the legacy C-language program, fast and accurate onboard classification increased onboard processing capability and two newly formulated programs for of image data, a critical part of modern than previously demonstrated in software. a more capable expanded-linear-kernel satellite image processing. The approach The original C-language program — and a more accurate polynomial-kernel again has been to exploit the versatility of demonstrated on an imaging instrument SVM algorithm, have been implemented recently developed hybrid Virtex-4FX aboard the Earth Observing-1 (EO-1) in the Virtex-4FX FPGA. In tests, the field-programmable gate array (FPGA) to satellite — implements a linear-kernel FPGA implementations have exhibited run diverse science applications on em- SVM algorithm for classifying parts of significant speedups over conventional bedded processors while taking advan- the images as snow, water, ice, land, or software implementations running on tage of the reconfigurable hardware re- cloud or unclassified. Current onboard general-purpose hardware. sources of the FPGAs. In this case, the processors, such as on EO-1, have lim- This work was done by Paula J. Pingree, FPGA serves as a coprocessor that imple- ited computing power, extremely lim- Lucas J. Scharenbroich, and Thomas A. ments legacy C-language support-vector- ited active storage capability and are no Werne of Caltech for NASA’s Jet Propulsion machine (SVM) image-classification algo- longer considered state-of-the-art. Laboratory. For more information, contact rithms to detect and identify natural Using commercially available software [email protected]. NPO-45961

SiC JFET Transistor Circuit Model for Extreme Temperature Range Simple modifications of common silicon model provide reasonable approximation from 25 to 500 °C. John H. Glenn Research Center, Cleveland, Ohio

A technique for simulating extreme- with Integrated Circuit Emphasis source code enable SiC JFETs to be sim- temperature operation of integrated cir- (SPICE) general-purpose analog-inte- ulated to 500 °C using the well-known cuits that incorporate silicon carbide grated-circuit-simulating software. “Level 1” model for silicon metal oxide (SiC) junction field-effect transistors NGSPICE in its unmodified form is used semiconductor field-effect transistors (JFETs) has been developed. The tech- for simulating and designing circuits (MOSFETs). First, the default value of nique involves modification of made from silicon-based transistors that the MOSFET surface potential must be NGSPICE, which is an open-source ver- operate at or near room temperature. changed. In the unmodified source sion of the popular Simulation Program Two rapid modifications of NGSPICE code, this parameter has a value of 0.6,

NASA Tech Briefs, December 2008 9