6 ASIC TECHNOLOGY TRENDS OVERVIEW This section will discuss three general trends associated with todayÕs ASIC industry: the rapid advancement of process technologies, the move toward specialization, and a blurring of the dis- tinctions between each of the ASIC product categories. There is also an underlying trend linking these together: each new ASIC generation requires greater cooperation between ASIC vendors and customers. Distinguishing between each of the ASIC product categories is becoming increasingly difficult. Until recently, the ASIC industry could be divided up into the three well-defined product groups defined in Section 1: semicustom ICs (gate arrays and linear arrays), custom ICs (standard cells and full custom devices), and programmable logic devices (simple and complex PLDs, FPGAs, and EPACs). However, the lines separating those three categories are getting blurry. The best fea- tures of products from one category are increasingly showing up in products of other categories. Take, for example, embedded arrays, which are based on a gate array structure but have large megacells such as compiled memories or microprocessor cores embedded in them (Figure 6-1). The cells/cores provide a higher level of integration than a pure gate-array structure, but can lead to longer prototype leadtimes, though, still shorter than the leadtimes for pure cell-based ASICs. Another example of the convergence of ASIC technologies is ActelÕs (co-developed with Synopsys) so-called SPGA (system-programmable gate array), shown in Figure 6-2. Ultimately, Actel will be using combinations of antifuse-, SRAM-, and/or flash-based PLD circuitry, mask- programmable gate array logic, and cell-based cores to serve the diverse ASIC customer base. One thing thatÕs true for all types of ASIC devices is that they are becoming more specialized to serve the needs of systems companies. The ASIC industry is moving away from a one-size-fits-all approach, toward a tighter market focusÑone that places greater emphasis on performance, power, functionality, and cost considerations on a per customer basis. ASICs are no longer just on the periphery of a system (i.e., glue logic), they are being designed as the core of the system. As a result, ASIC vendors are becoming more segmented or specialized in what they have to offer, including such devices as digital video, networking, telecommunications, or audio ASICs. INTEGRATED CIRCUIT ENGINEERING CORPORATION 6-1 ASIC Technology Trends RAM ROM Sea of Gates Array Special Function Serial I/O Source: EDN 19190B Figure 6-1. Typical Embedded Array ASIC (a) (b) Field - Field - Programmable Programmable Logic Logic 66MHz Mask PCI Core Programmable ASIC Datacom Computer Instrumentation • Router • DMA ••• • Data Acquisition • Bridge • Graphics • Image Processing An SPGA could either be standard – an FPGA with widely used cells on chip (a) or customer specific – a combination FPGA and gate array (b). Source: Electronic Products 21735 Figure 6-2. ActelÕs System-Programmable Gate Array (SPGA) To meet their complex chip requirements, ASIC customers are having to rely more on the design groups of ASIC vendors or third-party design houses (see Appendix for listing). This is in con- trast to the past, when it was basically only a matter of drawing up a schematic and sending the design off to be implemented in silicon by an ASIC manufacturer. 6-2 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Technology Trends Additionally, the use of third-party cell/core library providers (e.g., Aspec Technology, Cadence Design Automation, Compass, the Silicon Architects Group of Synopsys, and VLSI Libraries) and foundries is becoming an attractive option for ASIC customers. This strategy is sometimes called customer-owned-tooling (COT) ASIC design. COT customers purchase third-party libraries, create a tape of their mask layout using ASIC and physical design tools, and then take the design to foundries like TSMC and Chartered. Figure 6-3 provides a sampling of companies offering ASIC foundry services. Third-party library firms are attracting not only customers of ASICs, but also vendors of ASICs who may be seeking to broaden their own core libraries. Product Company Technologies Number of Layers Feature Size Metal Pitch Wafer Size Packages Available Commitment Turnaround Time Location Offered (Metal/Poly) Required American Microsystems CMOS 0.5µm 1.2µm 3/1 and 3/2 125mm and All Open-Tooled Packages Negotiable 4-5 Weeks Pocatello, ID 200mm AMCC Bipolar 1.0µm 3.0µm 3/2 100mm Most Standard Packages 50 Wafers 10 Weeks San Diego, CA Per Year California Micro Devices BiCMOS and CMOS BiCMOS—1.5µm 1.2µm and 5.0µm 2/2 125mm and PLCC, DIP, SOIC, SSOP, 1,000 Wafers 3 Weeks Minutes Milpitas, CA CMOS—1.5µm to 5µm 100mm and QSOP Per Year Chartered Semiconductor CMOS 0.6, 0.5, and 0.35µm 0.6µm / 1.6µm 1, 2, 3, or 4 Metal 150mm and BGA—225 to 313 Leads Varies Prototypes—1-2 Milpitas, CA 0.5µm / 1.2µm and 1 or 2 Poly 200mm MQFP—48 to 240 Leads Days Per Mask Layer 0.35µm / 0.9µm TQFP—32 to 208 Leads Production—2 Days 0.25µm / 0.7µm PLCC—44, 68, and 84 Leads Per Mask Layer Thermally Enhanced MQFP Fujitsu Microelectronics CMOS 0.5 and 0.35µm 0.5µm / 1.60µm 0.5µm—3/1 0.5µm—150mm QFP, SQFP, PGA, and BGA Minimum 600 Standard 4-6 Weeks San Jose, CA Contacted 0.35µm—4/1 0.35µm—200mm Wafers Per 0.35µm / 0.25µm Year, Negotiable Contacted IC Works BiCMOS and CMOS BiCMOS—0.6µm BiCMOS—1.5µm 1, 2, or 3 Metal 150mm N/A 500-1,000 3 Weeks San Jose, CA CMOS—0.75µm CMOS—2.0µm 1 or 2 Poly IMP BiCMOS, CMOS, 0.8 to 5µm 2.4µm 2/2 125mm DIP, PLCC, SOIC, SSOP, Negotiable 6 Weeks, Expedite San Jose, CA EECMOS, and High- TSSOP, QFP, and TQFP Available Voltage CMOS Kawasaki LSI USA CMOS CMOS 0.35µm 1.2µm 3/1 150mm DIP, SDIP, QFP, SQFP, 6,000 Wafers 7 Weeks Santa Clara, CA and PGA Per Year Min. LG Semicon America CMOS 0.8, 0.6, 0.5, and 0.8µm / 2.0µm 0.8, 0.6, and 0.8 and 0.6 PLCC, PQFP, TQFP, and BGA Customer Wafers in 4 Weeks San Jose, CA 0.35µm 0.6µm / 1.7µm 0.5µm—3/1 150mm Dependent Assembled and Tested 0.5µm / 1.3µm 0.35µm—4/1 0.5 and 0.35µm in 6 Weeks 0.35µm / 1.0µm 200mm Micrel Semiconductor BiCMOS, Bipolar, Bipolar—1.0µm 6.0µm 2/3 100mm or All None 12-16 Weeks San Jose, CA CMOS, and DMOS CMOS—1.2µm 150mm Mitel Semiconductor CCD and CMOS CCD—2.5µm 2.1µm 2/2 100mm Standard Packages 100 Wafers 10 Weeks Bromont, Quebec, Canada CMOS—1.2µm Per Year Min. Newport Wafer-Fab CMOS 0.5µm 1.6µm 3/2 150mm All High Pin-Count Molded Minimum Lot 2.5 Days Per Mask Palo Alto, CA Packaging (PDIF, QFP, Size of 25 and BGA) Wafers Orbit Semiconductor CCD, CMOS, and 0.6, 0.8, 1.2µm 1.6µm 3/2 150mm Any Commercial 12 Die Process Dependent Sunnyvale, CA CMOS Mixed Signal 2.0 to 5.0µm CMOS DLP 21 Days Raytheon Electronics, Bipolar, Bipolar—4µm Bipolar—11µm. 2 Metal 100mm LCC, DIP, Side Braze, Metal 240 Wafers Bipolar—12 Weeks Semiconductor Division Complementary Cbipolar—2µm Cbipolar—7µm Can, Flat Pack, PGA, all Min. Cbipolar—16 Weeks Mountain View, CA Bipolar, and CBiCMOS—2µm CBiCMOS—7µm Other Packages are with CBiCMOS— 16 Weeks Complementary Subcontract Agreements BiCMOS with Assembly Houses Rockwell Semiconductor GaAs HBT 2.1µm (Emitter Width) 3.6µm min. 3 Metal 100mm Not Offered at this Time Contact 16 Weeks Systems Factory Newport Beach, CA Source: Integrated System Design 23174/23175 Figure 6-3. Foundries INTEGRATED CIRCUIT ENGINEERING CORPORATION 6-3 ASIC Technology Trends Product Company Technologies Number of Layers Feature Size Metal Pitch Wafer Size Packages Available Commitment Turnaround Time Location Offered (Metal/Poly) Required Rohm BiCMOS, CMOS, CMOS and Flash— 1.2µm 4/2 150mm and QFPs and BGAs 3,000 Per 7 Weeks Kyoto, Japan DMOS, FRAM, and 0.35, 0.5, and 0.6µm 200mm Year at 200mm Flash Bipolar—2 to 4µm BiCMOS—0.6 to 1.7µm Semtech (Formerly Bipolar and Metal 4µm 8µm 2 Metal 100mm and Standard Open Tooling 1,200 Wafers PG to Wafer Out— ECI Semiconductor) Gate CMOS 125mm Packages Per Year Min. 14 Weeks Santa Clara, CA Under Purchase Agreement Symbios Logic CMOS 0.35µm (200mm) 1.0µm 4/2 (200mm) and 150mm and PDIP, QFP, TQFP, SOIC, 500 (200mm) 4-8 Weeks Fort Collins, CO and 0.75µm 3/2 (150mm) 200mm PLCC, and BGA and 1,500 (150mm) (150mm) Texas Instruments, 25C10 CMOS—2.5V 25C10.A5L— 25C10.A5L—1.0µm 5 Metal 200mm BGA, CPGA, PPGA, QFP, 3,000 Wafers Process Dependent Advanced Custom CMOS. Timeline 0.25µm (Uncontacted) and and TQFP Per Year and Expedite Fee Products (ACP) 18C07 CMOS—1.8V 18C07.A5L— 1.2µm (Contacted). Required. Prototype Dallas, TX CMOS 0.18µm 18C07.A5L—0.70µm in 30-65 Days (Uncontacted) and 0.85µm (Contacted) Thesys Gesellschaft Fuhr BiCMOS, BiCMOS BiCMOS—0.8µm Metal 1, 0.6µm— 2 or 3 Metal 150mm All Typical Standard 50 Wafers 6 Weeks Mikroelektronik Analog, CMOS, CMOS—0.6µm 1.7µm. Metal 2, 1 or 2 Poly Per Year Erfurt, Germany CMOS Analog, CMOS High 0.6µm—.7µm. and CMOS High Voltage—0.8µm Metal 3, 0.6µm— Voltage 2.3µm. Metal 1, 0.8µm—2.1µm. Metal 2, 0.8µm —2.3µm Tower Semiconductor CMOS and EPROM CMOS—0.8µm, 0.8µm—2.4µm 0.8µm—3/1 150mm All Commercially Available Project 33 Days Migdal Haemek, Israel Capacitor Module 0.6µm—1.6µm 0.6µm—3/2 Dependent CMOS—0.6µm, 0.5µm—1.2µm 0.5µm—3/1 Polycide, Double Poly, EPROM CMOS—0.5µm, Polycide Toshiba America CMOS STD 0.6µm— 1.5 2 or 3 Metal 150mm and PLCC, QFP, PGA, BGA, Negotiable 5-7 Weeks Electronic Components 0.58µm.