Lecture 5: Aldec Active-HDL Simulator
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Co-Simulation Between Cλash and Traditional Hdls
MASTER THESIS CO-SIMULATION BETWEEN CλASH AND TRADITIONAL HDLS Author: John Verheij Faculty of Electrical Engineering, Mathematics and Computer Science (EEMCS) Computer Architecture for Embedded Systems (CAES) Exam committee: Dr. Ir. C.P.R. Baaij Dr. Ir. J. Kuper Dr. Ir. J.F. Broenink Ir. E. Molenkamp August 19, 2016 Abstract CλaSH is a functional hardware description language (HDL) developed at the CAES group of the University of Twente. CλaSH borrows both the syntax and semantics from the general-purpose functional programming language Haskell, meaning that circuit de- signers can define their circuits with regular Haskell syntax. CλaSH contains a compiler for compiling circuits to traditional hardware description languages, like VHDL, Verilog, and SystemVerilog. Currently, compiling to traditional HDLs is one-way, meaning that CλaSH has no simulation options with the traditional HDLs. Co-simulation could be used to simulate designs which are defined in multiple lan- guages. With co-simulation it should be possible to use CλaSH as a verification language (test-bench) for traditional HDLs. Furthermore, circuits defined in traditional HDLs, can be used and simulated within CλaSH. In this thesis, research is done on the co-simulation of CλaSH and traditional HDLs. Traditional hardware description languages are standardized and include an interface to communicate with foreign languages. This interface can be used to include foreign func- tions, or to make verification and co-simulation possible. Because CλaSH also has possibilities to communicate with foreign languages, through Haskell foreign function interface (FFI), it is possible to set up co-simulation. The Verilog Procedural Interface (VPI), as defined in the IEEE 1364 standard, is used to set-up the communication and to control a Verilog simulator. -
Co-Emulation of Scan-Chain Based Designs Utilizing SCE-MI Infrastructure
UNLV Theses, Dissertations, Professional Papers, and Capstones 5-1-2014 Co-Emulation of Scan-Chain Based Designs Utilizing SCE-MI Infrastructure Bill Jason Pidlaoan Tomas University of Nevada, Las Vegas Follow this and additional works at: https://digitalscholarship.unlv.edu/thesesdissertations Part of the Computer Engineering Commons, Computer Sciences Commons, and the Electrical and Computer Engineering Commons Repository Citation Tomas, Bill Jason Pidlaoan, "Co-Emulation of Scan-Chain Based Designs Utilizing SCE-MI Infrastructure" (2014). UNLV Theses, Dissertations, Professional Papers, and Capstones. 2152. http://dx.doi.org/10.34917/5836171 This Thesis is protected by copyright and/or related rights. It has been brought to you by Digital Scholarship@UNLV with permission from the rights-holder(s). You are free to use this Thesis in any way that is permitted by the copyright and related rights legislation that applies to your use. For other uses you need to obtain permission from the rights-holder(s) directly, unless additional rights are indicated by a Creative Commons license in the record and/ or on the work itself. This Thesis has been accepted for inclusion in UNLV Theses, Dissertations, Professional Papers, and Capstones by an authorized administrator of Digital Scholarship@UNLV. For more information, please contact [email protected]. CO-EMULATION OF SCAN-CHAIN BASED DESIGNS UTILIZING SCE-MI INFRASTRUCTURE By: Bill Jason Pidlaoan Tomas Bachelor‟s Degree of Electrical Engineering Auburn University 2011 A thesis submitted -
Download the Compiled Program File Onto the Chip
International Journal of Computer Science & Information Technology (IJCSIT) Vol 4, No 2, April 2012 MPP SOCGEN: A FRAMEWORK FOR AUTOMATIC GENERATION OF MPP SOC ARCHITECTURE Emna Kallel, Yassine Aoudni, Mouna Baklouti and Mohamed Abid Electrical department, Computer Embedded System Laboratory, ENIS School, Sfax, Tunisia ABSTRACT Automatic code generation is a standard method in software engineering since it improves the code consistency and reduces the overall development time. In this context, this paper presents a design flow for automatic VHDL code generation of mppSoC (massively parallel processing System-on-Chip) configuration. Indeed, depending on the application requirements, a framework of Netbeans Platform Software Tool named MppSoCGEN was developed in order to accelerate the design process of complex mppSoC. Starting from an architecture parameters design, VHDL code will be automatically generated using parsing method. Configuration rules are proposed to have a correct and valid VHDL syntax configuration. Finally, an automatic generation of Processor Elements and network topologies models of mppSoC architecture will be done for Stratix II device family. Our framework improves its flexibility on Netbeans 5.5 version and centrino duo Core 2GHz with 22 Kbytes and 3 seconds average runtime. Experimental results for reduction algorithm validate our MppSoCGEN design flow and demonstrate the efficiency of generated architectures. KEYWORD MppSoC, Automatic code generation; mppSoC configuration;parsing ; MppSoCGEN; 1. INTRODUCTION Parallel machines are most often used in many modern applications that need regular parallel algorithms and high computing resources, such as image processing and signal processing. Massively parallel architectures, in particular Single Instruction Multiple Data (SIMD) systems, have shown to be powerful executers for data-intensive applications [1]. -
Simulating Altera Designs
1. Simulating Altera Designs May 2013 QII53025-13.0.0 QII53025-13.0.0 This document describes simulating designs that target Altera® devices. Simulation verifies design behavior before device programming. The Quartus® II software supports RTL and gate level design simulation in third-party EDA simulators. Altera Simulation Overview Simulation involves setting up your simulator working environment, compiling simulation model libraries, and running your simulation. Generate simulation files in an automated or custom flow. Refer to Figure 1–1 and Table 1–3. Figure 1–1. Simulation in Quartus II Design Flow Design Entry (HDL, Qsys, DSP Builder) Altera Simulation RTL Simulation Models Quartus II Design Flow Gate-Level Simulation Post-synthesis functional Post-synthesis Analysis & Synthesis simulation netlist functional simulation EDA Fitter Netlist Post-fit functional Post-fit functional (place-and-route) Writer simulation netlist simulation Post-fit timing TimeQuest Timing Analyzer (Optional)Post-fit timing Post-fit simulation netlist (1) timing simulation simulation (3) Device Programmer (1) Timing simulation is not supported for Arria® V, Cyclone® V, Stratix® V, and newer families. You can use the Quartus II NativeLink feature to automatically generate simulation files and scripts. NativeLink can launch your simulator a from within the Quartus II software. Use a custom flow for more control over all aspects of simulation file generation. © 2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. -
Using Modelsim to Simulate Logic Circuits in Verilog Designs
Using ModelSim to Simulate Logic Circuits in Verilog Designs For Quartus Prime 16.0 1 Introduction This tutorial is a basic introduction to ModelSim, a Mentor Graphics simulation tool for logic circuits. We show how to perform functional and timing simulations of logic circuits implemented by using Quartus Prime CAD software. The reader is expected to have the basic knowledge of the Verilog hardware description language, and the Altera Quartus® Prime CAD software. Contents: • Introduction to simulation • What is ModelSim? • Functional simulation using ModelSim • Timing simulation using ModelSim Altera Corporation - University Program 1 May 2016 USING MODELSIM TO SIMULATE LOGIC CIRCUITS IN VERILOG DESIGNS For Quartus Prime 16.0 2 Background Designers of digital systems are inevitably faced with the task of testing their designs. Each design can be composed of many modules, each of which has to be tested in isolation and then integrated into a design when it operates correctly. To verify that a design operates correctly we use simulation, which is a process of testing the design by applying inputs to a circuit and observing its behavior. The output of a simulation is a set of waveforms that show how a circuit behaves based on a given sequence of inputs. The general flow of a simulation is shown in Figure1. Figure 1. The simulation flow. There are two main types of simulation: functional and timing simulation. The functional simulation tests the logical operation of a circuit without accounting for delays in the circuit. Signals are propagated through the circuit using logic and wiring delays of zero. This simulation is fast and useful for checking the fundamental correctness of the 2 Altera Corporation - University Program May 2016 USING MODELSIM TO SIMULATE LOGIC CIRCUITS IN VERILOG DESIGNS For Quartus Prime 16.0 designed circuit. -
In the United States District Court for the Eastern District of Texas Tyler Division
Case 6:06-cv-00480-LED Document 1 Filed 11/08/06 Page 1 of 8 IN THE UNITED STATES DISTRICT COURT FOR THE EASTERN DISTRICT OF TEXAS TYLER DIVISION NARPAT BHANDARI § § Plaintiff § § v. § Case No. 6:06-cv-480 § CADENCE DESIGN SYSTEMS, INC.; § MAGMA DESIGN AUTOMATION, § INC.; DYNALITH SYSTEMS, INC.; § JURY TRIAL DEMANDED ALTERA CORP.; MENTOR GRAPHICS § CORP.; AND ALDEC, INC. § § Defendants § § § § § PLAINTIFF’S ORIGINAL COMPLAINT Plaintiff, Narpat Bhandari (“Bhandari”), files this Original Complaint against Defendants, Cadence Design Systems, Inc. (“Cadence”), Magma Design Automation, Inc. (“Magma”), Dynalith Systems, Inc. (“Dynalith”), Altera Corp. (“Altera”), Mentor Graphics Corp. (“Mentor”), and Aldec, Inc. (“Aldec”) and alleges as follows: THE PARTIES 1. Bhandari is an individual who resides at 14530 Deer Park Court, Los Gatos, CA 95032. 2. Cadence, on information and belief, is a corporation organized under the laws of the State of Delaware. Cadence is doing business in Texas, and, on information and belief, has a principal place of business at 2655 Seely Ave, Building 5, San Jose, CA 95134-1931. Case 6:06-cv-00480-LED Document 1 Filed 11/08/06 Page 2 of 8 Cadence may be served with process by serving its registered agent, CT Corp System at 350 N. St. Paul Street, Dallas, TX 75201. 3. Magma, on information and belief, is a corporation organized under the laws of the State of Delaware. Magma is doing business in Texas, and, on information and belief, has a principal place of business at 5460 Bayfront Plaza, Santa Clara, CA 95054. Magma may be served with process by serving its registered agent, Corporation Service Company, d/b/a CSC-Lawyers Incorporating Service Company at 701 Brazos Street Suite 1050, Austin, TX 78701. -
Quartus Prime Standard Edition Handbook Volume 3: Verification
Quartus Prime Standard Edition Handbook Volume 3: Verification Subscribe QPS5V3 101 Innovation Drive 2015.11.02 San Jose, CA 95134 Send Feedback www.altera.com Simulating Altera Designs 1 2015.11.02 QPS5V3 Subscribe Send Feedback This document describes simulating designs that target Altera devices. Simulation verifies design behavior before device programming. The Quartus® Prime software supports RTL- and gate-level design simulation in supported EDA simulators. Simulation involves setting up your simulator working environ‐ ment, compiling simulation model libraries, and running your simulation. Simulator Support The Quartus Prime software supports specific EDA simulator versions for RTL and gate-level simulation. Table 1-1: Supported Simulators Vendor Simulator Version Platform Aldec Active-HDL 10.2 Update 2 Windows Aldec Riviera-PRO 2015.06 Windows, Linux Cadence Incisive Enterprise 14.2 Linux Mentor ModelSim-Altera (provided) 10.4b Windows, Linux Graphics Mentor ModelSim PE 10.4b Windows Graphics Mentor ModelSim SE 10.4b Windows, Linux Graphics Mentor QuestaSim 10.4b Windows, Linux Graphics Synopsys VCS/VCS MX 2014,12-SP1 Linux Simulation Levels The Quartus Prime software supports RTL and gate-level simulation of IP cores in supported EDA simulators. © 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any 9001:2008 products and services at any time without notice. -
Xilinx Xcell 25
Issue 25 Second Quarter 1997 THE QUARTERLYX JOURNALCELL FOR XILINX PROGRAMMABLE LOGIC USERS R PRODUCT INFORMATION The Programmable Xilinx Delivers Next Logic CompanySM Generation Platform Inside This Issue: The new XACTstep version M1 release enables GENERAL The Fawcett - FPGAs, Power users to increase design performance while & Packages .......................................... 2 leveraging high-level design methodologies ... Guest Editorial: See pages 12 & 19 HardWire and PCI LogiCOREs ...... 3 Customer Success Story ...................... 5 WebLINX Enhancements .................... 6 XC4000 Series: The World’s “Power of Innovation” Seminars ...... 7 Technical Training Update ................. 7 Upcoming Events .................................. 8 Largest and Fastest FPGAs New Product Literature ....................... 8 The world’s highest-capacity FPGA, the XC4085XL, Financial Results .................................... 8 begins sampling as the world’s highest-performance PRODUCTS FPGAs, the XC4000E-1 family, move into production ... XC4000E-1 Speed Grade .................... 9 See Pages 9 & 11 XC95288 CPLD in Production ........ 10 XC4085XL Now Largest FPGA ....... 11 New 64,000-Gate XC6264 .............. 11 DESIGN TIPS & HINTS DEVELOPMENT SYSTEMS XACTstep M1 Software Released .. 12 Xilinx Shipping Cadence Interface . 13 XC9500 CPLD CORE Generator for PCI .................. 14 DSP CORE Generator ........................ 15 Programming HINTS & ISSUES Simple XC9500 CPLD Guidelines Programming Guidelines ............... 16 To reap -
Cyberworkbench® High-Level Synthesis and Verification By
CyberWorkBench® High-Level Synthesis and Verification by: SystemC ANSI-C High-Level Synthesis and Verification CyberWorkBench® enables higher design efficiency, low power Source Code Debugger and high performance of the chip by allowing designers to Behavioral Synthesizer implement hardware at the algorithmic level. This “All-in-C” Property Checker Behavioral Simulator high-level synthesis and verification tool set for ASIC and FPGAs Library Characterizer Cycle Level Simulator C-RTL (Xilinx/Altera) reduces the development time and cost Equivalence Prover QoR Analyzer Testbench Generator significantly. Formal Verification High-Level Synthesis Simulation Designers can describe hardware at higher abstraction level using SystemC and ANSI-C and using CyberWorkBench they can generate highly optimized RTL for their ASIC and FPGAs RTL (Xilinx/Altera) chip. Automatic pipelining, power optimization and powerful parallelism extraction allows designers to ASIC FPGA generate smaller and low power designs compared to manual RTL design approach. “All-in-C” Synthesis Behavioral synthesizer in CyberWorkBench can synthesize any Top Benef its type of application including control dominated circuits and datapath. This best-in-class high-level synthesizer features • Support for both control dominated circuits and automatic pipelining, power optimization and powerful datapath module parallelism extraction to reduce chip area and power through maximum resource sharing. Designers with IP/RTL legacy Dedicated technology support for Altera® & Xilinx® • modules can use top level structural description generator FPGAs and can easily connect to C-based modules. To improve • Best-in-class High-Level Synthesizer that features the design productivity CyberWorkBench also includes automatic pipelining, power optimization, powerful numerous behavioral IPs that can be retargeted to different parallelism extraction implementation technologies or system requirements. -
Starting Active-HDL As the Default Simulator in Xilinx
7/29/13 Support - Resources - Documentation - Application Notes - Aldec 日本語 Sign In | Register Search aldec.com SOLUTIONS PRODUCTS EVENTS COMPANY SUPPORT DOWNLOADS Home Support Resources Documentation Application Notes RESOURCES Starting Active-HDL as the Default Simulator in Xilinx ISE « Prev | Next » Documentation Application Notes Introduction FAQ This document describes how to start Active-HDL simulator from Xilinx ISE Project Navigator to run behavioral and timing simulations. This Manuals application note has been verified on Active-HDL 9.1 and Xilinx ISE 13.4. This interface allows users to run mixed VHDL, Verilog and White Papers System Verilog (design ) simulation using Active-HDL as a default simulator. Tutorials Installing Xilinx libraries in Active-HDL Multimedia Demonstration In order to run the simulation successfully, depending on the design both VHDL and Verilog libraries for Xilinx may have to be installed in Videos Active-HDL. You can check what libraries are currently installed in your Active-HDL using Library Manager tool. You can access the Library Manager from the menu View>Library Manger>. Recorded Webinars You can install precompiled libraries in multiple ways: 1. If you are using Active-HDL DVD to install the software, during the installation, you will get the option to select and install the Xilinx libraries 2. If you have received a web link to download Active-HDL, on the same page you will find the links to download Xilinx libraries. 3. At any time you can visit the update center to download the latest Xilinx libraries at http://www.aldec.com/support Set Active-HDL as Simulator in Xilinx Project Navigator After creating a project, open your Xilinx project in ISE Project Navigator. -
Riviera-PRO 2012.06
R e l e a s e N o t e s Riviera-PRO 2012.06 Release Notes www.aldec.com This page is intentionally left blank. TABLE OF CONTENTS Table of Contents Release Notes for Riviera-PRO 2012.06 ...................................................................................................... 4 What's New ............................................................................................................................................. 4 Performance Improvements ............................................................................................................... 4 SystemVerilog Simulation ................................................................................................................... 4 OVM and UVM Libraries ..................................................................................................................... 5 DPI Interface ....................................................................................................................................... 5 Mixed VHDL and SystemVerilog Simulation ....................................................................................... 5 VCD Files ........................................................................................................................................... 6 Interface to SystemVue ...................................................................................................................... 6 Macro Commands ............................................................................................................................. -
Introduction to Simulation of VHDL Designs Using Modelsim Graphical Waveform Editor
Introduction to Simulation of VHDL Designs Using ModelSim Graphical Waveform Editor For Quartus II 13.1 1 Introduction This tutorial provides an introduction to simulation of logic circuits using the Graphical Waveform Editor in the ModelSim Simulator. It shows how the simulator can be used to perform functional simulation of a circuit specified in VHDL hardware description language. It is intended for a student in an introductory course on logic circuits, who has just started learning this material and needs to acquire quickly a rudimentary understanding of simulation. Contents: • Design Project • Creating Waveforms for Simulation • Simulation • Making Changes and Resimulating • Concluding Remarks Altera Corporation - University Program 1 October 2013 INTRODUCTION TO SIMULATION OF VHDL DESIGNS USING MODELSIM GRAPHICAL WAVEFORM EDITOR For Quartus II 13.1 2 Background ModelSim is a powerful simulator that can be used to simulate the behavior and performance of logic circuits. This tutorial gives a rudimentary introduction to functional simulation of circuits, using the graphical waveform editing capability of ModelSim. It discusses only a small subset of ModelSim features. The simulator allows the user to apply inputs to the designed circuit, usually referred to as test vectors, and to observe the outputs generated in response. The user can use the Waveform Editor to represent the input signals as waveforms. In this tutorial, the reader will learn about: • Test vectors needed to test the designed circuit • Using the ModelSim Graphical Waveform Editor to draw test vectors • Functional simulation, which is used to verify the functional correctness of a synthesized circuit This tutorial is aimed at the reader who wishes to simulate circuits defined by using the VHDL hardware description language.