Ph.D. Candidate CSE Dept., SUNY at Buffalo

Ph.D. Candidate CSE Dept., SUNY at Buffalo    Introduction  Verilog Programming on Windows  Verilog Programming on Linux  Example 1: Swap Values  Example 2: 4-Bit Binary Up-Counter  Summary  X-Win32 2010 Installation Guide  References

 Verilog o A commonly used hardware description language (HDL) o Organizes hardware designs into modules  Icarus Verilog o An open-source compiler/simulator/synthesis tool • Available for both Windows and linux o Operates as a compiler • Compiling source code written in Verilog (IEEE-1364) into some target format o For batch simulation, the compiler can generate an intermediate form called vvp assembly • Executed by the command, “vvp” o For synthesis, the compiler generates netlists in the desired format  Other Tools o Xilinx’s WebPack & ModelSim o Altera’s Quartus

4/2/2012 (c) 2012 Jaehan Koh 4  Downloading and Installing Software o Icarus Verilog for Windows • Download Site: http://bleyer.org/icarus/  Edit source code using a text editor o Notepad, Notepad++, etc  Compiling Verilog code o Type “iverilog –o xxx_out.vvp xxx.v xxx_tb.v”  Running the simulation o Type “vvp xxx_out.vvp”  Viewing the output o Type “gtkwave xxx_out.vcd” o An output waveform waveform file xxx_out.vcd (“value change dump”) can be viewed by gtkwave under Linux/Windows.

4/2/2012 (c) 2012 Jaehan Koh 5  Icarus Verilog under CSE Systems o Have access to [timberlake] remotely using • [X-Win 2010] software • [Cygwin] software  How to check if the required software is installed • Type “where iverilog” • Type “where vvp”  Edit source code using a text editor o Vim, emacs, etc.  Compiling Verilog code o Type “iverilog –o xxx_out.vvp xxx.v xxx_tb.v”  Running the simulation o Type “vvp xxx_out.vvp”

4 4 IN 0 0 OUT

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module swapvals(IN, OUT); module swapvals_tb; input [3:0] IN; reg [3:0] IN = 4'b0101; output [3:0] OUT; wire [3:0] OUT;

// swap the input bits initial assign OUT ={IN[2],IN[3],IN[0],IN[1]}; begin endmodule $dumpfile("swapvals.vcd"); $dumpvars(0, s); $monitor("IN=[%b], OUT=[%b].",IN,OUT); #100 IN = 4'b0011; #100 $finish; end

swapvals s(IN, OUT); endmodule

4/2/2012 (c) 2012 Jaehan Koh 8  How to compile code o iverilog -o swapvals.vvp swapvals.v swapvals_tb.v  How to run the simulation o vvp simple.vvp  How to view the output using GTKWave program o gtkwave swapvals.vcd

C:\iverilog\bin>vvp swapvals.vvp VCD info: dumpfile swapvals.vcd opened for output. IN=[0101], OUT=[1010]. IN=[0011], OUT=[0011]. C:\iverilog\bin>gtkwave swapvals.vcd

GTKWave Analyzer v3.3.0 (w)1999-2009 BSI

4 0 OUT

4/2/2012 (c) 2012 Jaehan Koh 10 `timescale 1ns/1ns  Code module fourbit_up_counter_tb; reg clk; reg reset; module fourbit_up_counter(clk,q,reset); wire [3:0] q; input clk; input reset; fourbit_up_counter output reg [3:0] q; instance0(.clk(clk),.q(q),.reset(reset)); initial initial begin begin clk = 1'b0; q=4'b0000; reset = 1'b1; end #10 reset = 1'b0; #1000 ; always@(posedge clk) $finish; begin end if (reset==1'b1) initial q=4'b0000; begin else forever #20 clk = ~clk; q=q+1; end end initial endmodule begin $monitor("Time = [%t]ns, Q = [%b]",$time,q); end endmodule 4/2/2012 (c) 2012 Jaehan Koh 11 C:\iverilog\bin>vvp fourbit_up_counter.vvp  How to compile code Time = [ 0]ns, Q = [0000] Time = [ 20]ns, Q = [0001] o C:\iverilog\bin>iverilog -o Time = [ 60]ns, Q = [0010] Time = [ 100]ns, Q = [0011] fourbit_up_counter.vvp Time = [ 140]ns, Q = [0100] fourbit_up_counter.v Time = [ 180]ns, Q = [0101] Time = [ 220]ns, Q = [0110] fourbit_ Time = [ 260]ns, Q = [0111] Time = [ 300]ns, Q = [1000] o up_counter_tb.v Time = [ 340]ns, Q = [1001] Time = [ 380]ns, Q = [1010]  How to run the simulation Time = [ 420]ns, Q = [1011] Time = [ 460]ns, Q = [1100] o vvp simple.vvp Time = [ 500]ns, Q = [1101] Time = [ 540]ns, Q = [1110] Time = [ 580]ns, Q = [1111] Time = [ 620]ns, Q = [0000] Time = [ 660]ns, Q = [0001] Time = [ 700]ns, Q = [0010] Time = [ 740]ns, Q = [0011] Time = [ 780]ns, Q = [0100] Time = [ 820]ns, Q = [0101] Time = [ 860]ns, Q = [0110] Time = [ 900]ns, Q = [0111] Time = [ 940]ns, Q = [1000] 4/2/2012 (c) 2012 Jaehan Koh Time = [ 980]ns, Q = [1001]  Icarus Verilog is a Verilog simulation and synthesis tool  You can download and run it under different platforms  You can perform simulation by using Xilinx WebPack software

4/2/2012 (c) 2012 Jaehan Koh 13  Download the Software o Visit http://ubit.buffalo.edu/software/ o Go to [Windows software]  [Software downloads]. o Download the file [win_xwin32-2010_xxxx.exe]. o You will be asked to log in for downloading.

4/2/2012 (c) 2012 Jaehan Koh 16  Icarus Verilog, http://iverilog.icarus.com/.  Matt Zucker, “Icarus Verilog,” Swarthmore College, http://www.swarthmore.edu/NatSci/mzucker1/e15/iverilo g-instructions.html.  Wikipedia, “Icarus Verilog,” http://en.wikipedia.org/wiki/Icarus_Verilog.