Intro to Verilog

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Intro to Verilog Verilog History I Developed by Gateway Design Automation (1984) I Proprietary hardware simulation and verification tool only I Influenced by HiLo (old HDL language) and C I Fault simulation, timing analyzer and synthesis ready 1987 I Cadence Design Systems bought Gateway (and Verilog) in 1990 I Cadence marketed it as a language and simulator, Verilog-XL Intro to Verilog Verilog History(cont.) I VHDL influence I VHDL driven by DOD VHSIC program I Based on Ada I Vhsic Hardware Design Language = VHDL I Cadence recognized a closed language was doomed I Standardization would win the day eventually I Cadence organized Open Verilog International (OVI) and gave language away I Others were trying to alter the language for their benefit I IEEE 1364 working group made Verilog IEEE std. 1364-1995 I Verilog 95 finished in 1995 (duh!) Intro to Verilog Verilog History(cont.) I Other Verilog simulators than Cadence Verilog-XL available (1992) I Verilog Compiled Simulator (VCS) from Chronologic: very successful I VCS eventually bought by Synopsys I Modelsim (Mentor), a very good mixed language simulator I The big three simulators (all sign-off quality) are: I Modelsim [Mentor] I NC-Verilog [Cadence] (derived from Verilog-XL) I VCS [Synopsys] (derived from Chronologic VCS) I Icarus Verilog [open source] (not fully 1356-2001 compliant) Intro to Verilog Verilog History(cont.) I Verilog 2001 fixed many shortcomings Verilog 95 had I System Verilog is a super-set of Verilog 2001 I System Verilog born from the need to unify design and verification I Adds VHDL features and design verification improvements I Both Verilog and VHDL have analog extensions VHDL-A and Verilog-AMS Intro to Verilog Verilog and VHDL Compared Verilog VHDL Weakly typed Strongly typed Looks like C Looks like Ada (Pascal) Case sensitive Case insensitive Terse Verbose Design by a few Design by committee Used all over Mandated by government Easy to learn Harder to learn Easy to screw up Holds your hand closely.

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