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Welcome to 6.111! Hardware – Nothing in the Cloud 6.111 Introductory Digital Systems Lab • Learn digital systems through lectures, labs and a final project using FPGAs and Verilog. • Gain experience with hands on course with real Welcome to 6.111! hardware – nothing in the cloud. • Introductions, course mechanics Handouts • 6.111 satisfies • Course overview • lecture slides, – Course 6: DLAB2, II, EECS, AUS2 • Digital signaling • LPset #1, • info form – Course 16: Laboratory requirement, Professional Area • Combinational logic subject Lecture material: Prof Anantha Chandrakasan and Dr. Chris Terman. Lecture 1 6.111 Fall 2019 1 Lecture 1 6.111 Fall 2019 2 Introductions 38-600 Lab hours: S 1-11:45p M-R 9-11:45p 49 Stations F 9-5p Stata 38-644 Conference GH room Gim Hom Joe Steinmeyer Sarah Flanagan Mike Wang Diana Wofk TA Lectures Lectures TA TA Sam Cherna Isabelle Liu Lydia SunMark Theng August Trollback LA’s Lecture 1 6.111 Fall 2019 3 Lecture 1 6.111 Fall 2019 4 Course Website: web.mit.edu/6.111 Assignments - Grading Lab: 38-600 Participation Presentation 2% Lecture & report Problems 13% 16% Announcements, updates, etc Technical information and data sheet Online copies of lecture notes, lpsets and labs Final project info On‐line grades Labs 34% * PDF submissions Final Project 35% Verilog submissions Policies and important dates A large number of students do "A" level work and are, indeed, rewarded Tools with a grade of "A". The corollary to this is that, since average On‐line Q&A performance levels are so high, punting any part of the subject can lead to a disappointing grade. Lecture 1 6.111 Fall 2019 5 Lecture 1 6.111 Fall 2019 6 Labs: learning the ropes Final Project • Lab 1 (2%) • Grading: 35% – Experiment with gates, design & implement some logic with FPGA – Learn about simulation and using Verilog design suite: Vivado • Done in groups of two or three; one person project by exception • Lab 2 (5%) • Open-ended – Introduction to clocks, counters and more hardware • You and the staff negotiate a project proposal – Serial communications • Lab 3 (8%) – Must emphasize digital concepts, but inclusion of analog interfaces – Video circuits: a simple Pong game (e.g., data converters, sensors or motors) common and often desirable • Use Verilog to program an FPGA – Proposal Conference, several Design Reviews • Display images – Have fun! • Lab 4 (11%) – Design and implement a Finite State Machine (FSM) – Car Alarm • Design presentation to staff • Staff will provide help with project definition and scope, design, • Lab 5 (8%) – Design a complicated system with multiple FSMs (Major/Minor FSM) debugging, and testing • Audio processing • It is extremely difficult for a student to receive an A without • Digital bubble level using IMU completing the final project. Sorry, but we don’t give incompletes. • You must have a non-zero score for each of the labs and all the labs must be checked off as a prerequisite for passing the course. A missing lab will result in a failing grade. Lecture 1 6.111 Fall 2019 7 Lecture 1 6.111 Fall 2019 8 Virtual Pool – La PC Na Project Presentation & Report (13%) • Design proposal (2%) Fall 2016 Matt Basile • Design presentation (6%) Zareen Choudhury • Final Report (5%) Lecture 1 6.111 Fall 2019 10 FPGA Beethoven Virtual Softball Fall 2016: Henry Love, Mark Yang Fall 2017 Katherine Shade, Melinda Szabo Lecture 1 6.111 Fall 2019 11 Lecture 1 6.111 Fall 2019 12 FPGA Passport Gesture Controlled Drone Fall 2016 Lorenzo Vigano, Diana Wofk Fall 2014 Lee Gross, Ben Schrenk Lecture 1 6.111 Fall 2019 13 Lecture 1 6.111 Fall 2019 14 6.111 Topics Collaboration • Combinational logic Digital • Sequential Logic Building Blocks • Memories • Labs and lpset must be done independently but students & Architecture • Performance issues may seek help from other students and of course staff. •… • Work submitted for review must be your own Design Implementation Methodologies Technologies & Tools • Design metrics • FPGAs • HDL: Verilog, System Verilog • Flash, ram • Simulation tools • ADC, DAC, • Synthesis, Place & Route • Sensors … •… Lecture 1 6.111 Fall 2019 15 Lecture 1 6.111 Fall 2019 16 Boolean Algebra Key Link Between Logic and Circuits (The Vacuum Tube) 0 AND OR NOT 0 1 0 0 1 + 0 0 1 0 0 0 0 0 0 1 01 1 1 Lee de Forest, 1906 1 1 0 1 10 0 0 Digital 1 1 Electronics 1 1 1 1 • Despite existence of relays and introduction of vacuum tube in 1906, digital electronics did not emerge for thirty years! • 1854: George Boole shows that logic is math, not just • Claude Shannon notices similarities between Boolean algebra and philosophy! electronic telephone switches • Boolean algebra: the mathematics of binary values • Shannon’s 1937 MIT Master’s Thesis introduces the world to binary digital electronics Lecture 1 6.111 Fall 2019 17 Lecture 1 6.111 Fall 2019 18 Evolution of Digital Electronics Digital Systems Thru the Ages Vacuum Tubes Transistors VLSI Circuits Vacuum tube computer Circa 1950 IBM 1401 Computer First Transistor 4004, 1971 Circa 1962 ENIAC, 1946 Bell Labs, 1948 DEC PDP 11 Circa 1980 Intel Cascade Lake UNIVAC, 1951 IBM System/360, 1964 2018 - 22 Cores >>7 Billion 14nm 1900 adds/sec 500,000 adds/sec Lecture 1 6.111 Fall 2019 20 6.111 Thru the Ages 6.111 Evolution Fall 1969 Fall 2019 Introduces digital systems with lectures and labs on logic, flip flops, FPGAs, counters, timing, Lab kit 1990 aka “digital death” Labkit 2005 synchronization, and finite-state machines. Includes overview of accelerometers, gyros, time of light and other modern sensors. Prepares students for the design and implementation of a final project of their choice: games, music, digital filters, wireless communications, video, or graphics. Extensive use of Verilog for describing and implementing digital logic designs. Nexys 4 - 2016 PYNQ - 2019 Lecture 1 6.111 Fall 2019 21 6.111 Fall 2016 6.111 Fall 2019 22 The trouble with analog signaling Music at MIT circa 1970s The real world is full of continuous-time continuous-value (aka “analog”) signals created by physical processes: sound vibrations, light fields, voltages and currents, phase and amplitudes, … But if we build processing elements to manipulate these signals we must use non-ideal components in real-world environments, so some amount of error (aka “noise”) is Processing introduced. The error comes from component tolerances, Element electrical phenomenon (e.g., IR and LdI/dt effects), transmission losses, thermal noise, etc. Facts of life that can’t be avoided… Need an architecture that is noise tolerant, inexpensive, And the more analog processing we do, the worse it gets: reproducible. signaling errors accumulate in analog systems since we can’t tell from looking at signal which wiggles were there to begin with and which got added during processing. Lecture 1 6.111 Fall 2019 23 Lecture 1 6.111 Fall 2019 24 Solution: go digital! The Digital Abstraction Noise and inaccuracy are inevitable; we can’t reliably engineer perfect components – we must design our system to tolerate some amount of error if it is to process information reliably. Continuous values “Ideal” Digital World Continuous time Real Analog World 0/1 Manufacturing Variations So we can detect small Noise Bits changes and restore original values Volts or Electrons or Discrete values Ergs or Gallons Discrete time Keep in mind that the world is not digital, we would simply like to So we don’t look engineer it to behave that way. Furthermore, we must use real physical while it’s changing phenomena to implement digital designs! Lecture 1 6.111 Fall 2019 25 Lecture 1 6.111 Fall 2019 26 Digital Encoding Digital processing elements To ensure we can distinguish signal from noise, we’ll encode information using a fixed set of discrete values. Options are: “D” Digital processing elements restore noisy input voltages phase values to legal output values – signaling errors currents frequency -N +N don’t accumulate in digital systems. So the number IN of processing elements isn’t limited by noise problems! For 6.111, we’ll use voltages to encode information. Current, phase Processing and frequency encoding have uses in other applications. The “trick” is that we’ve defined our signaling Element convention so that we can tell from looking at a signal which wiggles were there to begin with and Why voltage? which got added during processing. easily generated, well understood “D” historically used, lots of circuits We’ll keep things simple by designing our -N +N with CMOS, almost zero power in steady state processing elements to use voltages to encode OUT binary values (0 or 1). No free lunch: noise sensitivity, non-ideal wires (RC time constant), Lecture 1 6.111 Fall 2019 27 Lecture 1 6.111 Fall 2019 28 Using voltages to encode binary values Digital Signaling Specification To avoid hard-to-make decisions at the boundaries between voltages, insert a “forbidden zone” between levels. To ensure ’ robust operation we d like to make the noise margins as large as Digital input: VIN < VIL or VIN > VIH possible. 0OUT 1OUT Digital output: VOUT < VOL or VOUT > VOH OUTPUTS: Forbidden Zone Noise margins: VIL−VOL and VOH −VIH volts 0 VOL VOH VDD Where VOL, VIL, VIH and VOH are part of the 0IN 1IN specification for a particular family of digital components. INPUTS: Forbidden Zone volts Now that we have a way of encoding information as 0 V V V V V OL IL IH OH DD a signal, we can define what it means to be digital device. Noise Margins Lecture 1 6.111 Fall 2019 29 Lecture 1 6.111 Fall 2019 30 Sample DC (signaling) Specification Arduino Processor DC Specification Source: Xilinx Virtex 5 Datasheet Source: ATmega328P Datasheet
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