6.111 Introductory Digital Systems Lab

• Learn digital systems through lectures, labs and a final project using FPGAs and Verilog.

• Gain experience with hands on course with real Welcome to 6.111! hardware – nothing in the cloud.

• Introductions, course mechanics Handouts • 6.111 satisfies • Course overview • lecture slides, – Course 6: DLAB2, II, EECS, AUS2 • Digital signaling • LPset #1, • info form – Course 16: Laboratory requirement, Professional Area • Combinational logic subject

Lecture material: Prof Anantha Chandrakasan and Dr. Chris Terman.

Lecture 1 6.111 Fall 2019 1 Lecture 1 6.111 Fall 2019 2

Introductions 38-600 Lab hours: S 1-11:45p M-R 9-11:45p 49 Stations F 9-5p Stata

38-644 Conference GH room Gim Hom Joe Steinmeyer Sarah Flanagan Mike Wang Diana Wofk TA Lectures Lectures TA TA

Sam Cherna Isabelle Liu Lydia SunMark Theng August Trollback

LA’s

Lecture 1 6.111 Fall 2019 3 Lecture 1 6.111 Fall 2019 4 Course Website: web.mit.edu/6.111 Assignments - Grading Lab: 38-600 Participation Presentation 2% Lecture & report Problems 13% 16% Announcements, updates, etc

Technical information and data sheet

Online copies of lecture notes, lpsets and labs

Final project info

On‐line grades Labs 34% *

PDF submissions Final Project 35% Verilog submissions

Policies and important dates A large number of students do "A" level work and are, indeed, rewarded Tools with a grade of "A". The corollary to this is that, since average On‐line Q&A performance levels are so high, punting any part of the subject can lead to a disappointing grade.

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Labs: learning the ropes Final Project

• Lab 1 (2%) • Grading: 35% – Experiment with gates, design & implement some logic with FPGA – Learn about simulation and using Verilog design suite: Vivado • Done in groups of two or three; one person project by exception • Lab 2 (5%) • Open-ended – Introduction to clocks, counters and more hardware • You and the staff negotiate a project proposal – Serial communications • Lab 3 (8%) – Must emphasize digital concepts, but inclusion of analog interfaces – Video circuits: a simple Pong game (e.g., data converters, sensors or motors) common and often desirable • Use Verilog to program an FPGA – Proposal Conference, several Design Reviews • Display images – Have fun! • Lab 4 (11%) – Design and implement a Finite State Machine (FSM) – Car Alarm • Design presentation to staff • Staff will provide help with project definition and scope, design, • Lab 5 (8%) – Design a complicated system with multiple FSMs (Major/Minor FSM) debugging, and testing • Audio processing • It is extremely difficult for a student to receive an A without • Digital bubble level using IMU completing the final project. Sorry, but we don’t give incompletes.

• You must have a non-zero score for each of the labs and all the labs must be checked off as a prerequisite for passing the course. A missing lab will result in a failing grade.

Lecture 1 6.111 Fall 2019 7 Lecture 1 6.111 Fall 2019 8 Virtual Pool – La PC Na Project Presentation & Report (13%)

• Design proposal (2%) Fall 2016 Matt Basile • Design presentation (6%) Zareen Choudhury

• Final Report (5%)

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FPGA Beethoven Virtual Softball

Fall 2016: Henry Love, Mark Yang Fall 2017 Katherine Shade, Melinda Szabo

Lecture 1 6.111 Fall 2019 11 Lecture 1 6.111 Fall 2019 12 FPGA Passport Gesture Controlled Drone

Fall 2016 Lorenzo Vigano, Diana Wofk Fall 2014 Lee Gross, Ben Schrenk

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6.111 Topics Collaboration • Combinational logic Digital • Sequential Logic Building Blocks • Memories • Labs and lpset must be done independently but students & Architecture • Performance issues may seek help from other students and of course staff. •…

• Work submitted for review must be your own

Design Implementation Methodologies Technologies & Tools

• Design metrics • FPGAs • HDL: Verilog, System Verilog • Flash, ram • Simulation tools • ADC, DAC, • Synthesis, Place & Route • Sensors … •…

Lecture 1 6.111 Fall 2019 15 Lecture 1 6.111 Fall 2019 16 Boolean Algebra Key Link Between Logic and Circuits

(The Vacuum Tube)

0 AND OR NOT 0 1 0 0 1 + 0 0 1 0 0 0 0 0 0 1 01 1 1 Lee de Forest, 1906

1 1 0 1 10 0 0 Digital

1 1 Electronics 1 1 1 1

• Despite existence of relays and introduction of vacuum tube in 1906, digital electronics did not emerge for thirty years! • 1854: George Boole shows that logic is math, not just • Claude Shannon notices similarities between Boolean algebra and philosophy! electronic telephone switches • Boolean algebra: the mathematics of binary values • Shannon’s 1937 MIT Master’s Thesis introduces the world to binary digital electronics

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Evolution of Digital Electronics Digital Systems Thru the Ages Vacuum Tubes Transistors VLSI Circuits

Vacuum tube computer Circa 1950

IBM 1401 Computer First Transistor 4004, 1971 Circa 1962 ENIAC, 1946 Bell Labs, 1948

DEC PDP 11 Circa 1980 Intel Cascade Lake UNIVAC, 1951 IBM System/360, 1964 2018 - 22 Cores >>7 Billion 14nm 1900 adds/sec 500,000 adds/sec

Lecture 1 6.111 Fall 2019 20 6.111 Thru the Ages 6.111 Evolution

Fall 1969 Fall 2019

Introduces digital systems with lectures and labs on logic, flip flops, FPGAs, counters, timing, Lab kit 1990 aka “digital death” Labkit 2005 synchronization, and finite-state machines. Includes overview of accelerometers, gyros, time of light and other modern sensors. Prepares students for the design and implementation of a final project of their choice: games, music, digital filters, wireless communications, video, or graphics. Extensive use of Verilog for describing and implementing digital logic designs.

Nexys 4 - 2016 PYNQ - 2019

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The trouble with analog signaling Music at MIT circa 1970s

The real world is full of continuous-time continuous-value (aka “analog”) signals created by physical processes: sound vibrations, light fields, voltages and currents, phase and amplitudes, …

But if we build processing elements to manipulate these signals we must use non-ideal components in real-world environments, so some amount of error (aka “noise”) is Processing introduced. The error comes from component tolerances, Element electrical phenomenon (e.g., IR and LdI/dt effects), transmission losses, thermal noise, etc. Facts of life that can’t be avoided… Need an architecture that is noise tolerant, inexpensive, And the more analog processing we do, the worse it gets: reproducible. signaling errors accumulate in analog systems since we can’t tell from looking at signal which wiggles were there to begin with and which got added during processing.

Lecture 1 6.111 Fall 2019 23 Lecture 1 6.111 Fall 2019 24 Solution: go digital! The Digital Abstraction Noise and inaccuracy are inevitable; we can’t reliably engineer perfect components – we must design our system to tolerate some amount of error if it is to process information reliably. Continuous values “Ideal” Digital World Continuous time Real Analog World 0/1 Manufacturing Variations So we can detect small Noise Bits changes and restore original values Volts or Electrons or Discrete values Ergs or Gallons Discrete time Keep in mind that the world is not digital, we would simply like to So we don’t look engineer it to behave that way. Furthermore, we must use real physical while it’s changing phenomena to implement digital designs!

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Digital Encoding Digital processing elements

To ensure we can distinguish signal from noise, we’ll encode information using a fixed set of discrete values. Options are: “D” Digital processing elements restore noisy input voltages phase values to legal output values – signaling errors currents frequency -N +N don’t accumulate in digital systems. So the number IN of processing elements isn’t limited by noise problems! For 6.111, we’ll use voltages to encode information. Current, phase Processing and frequency encoding have uses in other applications. The “trick” is that we’ve defined our signaling Element convention so that we can tell from looking at a signal which wiggles were there to begin with and Why voltage? which got added during processing. easily generated, well understood “D” historically used, lots of circuits We’ll keep things simple by designing our -N +N with CMOS, almost zero power in steady state processing elements to use voltages to encode OUT binary values (0 or 1). No free lunch: noise sensitivity, non-ideal wires (RC time constant),

Lecture 1 6.111 Fall 2019 27 Lecture 1 6.111 Fall 2019 28 Using voltages to encode binary values Digital Signaling Specification To avoid hard-to-make decisions at the boundaries between voltages, insert a “forbidden zone” between levels. To ensure ’ robust operation we d like to make the noise margins as large as Digital input: VIN < VIL or VIN > VIH possible.

0OUT 1OUT Digital output: VOUT < VOL or VOUT > VOH

OUTPUTS: Forbidden Zone Noise margins: VIL−VOL and VOH −VIH volts

0 VOL VOH VDD Where VOL, VIL, VIH and VOH are part of the 0IN 1IN specification for a particular family of digital components. INPUTS: Forbidden Zone volts Now that we have a way of encoding information as 0 V V V V V OL IL IH OH DD a signal, we can define what it means to be digital device.

Noise Margins Lecture 1 6.111 Fall 2019 29 Lecture 1 6.111 Fall 2019 30

Sample DC (signaling) Specification Arduino Processor DC Specification

Source: Xilinx Virtex 5 Datasheet Source: ATmega328P Datasheet

Lecture 1 6.111 Fall 2019 31 Lecture 1 6.111 Fall 2019 32 A Digital Processing Element Why have processing blocks?

A combinational device is a processing element that has • The goal of modular design: – one or more digital inputs One of two discrete values – one or more digital outputs – a functional specification that details the value of each ABSTRACTION Static output for every possible combination of valid input discipline values • What does that mean anyway: – a timing specification consisting (at minimum) of an – Rules simple enough for a 6-3 to follow… upper bound tpd on the required time for the device to – Understanding BEHAVIOR without knowing IMPLEMENTATION compute the specified output values from an arbitrary – Predictable composition of functions set of stable, valid input values – Tinker-toy assembly Output “1” if at – Guaranteed behavior under REAL WORLD input A least 2 out of 3 of my inputs are a “1”. circumstances Otherwise, output “0”. input B output Y

input C I will generate a valid output in no more than 2 minutes after seeing valid inputs

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A Combinational Digital System Example Device: An Inverter

+ VIN - VOUT • A set of interconnected elements is a combinational device if VOUT 0110 – each circuit element is a combinational device – every input is connected to exactly one output or a constant (e.g., some VOH vast supply of 0’s and 1’s) Voltage Transfer Characteristic: Plot of V vs. V where each – the circuit contains no directed cycles OUT IN measurement is taken after any transients have died out. • Why is this true?

– Given an acyclic circuit meeting the above constraints, we can derive VOL Note: VTC does not tell you anything functional and timing specs for the input/output behavior from the specs about how fast a device is—it of its components! VIN measures static behavior not dynamic –We’ll see lots of examples soon. But first, we need to build some VIL VIH behavior combinational devices to work with… Static Discipline requires that we avoid the shaded regions (aka “forbidden zones”), which correspond to valid inputs but invalid outputs. Net result: combinational devices must have GAIN > 1 and be NONLINEAR. VOUT V Lecture 1 6.111 Fall 2019 35 Lecture 1 6.111 Fall 2019IN 36 Combinational Device Wish List Wishes Granted: CMOS

Vout  Design our system to tolerate some VOH amount of error V V IN OUT  Add positive noise margins  VTC: gain>1 & nonlinearity VIN VOUT VOUT  Lots of gain  big noise margin V  Cheap, small OL Vin V V VOH  Changing voltages will require us to IL IH dissipate power, but if no voltages are changing, we’d like zero power L dissipation L H H  Want to build devices with useful functionality (what sort of operations VOL do we want to perform?) V  V V  V VOUT  VOH V  V OUT OL VIN IN IL IN IH V V IL IH V eventually OUT VOUT eventually reaches VDD reaches GND

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MOSFETS: Gain & Non-linearity Digital Integrated Circuits

gate IBM photomicrograph (SiO2 has been removed!) source Polysilicon wire

Inter-layer SiO insulation Heavily doped (n-type or p-type) diffusions 2 W Very thin (<20Å) high-quality SiO 2 Metal 2 insulating layer isolates gate from L drain channel region. M1/M2 via

Channel region: electric field from charges on gate locally “inverts” type of substrate to create a conducting bulk Doped (p-type or n-type) silicon substrate channel between source and drain. Metal 1

Polysilicon MOSFETs (metal-oxide-semiconductor field-effect transistors) are four- terminal voltage-controlled switches. Current flows between the diffusion Diffusion terminals if the voltage on the gate terminal is large enough to create a conducting “channel”, otherwise the mosfet is off and the diffusion terminals are not connected. Mosfet (under polysilicon gate)

Lecture 1 6.111 Fall 2019 39 Lecture 1 6.111 Fall 2019 40 Moore’s Forever? Functional Specifications

ABCY 0000 Output “1” if at 0010 input A least 2 out of 3 of my inputs are a “1”. 0100 Otherwise, output “0”. input B output Y 0111 input C I will generate a valid output in no more than 1000 2 minutes after seeing valid inputs 1011 1101 1111 3 binary inputs so 23 = 8 rows in our truth table

An concise, unambiguous technique for giving the functional specification of a combinational device is to use a truth table to specify the output value for each possible combination of input values (N binary inputs -> 2N possible combinations of input values).

Lecture 1 6.111 Fall 2019Economist March 12-18, 2016 41 Lecture 1 6.111 Fall 2019 42

Timing Specifications Contamination Delay an optional, additional timing spec Propagation delay (tPD): An upper bound on the delay from valid inputs to valid Contamination delay(tCD): A lower bound on the delay outputs (aka “tPD,MAX”) from invalid inputs to invalid outputs (aka “tPD,MIN”) VIN VIN V IH Do we really need V IH tCD? VIL V Design goal: IL Usually not… it’ll be minimize important when we design circuits with VOUT < t < t propagation PD PD V > t > t registers (coming delay OUT CD CD soon!) VOH VOH

If tCD is not specified, V OL VOL safe to assume it’s 0.

Lecture 1 6.111 Fall 2019 43 Lecture 1 6.111 Fall 2019 44 The Combinational Contract Building Digital Systems

• Goal of 6.111: Building binary digital solutions to A B t propagation delay computational problems AB 0 1 PD tCD contamination delay 1 0  Labs & Design project Problem Statement  Product specs

algorithm selection, A flowcharts, etc.  Algorithms, RTL, etc. B Behavioral Description  Flowcharts  State transition diagrams conversion to binary, Booelan algebra Must be ______> tCD  Logic equations Boolean Logic and State  Circuit schematics < t device selection Must be ______PD and wiring Note:  TTL Gates (AND,OR,XOR…) 1. No Promises during Hardware Implementation  Modules (counter, shifter,…)  Programmable Logic 2. Default (conservative) spec: tCD = 0

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Building Digital Systems with HDLs Verilog and VHDL

• Logic synthesis using a Hardware Description Language (HDL) VHDL Verilog

automates the most tedious and error-prone aspects of design  Commissioned in 1981 by • Created by Gateway Design Department of Defense; Automation in 1985;  Labs & Design project now an IEEE standard now an IEEE standard Problem Statement  Product specs  Initially created for ASIC • Initially an interpreted language algorithm selection, synthesis for gate-level simulation flowcharts, etc.  Algorithms, RTL, etc.  Strongly typed; potential for • Less explicit typing (e.g.,  Flowcharts Behavioral Description verbose code compiler will pad arguments of  State transition diagrams software-like different widths) programming • No special extensions for large  Strong support for package  Verilog code management and large designs HDL Description  VHDL code designs automated synthesis

 Programmable Logic Hardware structures can be modeled effectively in either Hardware Implementation  Custom ASICs VHDL and Verilog. Verilog is similar to c and a bit easier to learn.

Lecture 1 6.111 Fall 2019 47 Lecture 1 6.111 Fall 2019 48 Verilog HDL The FPGA: A Conceptual View

• Misconceptions • An FPGA is like an electronic breadboard that is wired together by an – The coding style or clarity does not matter as long as it works automated synthesis tool – Two different Verilog encodings that simulate the same way will synthesize to the same set of gates • Built-in components are called CLB (configurable logic blocks) and – Synthesis just can’t be as good as a design done by humans used to build logic blocks. • Shades of assembly language versus a higher level language

32 • What can be Synthesized 32 DQ – Combinational Functions + SUM • Multiplexors, Encoders, Decoders, Comparators, Parity Generators, Adders, 32 Subtractors, ALUs, Multipliers • Random logic sel – Control Logic counter • FSMs interconnect a F(a,b,c,d) • What can’t be Synthesized b c LUT G(a,b,c,d) – Precise timing blocks (e.g., delay a signal by 2ns) d – Large memory blocks (can be done, but very inefficient) ADR RAM DATA • Understand what constructs are used in simulation vs. hardware mapping R/W (for everything else)

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Xilinx FPGA Interconnect Details Synthesis and Mapping for FPGAs

• Infer logic : choose the FPGA CLB that efficiently implement various parts of the HDL code

... “This section of code looks like always @ (posedge clk) a counter. My FPGA can begin synthesize some of those...” count <= count + 1; counter end ... HDL Code Inferred logic • Place-and-route: with area and/or speed in mind, choose the needed macros by location and route the interconnect

M M M M M M M

M M M M M M M “This design only uses 10% of the FPGA. Let’s use the CLB in one M M M M M M M corner to minimize the distance M M M M M M M between blocks.” M M M M M M M Why six transistors?

Lecture 1 6.111 Fall 2019 51 Lecture 1 6.111 Fall 2019 52 Summary Lab Checkoff • Use voltages to encode information • “Digital” encoding • Lab check off will be in two groups: Thu or Fri. – valid voltage levels for representing “0” and “1” • Thu group indicated by @G1 or @G2 in grade sheet – forbidden zone avoids mistaking “0” for “1” and vice versa •Noise – Want to tolerate real-world conditions: NOISE. – Key: tougher standards for output than for input – devices must have gain and have a non-linear VTC • Combinational devices – Each logic family has Tinkertoy-set simplicity, modularity – predictable composition: “parts work  whole thing works” – static discipline • digital inputs, outputs; restore marginal input voltages • complete functional spec, e.g., a truth table

• valid inputs lead to valid outputs in bounded time (

Lecture 1 6.111 Fall 2019 53 Lecture 1 6.111 Fall 2019 54 6.111 Thru the Ages

Lecture 1 Part 2 Lab kit 1990 aka “digital death” Labkit 2005 Quick SystemVerilog and Vivado Overview for Lab 1

Nexys 4 ‐ 2016 PYNQ ‐ 2019*** 9/5/2019 6.111 Fall 2019 1 Lecture 1 6.111 Fall 2019 2

Things Change…. Vivado Demo

https://web.mit.edu/6.111/volume2/www/f2019/handouts/labs/vivado_quickstart/quickstart.html

https://www.nature.com/articles/s41586‐019‐1493‐8

9/5/2019 6.111 Fall 2019 3 9/5/2019 6.111 Fall 2019 4 What Controls “Verilog” or “SystemVerilog”? This? • SystemVerilog is a superset of Verilog (just like C++ • SystemVerilog is a superset of C) interpreted with • We will learn/use SystemVerilog (.sv files), however Vivado ~90% of what we do is just Verilog! • We’re transitioning to this for 2019 since this is how the field is. It also opens a lot more doors for self‐study: • SystemVerilog is pretty nice so maybe you’ll arrive organically at needing some of its behaviors in the project

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Online Verilog/SystemVerilog How to Think About Designing Logic Resources • There are books, but you can figure out most of it • A piece of software/program should be thought of from: as a set of instructions that are executed roughly • Doing the labs (motivation to have to figure it out) sequentially • Formal‐ish online resources (best free tutorials): • You describe what to do with software • http://www.asic‐world.com/verilog/veritut.html • http://www.asic‐world.com/systemverilog/tutorial.html • Informal (StackOverflow)

9/5/2019 6.111 Fall 2019 7 9/5/2019 6.111 Fall 2019 8 Three Languages, Similar Functionality How to Think About Designing Logic • Verilog allows us to design hardware in ways similar to how we write programs: • A design in a Hardware Description Language (HDL) describes the wiring and placement of components. Think of it is specifying a blueprint for what you want to build • You describe what to build with HDL

• Everything you describe exists in parallel (sort of)

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The Verilog implementation is Verilog is Very Low Level only one‐bit wide by default

• We’ll be using Xilinx FPGAs in this class, and in order to do that, we’ll need to use their software

Will most likely get synthesized to or the equivalent: development environment Vivado • a is one bit • is one bit a b c • Large piece of software that takes care of b a • is one bit c 0 0 0 everything for us c b 0 1 1 1 0 1 • Lab 1 is designed to get you working with it quickly, 1 1 0 but it is going to take a few labs to get to really If we wanted an 8 bit adder: know it.

9/5/2019 6.111 Fall 2019 11 9/5/2019 6.111 Fall 2019 12 Verilog Gets Turned into a Circuit Vivado QuickStart SystemVerilog file Vivado • Video shown at beginning • We have a fully‐working project for you to build here: https://web.mit.edu/6.111/volume2/www/f2019/ Build handouts/labs/vivado_quickstart/quickstart.html Processes • We recommend building it before starting Lab 1 since it has some setup stuff in it.

Console

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Under Synthesis go to: This Circuit then Gets Schematic Verilog: Designed Verilog is interpreted into a circuit • Start with this:

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For Lab 1 Practicing Verilog • The circuits you’ll be building will be purely combinational, meaning they will be stateless • Current outputs based ONLY on current inputs • Install Vivado (takes up lots of space and requires • No clocks…your designs won’t need to include the Windows or Linux) concept of time • This shouldn’t be too bad and should let us focus more on syntax and Vivado rather than the intricacies of other • Or…. stuff.

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edaplayground.com/home Icarus Verilog

• Works well, but is only Verilog (not SystemVerilog) so a subset of commands we use such as always_ff always_comb will not be supported

• http://iverilog.icarus.com/

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Recommendation

• Start Lab 1 as soon as possible (due next week) • Lab 1 and Pset 1 will mutually support one another (Pset 1 is designed to help you do Lab 1)

• Lab 2 is longer, and will come out tomorrow/this weekend early in case you want to get started on it.

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