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Implementació D'un Mòdul De Comptadors Hardware En El Processador Openrisc 1200

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Implementació D'un Mòdul De Comptadors Hardware En El Processador Openrisc 1200 Implementació d'un mòdul de comptadors hardware en el processador OpenRISC 1200 Autor: Albert Batallé García Grau en Enginyeria Informàtica Especialitat en Enginyeria de Computadors Director: Ramon Canal Corretger Codirector: Roger Espasa Sans Departament d'Arquitectura de Computadors (DAC) Facultat d'Informàtica de Barcelona (FIB) Universitat Politècnica de Catalunya (UPC) – Barcelona Tech Dijous 6 de febrer de 2014 RESUM Els comptadors hardware són uns registres interns al processador que compten esdeveniments. D’aquesta manera es pot recopilar informació del que està passant internament al processador. Després d’una selecció sobre diferents processadors existents, s’analitza i es genera documentació per al processador OR1200 basat en OpenRISC. Finament s’implementa un mòdul de comptadors hardware en el processador i es presenten resultats del correcte funcionament de la implementació basant-se en uns jocs de proves. i RESUMEN Los contadores hardware son unos registros internos al procesador que cuentan eventos. De esta forma se recopila información de lo que está sucediendo internamente al procesador. Tras una selección sobre diferentes procesadores existentes, se analiza y genera documentación para el procesador OR1200 basado en OpenRISC. Finalmente se implementa un módulo de contadores hardware en el procesador y se presentan resultados del correcto funcionamiento de la implementación basándose en unos test. ii ABSTRACT Performance counters are internal registers in the processor that count events. Thereby information about what is happening in the core is collected. After selecting a processor from a variety of them, documentation for OR1200 processor, which is based on OpenRISC, has been analyzed and generated. Lastly, a performance counters module has been implemented in the processor and results of the implementation correctness are provided through executed tests. iii AGRAÏMENTS El TFG és un treball de caràcter personal però altres persones resulten implicades i és humà reconèixer el seu ajut. En primer lloc vull agrair al director del projecte, Ramon Canal Corretger, per acceptar ser- ne el director i la paciència en la lectura dels correus electrònics extensos que li enviava. En segon lloc al codirector, Roger Espasa Sans, per fer realitat el projecte al proposar afegir un mòdul de comptadors hardware en un processador que s’havia d’escollir. Finalment, al professor Josep-Llorenç Cruz Díaz, per rebre’m quan no ens podíem trobar amb el director i per la resolució de petits dubtes sorgits tot i no participar d'aquest projecte. iv ÍNDEX DE CONTINGUTS 1 INTRODUCCIÓ ..................................................................................................................... 1 1.1 MOTIVACIÓ .............................................................................................................................. 1 1.2 OBJECTIUS ............................................................................................................................... 1 1.3 ELS COMPTADORS HARDWARE ...................................................................................................... 2 1.4 RELLEVÀNCIA I JUSTIFICACIÓ ........................................................................................................ 3 1.5 METODOLOGIA ......................................................................................................................... 3 1.6 DOCUMENTACIÓ OR1200 GENERADA ........................................................................................... 5 2 ESTAT DE L'ART ................................................................................................................... 6 2.1 LLENGUATGES DE DESCRIPCIÓ DE HARDWARE (HDL) ......................................................................... 6 2.2 PROCESSADORS EXISTENTS .......................................................................................................... 7 2.3 COMPTADORS HARDWARE ACTUALS .............................................................................................. 9 3 OPENRISC ......................................................................................................................... 11 3.1 QUÈ ÉS OPENRISC .................................................................................................................. 11 3.2 L'ARQUITECTURA OPENRISC 1000 ............................................................................................ 11 3.2.1 El conjunt de registres .................................................................................................... 12 3.2.2 El joc d'instruccions ........................................................................................................ 13 3.2.2.1 El format de les instruccions ............................................................................................. 14 3.3 ORPSOC ............................................................................................................................... 17 3.4 EL PROCESSADOR OR1200 ....................................................................................................... 19 3.4.1 El pipeline ....................................................................................................................... 21 4 EINES I RECURSOS SW I HW ............................................................................................... 25 4.1 PLACA DE1 D’A LTERA ............................................................................................................... 25 4.1.1 Les FPGA ......................................................................................................................... 26 4.2 SOFTWARE QUARTUS II D’A LTERA ............................................................................................... 29 4.3 SOFTWARE LOGICWORKS .......................................................................................................... 29 4.4 SIMULADOR MODELSIM .......................................................................................................... 30 4.5 SIMULADOR ICARUS VERILOG + VISUALITZADOR GTKWAVE ............................................................ 30 4.6 TOOL CHAIN D’OPENRISC ......................................................................................................... 31 v 4.6.1 Simulador OR1ksim ........................................................................................................ 32 4.6.2 Imatge de Linux .............................................................................................................. 32 4.7 OR1K-TCLTOOLS ...................................................................................................................... 32 4.8 EINES DE L’ORPSOC ................................................................................................................ 33 4.8.1 Obtenir el fitxer binari per a l’FPGA ............................................................................... 34 4.8.2 Programar el processador a l’FPGA ............................................................................... 34 4.8.3 Simular el processador ................................................................................................... 35 5 DISSENY I IMPLEMENTACIÓ DELS COMPTADORS HARDWARE ............................................ 36 5.1 ESDEVENIMENTS ..................................................................................................................... 36 5.1.1 Definició dels esdeveniments ......................................................................................... 37 5.2 UBICACIÓ DEL MÒDUL PCU ....................................................................................................... 39 5.3 REGISTRES DEL MÒDUL PCU ...................................................................................................... 40 5.3.1 Registres de configuració, grup SPR 0 ............................................................................ 40 5.3.2 Registres PCCR0-PCCR7 .................................................................................................. 42 5.3.3 Registres PCMR0-PCMR7 ............................................................................................... 42 5.4 LA LÒGICA DEL MÒDUL PCU ...................................................................................................... 43 5.4.1 Implementació dels esdeveniments ............................................................................... 44 5.4.2 Implementació dels registres comptadors ..................................................................... 47 5.5 IMPLEMENTACIÓ D’UN VISUALITZADOR DE COMPTADORS EXTERN AL PROCESSADOR ............................... 51 6 RESULTATS ........................................................................................................................ 53 6.1 IMPACTE DEL BUS I DE LA MEMÒRIA PRINCIPAL EN ELS RESULTATS ....................................................... 59 7 DESENVOLUPAMENT DEL PROJECTE .................................................................................. 60 7.1 PLANIFICACIÓ ......................................................................................................................... 60 7.1.1 Planificació inicial ........................................................................................................... 60 7.1.2 Canvi de planificació ....................................................................................................... 62 7.1.3 Planificació
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