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Co-Simulation Between Cλash and Traditional Hdls MASTER THESIS CO-SIMULATION BETWEEN CλASH AND TRADITIONAL HDLS Author: John Verheij Faculty of Electrical Engineering, Mathematics and Computer Science (EEMCS) Computer Architecture for Embedded Systems (CAES) Exam committee: Dr. Ir. C.P.R. Baaij Dr. Ir. J. Kuper Dr. Ir. J.F. Broenink Ir. E. Molenkamp August 19, 2016 Abstract CλaSH is a functional hardware description language (HDL) developed at the CAES group of the University of Twente. CλaSH borrows both the syntax and semantics from the general-purpose functional programming language Haskell, meaning that circuit de- signers can define their circuits with regular Haskell syntax. CλaSH contains a compiler for compiling circuits to traditional hardware description languages, like VHDL, Verilog, and SystemVerilog. Currently, compiling to traditional HDLs is one-way, meaning that CλaSH has no simulation options with the traditional HDLs. Co-simulation could be used to simulate designs which are defined in multiple lan- guages. With co-simulation it should be possible to use CλaSH as a verification language (test-bench) for traditional HDLs. Furthermore, circuits defined in traditional HDLs, can be used and simulated within CλaSH. In this thesis, research is done on the co-simulation of CλaSH and traditional HDLs. Traditional hardware description languages are standardized and include an interface to communicate with foreign languages. This interface can be used to include foreign func- tions, or to make verification and co-simulation possible. Because CλaSH also has possibilities to communicate with foreign languages, through Haskell foreign function interface (FFI), it is possible to set up co-simulation. The Verilog Procedural Interface (VPI), as defined in the IEEE 1364 standard, is used to set-up the communication and to control a Verilog simulator. An implementation is made, as will be described in this thesis, to show the practical feasibility of co-simulation of CλaSH and Verilog1. The VHDL Procedural Interface (VHPI), as defined in the IEEE 1067 standard, is less popular compared with the VPI. Furthermore, not every VHDL simulator gives support for the VHPI. For example, ModelSim and QuestaSim use a different interface. The VHPI is set up in the same way as the VPI. The expectation is that co-simulation through the VPHI can be implemented in a comparable way. GHDL, an open-source VHDL simulator, does however give support for the VPI and this interface could be used to set-up co-simulation between CλaSH and VHDL. 1The VPI can also be used to define co-simulation with SystemVerilog. The co-simulation supports both combinational and synchronous sequential designs. A combinational circuit does not contain memory elements and the output can be seen as a pure function of the present input. This is in contrast to a synchronous sequential design, in which the output also depends on the history of the input. Within a synchronous sequential circuit, the changes in the state of the memory el- ements are synchronized by a clock signal. A clock is a periodic signal, in which every period is called a clock-cycle, as shown in Figure 1. A clock-cycle consists of multiple simulation steps. A simulation step can be associated with a certain time indication in the Verilog code, for example 1 nanosecond. clock-cycle Figure 1: A clock signal In typical Register Transfer Level (RTL) code, some events cause other events to oc- cur in the same simulation step. For example, when a clock signal triggers, some signals may change in the same simulation step. To ensure race-free operations, HDLs must differentiate between such events with so-called 'delta' delays. However, CλaSH does not work with delta-delays and signals are defined per clock-cycle. The defined co-simulation tries to seamlessly communicate with the traditional HDL and thus clock-cycles have the same length in both HDLs. A clock signal will change twice in one clock-signal. The recommendation is to define the clock-signals in the tradi- tional HDL and only exchange the 'functional' values. Support for (feedback) loops is created with lazy-evaluation. The implementation uses the IO-monad to control and to communicate with the traditional HDL simulators. Lazy IO often has as disadvantage that releasing acquired resources is unpredictable. Foreign memory allocations are connected to the Haskell's Garbage Collector (GC). With the use of the GC, foreign functions are invoked when a resource is released, in which a particular co-simulation is finished and the traditional HDL simulator is closed. With Quasiquotation, Inline-Verilog is made possible. By using a Quasiquoter it is possible to define a Domain Specific Language (DSL). With Inline-Verilog it is possible to embed Verilog modules in CλaSH or to create a wrapper in which sub-modules (defined in verilog files) are included. Acknowledgements After doing the HBO study 'Technische Informatica' at Windesheim (Zwolle), I decided to do the Master study 'Embedded Systems'. Input for this decision was conversations with my family, but also discussions with my piano teacher. Looking backwards, I am very happy for this decision and my knowledge, related to Embedded Systems, is very extended. First of all I would like to thank Jan (Kuper) and Christiaan, for offering me this master thesis project and providing support. A year ago my knowledge about functional programming was very limited and I did not expect to learn so much in this field. I am very excited about CλaSH and the 'new' possibilities on how to program FPGAs. Furthermore, I would like to thank my exam commission for providing support and time during this graduation. Joris, thanks for the conversations and the time we spend together during this master. I very liked our discussions, which also gave inspiration for this master thesis. Guus and Rinse, for being my day-time room-mates and the conversations about hol- idays and technical things. The jokes we made together and the fun we had. Harm, for the discussions on how to improve my implementation. Bert Molenkamp, for always having time for checking & changing my study progress documents and the insights about VHDL & Verilog. And of course, for being part of my exam commission. All members of the CAES group, thanks for the conversations and the time together during the breaks. This group also gave me a good impression about performing research and doing a PhD. Finally I would like to thank my family and girlfriend for their support during my master and this thesis. Although we did not have much conversations about the technical part; I much appreciate the help with for example my car and all the other needed things. John, 't Harde, August 2016 Acronyms CλaSH CAES Language for Synchronous Hardware CAES Computer Architecture for Embedded Systems Cocotb COroutine based COsimulation TestBench DPI Direct Programming Interface DSL Domain Specific Language EDA Electronic Design Automation FFI Foreign Function Interface FLI Foreign Language Interface FPGA Field programmable Gate Array GHC Glasgow Haskell Compiler GHDL G Hardware Design Language HDL Hardware Description Language HVL Hardware Verification Language IVI Icarus Verilog Interactive MAC Multiply ACcumulate PLI Program Language Interface RTL Register Transfer Level TH Template Haskell VHDL VHSIC Hardware Description Language VHPI VHDL Procedural Interface VHSIC Very High Speed Integrated Circuit VPI Verilog Procedural Interface Contents 1 Introduction.......................................................................... 1 1.1 Problem statement and approach............................................... 3 1.2 Outline ........................................................................... 4 2 Background .......................................................................... 5 2.1 CλaSH............................................................................ 6 2.1.1 Foreign Function Interface.............................................. 9 2.1.2 Template Haskell & QuasiQuotation................................... 11 2.2 Related Work .................................................................... 13 2.2.1 MyHDL .................................................................. 14 2.2.2 Cocotb.................................................................... 17 2.3 Verilog & VHDL interfaces...................................................... 19 2.3.1 Verilog Procedural Interface ............................................ 20 2.3.2 VHDL Procedural Interface............................................. 21 2.3.3 Other Foreign Interfaces ................................................ 24 3 VPI .................................................................................... 25 3.1 Compiletf & Calltf............................................................... 27 3.2 Simulation Events & Callbacks................................................. 29 3.3 Traversing hierarchy............................................................. 33 3.4 Reading & Modifying Values.................................................... 36 CONTENTS CONTENTS 4 Implementation ..................................................................... 39 4.1 Overview ......................................................................... 39 4.2 CλaSH............................................................................ 42 4.2.1 Type Conversion......................................................... 43 4.2.2 Type Classes............................................................. 46 4.2.3 Foreign Function Interface.............................................
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