DOCSLIB.ORG

Hardware Description Languages Compared: Verilog and Systemc

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Hardware Description Languages Compared: Verilog and Systemc Hardware Description Languages Compared: Verilog and SystemC Gianfranco Bonanome Columbia University Department of Computer Science New York, NY Abstract This library encompasses all of the necessary components required to transform C++ into a As the complexity of modern digital systems hardware description language. Such additions increases, engineers are now more than ever include constructs for concurrency, time notion, integrating component modeling by means of communication, reactivity and hardware data hardware description languages (HDLs) in the types. design process. The recent addition of SystemC to As described by Edwards [1], VLSI an already competitive arena of HDLs dominated verification involves an initial simulation done in by Verilog and VHDL, calls for a direct C or C++, usually for proof of concept purposes, comparison to expose potential advantages and followed by translation into an HDL, simulation of flaws of this newcomer. This paper presents such the model, applying appropriate corrections, differences and similarities, specifically between hardware synthesization and further iterative Verilog and SystemC, in effort to better categorize refinement. SystemC is able to shorten this the scopes of the two languages. Results are based process by combining the first two steps. on simulation conducted in both languages, for a Consequently, this also decreases time to market model with equal specifications. for a manufacturer. Generally a comparison between two computer languages is based on the number of Introduction lines of code and execution time required to achieve a specific task, using the two languages. A Continuous advances in circuit fabrication number of additional parameters can be observed, technology have augmented chip density, such as features, existence or absence of constructs consequently increasing device complexity. This that facilitate coding, availability of optimization has resulted in a higher degree of design techniques, as well as others. These criteria vary automation and increase in the number of tools slightly when attempting to compare two HDLs. available to an integrated chip designer. Recently For instance, HDLs need to have time-handling there has been an incline toward the usage of constructs, unlike most other computer languages. Hardware Description Languages [3]. The Comparable “building blocks” may synthesize into portability of models created with such tools, has different circuitry, depending on the language’s made them preferable over their corresponding standard. flow, state and logic diagrams. Other points utilized as a basis for comparison Various HDLs with diverse properties and include: efficiency of methods and language objectives have been developed over the years, constructs, signal behavior description, scheduling giving designers a vast selection in the appropriate semantics and ease of implementation. modeling instrument. In this paper I will be comparing different SystemC presents a new approach to the aspects between the Verilog [2] and SystemC [4] concept of HDLs, as it combines hardware and HDLs, according to the measures mentioned software descriptions at different levels of above. The code that will be used to base this abstraction, by extending C++ with a new comparison implements an alarm clock controller. library. Related work after, to specify their sizes. SystemC accomplishes this in one step, but at its own can declare a Previous work comparing two or more HDLs is function separately from its body, as in C. This limited to a few papers, usually regarding VHDL property of the language can also be viewed as an and Verilog. This is mainly due to the fact that advantage, since a module can therefore call SystemC is a latecomer to this field, but also several different processes. Verilog is only able to because it is merely an extension of an already carry out a process if found within a module, existing language. which signifies having to write a module for every Douglas Smith wrote a tutorial [5] in which he process that needs to be called by external compares VHDL and Verilog. Smith also describes modules. The absence of a high level construct the range of modeling capacity possessed by the that replicates structure can often lead into two languages, exposing VHDL’s lower modeling writing code that may seem repetitive, or difficult limit: gate level. Interestingly enough, Verilog is to optimize. one of the few HDLs capable of modeling down to When modeling a process in Verilog, common transistor level. practice is to have an always construct around the Few additional papers dealing with two or body of the function to be evaluated. In SystemC, more HDLs exist, but are generally not meant to the functions are written as members of the bring forth comparison issues, rather to present module class being designed, allowing the designer co-design techniques such as Agliada [8]. to more easily integrate additional functionality in In his paper on co-simulation of VHDL and the same design. SystemC, Agliada introduces a method to Timing mechanisms vary extensively between homogenize the system descriptions in order to Verilog and SystemC. The later has a built-in simulate them together. This approach calls for a clocking mechanism, where such a device and its VHDL to SystemC translator. In describing such a output signal wave can be described using the tool, it is unavoidable to compare the two sc_clock() construct. Instead, Verilog uses a more languages, even if not in detail. general way to create a clock: by defining it as a module. Although this technique may appear inefficient, it is actually more natural for a Fundamental differences in constructs beginning designer, since no new constructs need to be learned. Figure 2 below, illustrates this Both Verilog and SystemC utilize modules as point. design entities While Verilog has the module keyword build in, SystemC needs to call a Verilog SystemC construct named sc_module() to declare the body module m555 (clock); sc_clock m555("m555", of the device at task. The difference in module output clock; 20, 0.5, 5, true); reg clock; declaration syntax can be seen below in figure 1. initial #5 clock = 1; always #50 clock = ~clock; Verilog SystemC endmodule module runner(port names); SC_MODULE(Runner) { Figure 2. Clock declaration syntax. //port sizes and direction //ports sizes and direction //body //body SystemC allows for three types of processes to endmodule }; //member functions be utilized in the description of a model: methods, threads and synchronized threads. Figure 1. Component declaration syntax. According to the SystemC User’s Guide [4], methods execute when changes occur in signals Although Verilog may appear slightly more found in their sensitivity list. Upon termination, a concise at first, it should be pointed out that the method returns control to the simulation kernel. former requires ports to be listed once in the Threads behave similarly as methods, but they module declaration line, and again immediately may also be suspended and reactivated at the occurrence of a specified event. As Edwards [1] wire or tri Simple interconnecting wire points out, hardware does not exhibit this wor or trior Wired outputs OR together behavior, but such processes can be useful when wand or triand Wired outputs AND together designing a test bench. tri0 Pulls down when tri-stated Synchronous threads are a special case of tri1 Pulls up when tri-stated threads, where triggering takes place at a specific supply0 Constant logic 0 (supply strength) edge of a signal. The scheduling of all three supply1 Constant logic 1 (supply strength) process types takes place at the bottom portion of trireg Stores last value when tri-stated a SystemC model, by using the sc_ctor() macro (capacitance strength) (SystemC constructor). In modeling an alarm clock controller, such a constructor was called for In order to support modeling at different levels the tick process of type method: of abstraction, from the functional to the register- transfer level, as well as to support software, sc_ctor ( Runner ) { SystemC provides programmers with a rich set of sc_method ( tick ); signal types. This is different from languages like sensitive_pos ( clock ); Verilog that only support bit-vectors as types. } SystemC can implement both two-valued and four-valued signal types, which add practicality to where Runner is the name of the sc_module that a simulation. owns the tick process. SystemC’s set of data types is enhanced to Verilog per se does not differentiate among support multiple design domains and abstraction processes, but allows flexibility to mimic the levels. The fixed precision types allow for fast behavior found in the three scenarios described simulation. The arbitrary precision types can be above. This is achieved by means of timing- used for computations with large numbers and to oriented constructs such as: model large busses. Such types do not have a limitation in size. always @ ( condition ) In addition, this HDL provides a large selection of overloaded operators, quantization and Here the condition may be a signal or an overflow modes, as well as type conversion event, in which case the identifier will be found mechanisms. between parentheses. By this token, a function SystemC, extends C++ types by utilizing the can also be edge-triggered: following signal definition syntax: always @ ( posedge clock ) sc_signal < base_type > signal_name; As strongly-typed languages, both Verilog and where base_type corresponds to one of C++’s
Load more

Recommended publications
  • Prostep Ivip CPO Statement Template
    CPO Statement of Mentor Graphics For Questa SIM Date: 17 June, 2015 CPO Statement of Mentor Graphics Following the prerequisites of ProSTEP iViP’s Code of PLM Openness (CPO) IT vendors shall determine and provide a list of their relevant products and the degree of fulfillment as a “CPO Statement” (cf. CPO Chapter 2.8). This CPO Statement refers to: Product Name Questa SIM Product Version Version 10 Contact Ellie Burns [email protected] This CPO Statement was created and published by Mentor Graphics in form of a self-assessment with regard to the CPO. Publication Date of this CPO Statement: 17 June 2015 Content 1 Executive Summary ______________________________________________________________________________ 2 2 Details of Self-Assessment ________________________________________________________________________ 3 2.1 CPO Chapter 2.1: Interoperability ________________________________________________________________ 3 2.2 CPO Chapter 2.2: Infrastructure _________________________________________________________________ 4 2.3 CPO Chapter 2.5: Standards ____________________________________________________________________ 4 2.4 CPO Chapter 2.6: Architecture __________________________________________________________________ 5 2.5 CPO Chapter 2.7: Partnership ___________________________________________________________________ 6 2.5.1 Data Generated by Users ___________________________________________________________________ 6 2.5.2 Partnership Models _______________________________________________________________________ 6 2.5.3 Support of
    [Show full text]
  • Systemverilog
    SystemVerilog ● Industry's first unified HDVL (Hw Description and Verification language (IEEE 1800) ● Major extension of Verilog language (IEEE 1364) ● Targeted primarily at the chip implementation and verification flow ● Improve productivity in the design of large gate-count, IP- based, bus-intensive chips Sources and references 1. Accellera IEEE SystemVerilog page http://www.systemverilog.com/home.html 2. “Using SystemVerilog for FPGA design. A tutorial based on a simple bus system”, Doulos http://www.doulos.com/knowhow/sysverilog/FPGA/ 3. “SystemVerilog for Design groups”, Slides from Doulos training course 4. Various tutorials on SystemVerilog on Doulos website 5. “SystemVerilog for VHDL Users”, Tom Fitzpatrick, Synopsys Principal Technical Specialist, Date04 http://www.systemverilog.com/techpapers/date04_systemverilog.pdf 6. “SystemVerilog, a design and synthesis perspective”, K. Pieper, Synopsys R&D Manager, HDL Compilers 7. Wikipedia Extensions to Verilog ● Improvements for advanced design requirements – Data types – Higher abstraction (user defined types, struct, unions) – Interfaces ● Properties and assertions built in the language – Assertion Based Verification, Design for Verification ● New features for verification – Models and testbenches using object-oriented techniques (class) – Constrained random test generation – Transaction level modeling ● Direct Programming Interface with C/C++/SystemC – Link to system level simulations Data types: logic module counter (input logic clk, ● Nets and Variables reset, ● enable, Net type,
    [Show full text]
  • Powerpoint Template
    Accellera Overview February 27, 2017 Lu Dai | Accellera Chairman Welcome Agenda . About Accellera . Current news . Technical activities . IEEE collaboration 2 © 2017 Accellera Systems Initiative, Inc. February 2017 Accellera Systems Initiative Our Mission To provide a platform in which the electronics industry can collaborate to innovate and deliver global standards that improve design and verification productivity for electronics products. 3 © 2017 Accellera Systems Initiative, Inc. February 2017 Broad Industry Support Corporate Members 4 © 2017 Accellera Systems Initiative, Inc. February 2017 Broad Industry Support Associate Members 5 © 2017 Accellera Systems Initiative, Inc. February 2017 Global Presence SystemC Evolution Day DVCon Europe DVCon U.S. SystemC Japan Design Automation Conference DVCon China Verification & ESL Forum DVCon India 6 © 2017 Accellera Systems Initiative, Inc. February 2017 Agenda . About Accellera . Current news . Technical activities . IEEE collaboration 7 © 2017 Accellera Systems Initiative, Inc. February 2017 Accellera News . Standards - IEEE Approves UVM 1.2 as IEEE 1800.2-2017 - Accellera relicenses SystemC reference implementation under Apache 2.0 . Outreach - First DVCon China to be held April 19, 2017 - Get IEEE free standards program extended 10 years/10 standards . Awards - Thomas Alsop receives 2017 Technical Excellence Award for his leadership of the UVM Working Group - Shrenik Mehta receives 2016 Accellera Leadership Award for his role as Accellera chair from 2005-2010 8 © 2017 Accellera Systems Initiative, Inc. February 2017 DVCon – Global Presence 29th Annual DVCon U.S. 4th Annual DVCon Europe www.dvcon-us.org 4th Annual DVCon India www.dvcon-europe.org 1st DVCon China www.dvcon-india.org www.dvcon-china.org 9 © 2017 Accellera Systems Initiative, Inc.
    [Show full text]
  • Co-Simulation Between Cλash and Traditional Hdls
    MASTER THESIS CO-SIMULATION BETWEEN CλASH AND TRADITIONAL HDLS Author: John Verheij Faculty of Electrical Engineering, Mathematics and Computer Science (EEMCS) Computer Architecture for Embedded Systems (CAES) Exam committee: Dr. Ir. C.P.R. Baaij Dr. Ir. J. Kuper Dr. Ir. J.F. Broenink Ir. E. Molenkamp August 19, 2016 Abstract CλaSH is a functional hardware description language (HDL) developed at the CAES group of the University of Twente. CλaSH borrows both the syntax and semantics from the general-purpose functional programming language Haskell, meaning that circuit de- signers can define their circuits with regular Haskell syntax. CλaSH contains a compiler for compiling circuits to traditional hardware description languages, like VHDL, Verilog, and SystemVerilog. Currently, compiling to traditional HDLs is one-way, meaning that CλaSH has no simulation options with the traditional HDLs. Co-simulation could be used to simulate designs which are defined in multiple lan- guages. With co-simulation it should be possible to use CλaSH as a verification language (test-bench) for traditional HDLs. Furthermore, circuits defined in traditional HDLs, can be used and simulated within CλaSH. In this thesis, research is done on the co-simulation of CλaSH and traditional HDLs. Traditional hardware description languages are standardized and include an interface to communicate with foreign languages. This interface can be used to include foreign func- tions, or to make verification and co-simulation possible. Because CλaSH also has possibilities to communicate with foreign languages, through Haskell foreign function interface (FFI), it is possible to set up co-simulation. The Verilog Procedural Interface (VPI), as defined in the IEEE 1364 standard, is used to set-up the communication and to control a Verilog simulator.
    [Show full text]
  • Development of Systemc Modules from HDL for System-On-Chip Applications
    University of Tennessee, Knoxville TRACE: Tennessee Research and Creative Exchange Masters Theses Graduate School 8-2004 Development of SystemC Modules from HDL for System-on-Chip Applications Siddhartha Devalapalli University of Tennessee - Knoxville Follow this and additional works at: https://trace.tennessee.edu/utk_gradthes Part of the Electrical and Computer Engineering Commons Recommended Citation Devalapalli, Siddhartha, "Development of SystemC Modules from HDL for System-on-Chip Applications. " Master's Thesis, University of Tennessee, 2004. https://trace.tennessee.edu/utk_gradthes/2119 This Thesis is brought to you for free and open access by the Graduate School at TRACE: Tennessee Research and Creative Exchange. It has been accepted for inclusion in Masters Theses by an authorized administrator of TRACE: Tennessee Research and Creative Exchange. For more information, please contact [email protected]. To the Graduate Council: I am submitting herewith a thesis written by Siddhartha Devalapalli entitled "Development of SystemC Modules from HDL for System-on-Chip Applications." I have examined the final electronic copy of this thesis for form and content and recommend that it be accepted in partial fulfillment of the equirr ements for the degree of Master of Science, with a major in Electrical Engineering. Dr. Donald W. Bouldin, Major Professor We have read this thesis and recommend its acceptance: Dr. Gregory D. Peterson, Dr. Chandra Tan Accepted for the Council: Carolyn R. Hodges Vice Provost and Dean of the Graduate School (Original signatures are on file with official studentecor r ds.) To the Graduate Council: I am submitting herewith a thesis written by Siddhartha Devalapalli entitled "Development of SystemC Modules from HDL for System-on-Chip Applications".
    [Show full text]
  • Lattice Synthesis Engine User Guide and Reference Manual
    Lattice Synthesis Engine for Diamond User Guide April, 2019 Copyright Copyright © 2019 Lattice Semiconductor Corporation. All rights reserved. This document may not, in whole or part, be reproduced, modified, distributed, or publicly displayed without prior written consent from Lattice Semiconductor Corporation (“Lattice”). Trademarks All Lattice trademarks are as listed at www.latticesemi.com/legal. Synopsys and Synplify Pro are trademarks of Synopsys, Inc. Aldec and Active-HDL are trademarks of Aldec, Inc. All other trademarks are the property of their respective owners. Disclaimers NO WARRANTIES: THE INFORMATION PROVIDED IN THIS DOCUMENT IS “AS IS” WITHOUT ANY EXPRESS OR IMPLIED WARRANTY OF ANY KIND INCLUDING WARRANTIES OF ACCURACY, COMPLETENESS, MERCHANTABILITY, NONINFRINGEMENT OF INTELLECTUAL PROPERTY, OR FITNESS FOR ANY PARTICULAR PURPOSE. IN NO EVENT WILL LATTICE OR ITS SUPPLIERS BE LIABLE FOR ANY DAMAGES WHATSOEVER (WHETHER DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL, INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR INABILITY TO USE THE INFORMATION PROVIDED IN THIS DOCUMENT, EVEN IF LATTICE HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION OR LIMITATION OF CERTAIN LIABILITY, SOME OF THE ABOVE LIMITATIONS MAY NOT APPLY TO YOU. Lattice may make changes to these materials, specifications, or information, or to the products described herein, at any time without notice. Lattice makes no commitment to update this documentation. Lattice reserves the right to discontinue any product or service without notice and assumes no obligation to correct any errors contained herein or to advise any user of this document of any correction if such be made.
    [Show full text]
  • Powerplay Power Analysis 8 2013.11.04
    PowerPlay Power Analysis 8 2013.11.04 QII53013 Subscribe Send Feedback The PowerPlay Power Analysis tools allow you to estimate device power consumption accurately. As designs grow larger and process technology continues to shrink, power becomes an increasingly important design consideration. When designing a PCB, you must estimate the power consumption of a device accurately to develop an appropriate power budget, and to design the power supplies, voltage regulators, heat sink, and cooling system. The following figure shows the PowerPlay Power Analysis tools ability to estimate power consumption from early design concept through design implementation. Figure 8-1: PowerPlay Power Analysis From Design Concept Through Design Implementation PowerPlay Early Power Estimator Quartus II PowerPlay Power Analyzer Higher Placement and Simulation Routing Results Results Accuracy Quartus II Design Profile User Input Estimation Design Concept Design Implementation Lower PowerPlay Power Analysis Input For the majority of the designs, the PowerPlay Power Analyzer and the PowerPlay EPE spreadsheet have the following accuracy after the power models are final: • PowerPlay Power Analyzer—±20% from silicon, assuming that the PowerPlay Power Analyzer uses the Value Change Dump File (.vcd) generated toggle rates. • PowerPlay EPE spreadsheet— ±20% from the PowerPlay Power Analyzer results using .vcd generated toggle rates. 90% of EPE designs (using .vcd generated toggle rates exported from PPPA) are within ±30% silicon. The toggle rates are derived using the PowerPlay Power Analyzer with a .vcd file generated from a gate level simulation representative of the system operation. © 2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S.
    [Show full text]
  • VHDL Modelling Guidelines Simulation and Documentation Aspects
    Second draft, 23 February 1997 CENELEC TC217/WG2 report 2.14 English version VHDL Modelling Guidelines Simulation and Documentation Aspects This CENELEC Report is under preparation and review by the Technical Committee CENELEC TC 217 Working Group 2. CENELEC members are the national electrotechnical committees of Austria, Belgium, Denmark, Finland, France, Germany, Greece, Iceland, Ireland, Italy, Luxembourg, Netherlands, Norway, Portugal, Spain, Sweden, Switzerland and United Kingdom. CENELEC European Committee for Electrotechnical Standardisation Comité Européen de Normalisation Electrotechnique Europäisches Komitee für Elektrotechnische Normung Central Secretariat: rue de Stassart 35, B-1050 Brussels CENELEC TC217/WG2 report 2.142 Second draft, 23 February 1997 3DJH LQWHQWLRQDOO\ OHIW EODQN Second draft, 23 February 19973 CENELEC TC217/WG2 report 2.14 )25(:25' 7KLV 7HFKQLFDO 5HSRUW LV WKH ILUVW GUDIW RI WKH &(1(/(& 7&:* UHSRUW 7KH UHSRUW LV GHULYHG IURP WKH (XURSHDQ 6SDFH $JHQF\ V (6$©V 9+'/ 0RGHOOLQJ *XLGHOLQHV UHIHUHQFH $6,& LVVXH GDWHG 6HSWHPEHU 7KLV GUDIW KDV EHHQ SUHSDUHG WDNLQJ LQWR DFFRXQW FRPPHQWV IURP &(1(/(& :* PHPEHUV SUHVHQWHG RQ WKH GHGLFDWHG HPDLO UHIOHFWRU 7KH DXWKRU ZRXOG OLNH WR WKDQN DOO FRQWULEXWRUV IRU WKHLU YDOXDEOH LQSXW 7KH (6$ 9+'/ 0RGHOOLQJ *XLGHOLQHV KDYH EHHQ XVHG LQ (6$ GHYHORSPHQW DQG VWXG\ FRQWUDFWV WR HQVXUH KLJKTXDOLW\ PDLQWDLQDEOH 9+'/ PRGHOV 7KH\ KDYH EHHQ SUHSDUHG E\ 3HWHU 6LQDQGHU ZLWK VXSSRUW IURP 6DQGL +DELQF ERWK DW WKH (6$(67(& 0LFURHOHFWURQLFV DQG 7HFKQRORJ\ 6HFWLRQ :60 32 %R[ $* 1RRUGZLMN
    [Show full text]
  • UNIVERSITY of CALIFORNIA RIVERSIDE Emulation of Systemc
    UNIVERSITY OF CALIFORNIA RIVERSIDE Emulation of SystemC Applications for Portable FPGA Binaries A Dissertation submitted in partial satisfaction of the requirements for the degree of Doctor of Philosophy in Computer Science by Scott Spencer Sirowy June 2010 Dissertation Committee: Dr. Frank Vahid, Chairperson Dr. Tony Givargis Dr. Sheldon X.-D. Tan Copyright by Scott Spencer Sirowy 2010 The Dissertation of Scott Spencer Sirowy is approved: Committee Chairperson University of California, Riverside ABSTRACT OF THE DISSERTATION Emulation of SystemC Applications for Portable FPGA Binaries by Scott Spencer Sirowy Doctor of Philosophy, Graduate Program in Computer Science University of California, Riverside, June 2010 Dr. Frank Vahid, Chairperson As FPGAs become more common in mainstream general-purpose computing platforms, capturing and distributing high-performance implementations of applications on FPGAs will become increasingly important. Even in the presence of C-based synthesis tools for FPGAs, designers continue to implement applications as circuits, due in large part to allow for capture of clever spatial, circuit-level implementation features leading to superior performance and efficiency. We demonstrate the feasibility of a spatial form of FPGA application capture that offers portability advantages for FPGA applications unseen with current FPGA binary formats. We demonstrate the portability of such a distribution by developing a fast on-chip emulation framework that performs transparent optimizations, allowing spatially-captured FPGA applications to immediately run on FPGA platforms without costly and hard-to-use synthesis/mapping tool flows, and sometimes faster than PC-based execution. We develop several dynamic and transparent optimization techniques, including just-in-time compilation , bytecode acceleration , and just-in-time synthesis that take advantage of a platform’s available resources, resulting in iv orders of magnitude performance improvement over normal emulation techniques and PC-based execution.
    [Show full text]
  • 3. Verilog Hardware Description Language
    3. VERILOG HARDWARE DESCRIPTION LANGUAGE The previous chapter describes how a designer may manually use ASM charts (to de- scribe behavior) and block diagrams (to describe structure) in top-down hardware de- sign. The previous chapter also describes how a designer may think hierarchically, where one module’s internal structure is defined in terms of the instantiation of other modules. This chapter explains how a designer can express all of these ideas in a spe- cial hardware description language known as Verilog. It also explains how Verilog can test whether the design meets certain specifications. 3.1 Simulation versus synthesis Although the techniques given in chapter 2 work wonderfully to design small machines by hand, for larger designs it is desirable to automate much of this process. To automate hardware design requires a Hardware Description Language (HDL), a different nota- tion than what we used in chapter 2 which is suitable for processing on a general- purpose computer. There are two major kinds of HDL processing that can occur: simu- lation and synthesis. Simulation is the interpretation of the HDL statements for the purpose of producing human readable output, such as a timing diagram, that predicts approximately how the hardware will behave before it is actually fabricated. As such, HDL simulation is quite similar to running a program in a conventional high-level language, such as Java Script, LISP or BASIC, that is interpreted. Simulation is useful to a designer because it allows detection of functional errors in a design without having to fabricate the actual hard- ware. When a designer catches an error with simulation, the error can be corrected with a few keystrokes.
    [Show full text]
  • Version Control Friendly Project Management System for FPGA Designs
    Copyright 2016 Society of Photo-Optical Instrumentation Engineers. This paper was published in Proceedings of SPIE (Proc. SPIE Vol. 10031, 1003146, DOI: http://dx.doi.org/10.1117/12.2247944 ) and is made available as an electronic reprint (preprint) with permission of SPIE. One print or electronic copy may be made for personal use only. Systematic or multiple reproduction, distribution to multiple locations via electronic or other means, duplication of any material in this paper for a fee or for com- mercial purposes, or modification of the content of the paper are prohibited. 1 Version control friendly project management system for FPGA designs Wojciech M. Zabołotnya aInstitute of Electronic Systems, Warsaw University of Technology, ul. Nowowiejska 15/19, 00-665 Warszawa, Poland ABSTRACT In complex FPGA designs, usage of version control system is a necessity. It is especially important in the case of designs developed by many developers or even by many teams. The standard development mode, however, offered by most FPGA vendors is the GUI based project mode. It is very convenient for a single developer, who can easily experiment with project settings, browse and modify the sources hierarchy, compile and test the design. Unfortunately, the project configuration is stored in files which are not suited for use with Version Control System (VCS). Another important problem in big FPGA designs is reuse of IP cores. Even though there are standard solutions like IEEE 1685-2014, they suffer from some limitations particularly significant for complex systems (e.g. only simple types are allowed for IP-core ports, it is not possible to use parametrized instances of IP-cores).
    [Show full text]
  • Waveform Editor
    1. Quartus II Simulator QII53017-9.1.0 This chapter describes how to perform different types of simulations with the Quartus II simulator. Introduction With today’s FPGAs becoming faster and more complex, designers face challenges in validating their designs. Simulation verifies the correctness of the design, reducing board testing and debugging time. The Altera® Quartus® II simulator is included in the Quartus II software to assist designers with design verification. The Quartus II simulator has a comprehensive set of features that are covered in the following sections: ■ “Simulation Flow” on page 1–2 ■ “Waveform Editor” on page 1–5 ■ “Simulator Settings” on page 1–13 ■ “Simulation Report” on page 1–16 ■ “Debugging with the Quartus II Simulator” on page 1–19 ■ “Scripting Support” on page 1–21 The Quartus II simulator supports the following device families: ■ ACEX® 1K ■ APEX™ 20KC, APEX 20KE, APEX II ■ Arria® GX ■ Cyclone® III, Cyclone II, Cyclone ■ FLEX® 10K, FLEX 10KA, FLEX 10KE, FLEX 6000 ■ HardCopy® II, HardCopy ■ MAX® II, MAX 3000A, MAX 7000AE, MAX 7000B, MAX 7000S ■ Stratix® III, Stratix II, Stratix, Stratix GX, Stratix II GX 1 The Quartus II simulator does not support newer devices introduced after Stratix III and Quartus II software version 8.1 and onwards. Use the ModelSim-Altera Edition to run simulations on designs targeting device introductions after Stratix III. For more information about the ModelSim-Altera Edition simulator, refer to the Mentor Graphics ModelSim Support chapter in volume 3 of the Quartus II Handbook. In the Quartus II software version 10.0 and onwards, the Quartus II simulator and Waveform Editor is removed.
    [Show full text]