A Mixed Language Fault Simulation of VHDL and SystemC Silvio Misera, Heinrich Theodor Vierhaus, Lars Breitenfeld, André Sieber Brandenburg University of Technology Cottbus, Computer Engineering Department <sm, htv, lars.breitenfeld,
[email protected]> Abstract instead, which typically have only a limited capability to handle effective and realistic fault models [7, 10]. Fault simulation technology is essential key not This is the reason why we implemented FIT [1] as a only to the validation of test patterns for ICs and SoCs, hierarchical fault simulation environment, which uses a but also to the analysis of system behavior under fault mixture of structural VHDL model at the gate level transient and intermittent faults. For this purpose, we and C++-models for large-size macros. Furthermore, developed a hierarchical fault simulation environment FIT supports non-trivial fault models such as single- that uses structural VHDL models at the gate level, but event upsets (SEUs). is able to model embedded blocks in C++. With While C++ is relatively effective in some cases, it SystemC becoming a de-facto standard in high-level cannot handle typical properties of hardware such as modeling, a simulation approach had to be developed concurrency. SystemC [3] has recently emerged as a which makes effective use of SystemC technology by C++-compatible extension, which is able to model encapsulating such “threads” into the fault simulation such effects. For a real system-level fault simulation, environment. Furthermore, it can be shown that concurrency becomes a must. Therefore the SystemC allows the modeling of complex transistor- compatibility of SystemC concepts and structures with level structures, for which equivalent gate-level the basic approach followed with FIT had to be representations are not adequate.