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VHDL Vs. Systemc: Design of Highly Parameterizable Artificial Neural

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VHDL Vs. Systemc: Design of Highly Parameterizable Artificial Neural IEICE TRANS. INF. & SYST., VOL.E102–D, NO.3 MARCH 2019 512 PAPER VHDL vs. SystemC: Design of Highly Parameterizable Artificial Neural Networks David ALEDOya), Member, Benjamin CARRION SCHAFERyy, and Felix´ MORENOy, Nonmembers SUMMARY This paper describes the advantages and disadvantages which includes a dedicated hardware module for the ANN. observed when describing complex parameterizable Artificial Neural Net- Typical speed-ups between 30-200x over SW implementa- works (ANNs) at the behavioral level using SystemC and at the Register tions have been reported [1]. Transfer Level (RTL) using VHDL. ANNs are complex to parameterize because they have a configurable number of layers, and each one of them Traditional Hardware Description Languages (HDLs) has a unique configuration. This kind of structure makes ANNs, a pri- like VHDL and Verilog, provide mechanisms to parameter- ori, challenging to parameterize using Hardware Description Languages ize descriptions. One most notorious examples includes the (HDL). Thus, it seems intuitively that ANNs would benefit from the raise use of generics in VHDL. Nevertheless, one additional trend in level of abstraction from RTL to behavioral level. This paper presents the results of implementing an ANN using both levels of abstractions. Results that is happening to further speed-up the design of ICs, is to surprisingly show that VHDL leads to better results and allows a much raise the level of abstraction from Register Transfer Level higher degree of parameterization than SystemC. The implementation of (RTL) to behavioral level. This implies that software de- these parameterizable ANNs are made open source and are freely available scriptions initially intended to be compiled on a fixed archi- online. Finally, at the end of the paper we make some recommendation for tecture are synthesized through High-Level Synthesis (HLS) future HLS tools to improve their parameterization capabilities. ff key words: VHDL, SystemC, high-level synthesis (HLS), artificial neural into an RTL description that can e ectively execute it. All network (ANN) modern commercial HLS tools can take SystemC as input. SystemC is a C++ class that allows to model concurrency 1. Introduction and has been standardize by the IEEE [2], [3]. Raising the level of abstraction has numerous advan- With the increase time to market pressure, companies are re- tages. One that can be applied to ANNs is that it allows, in lying on third party IPs (3PIPs), which are often highly pa- theory, a much wider set of parameterization compared to low-level HDLs. Thus, using C-based VLSI design should rameterizable to create their complex digital circuits. They ffi are also dedicating much effort to develop modules in-house lead to the designer of easier and more e cient ANNs. which can be re-used in future projects. Artificial Neural Whereas Ad-Hoc optimizations are described in a low ab- straction level in order to take advantage of low-level de- Networks (ANNs) do not escape this trend. Thus, it makes ffi sense to have highly parameterizable ANN descriptions that tails. Hence, these descriptions are di cult to reuse. The can be used in multiple different applications. Some param- high-level descriptions are more general, therefore they are eters include, the number of layers, number of neurons and more likely to be reused. activation function. This work presents our experience creating highly pa- rameterizable ANNs using VHDL and SystemC. Both levels ANNs have gained tremendous importance recently. ff They belong to the group of artificial intelligence (AI) be- of abstractions will be compared and the di erent configura- cause they have the capability of learning. Their name tion parameters exposed. Finally we make some recommen- comes from the fact that they are biologically inspired on dations of how to enhance the way HLS tools parameterize a simple model of a neuron, connected in a network sim- behavioral descriptions for synthesis. In particular the con- ilar to the brain ones. ANNs have an enormous amount tributions of this work can be summarized as: of parallelism, making them excellent candidates for hard- • Study the key parameters that allow the description of ware (HW) acceleration. This allows the full exploitation highly parametrizable, and thus, re-usable, ANNs in of this parallelism while being extremely energy efficient SystemC and VHDL. compared to using general purpose solutions. The latest • Present experimental results, which quantify the effect A11 Bionic application processor or Apple is one example, of these parameters on the number of ANN configura- tions and quality of the ANNs. Manuscript received April 19, 2018. • Propose suggestions when designing at behavioral Manuscript revised September 21, 2018. Manuscript publicized November 29, 2018. level to improve configurability. y • The authors are with the CEI, Universidad Politecnica´ de Open source release of the ANNs described in Sys- Madrid, Spain. temC and RTL. yyThe author is with Department of Electrical and Computer Engineering, University of Texas at Dallas, USA. It should be noted that the main aim of this work is not a) E-mail: [email protected] to develop a specific ANN, but to understand the trade-offs DOI: 10.1587/transinf.2018EDP7142 and limitations between the different levels of abstractions Copyright ⃝c 2019 The Institute of Electronics, Information and Communication Engineers ALEDO et al.: VHDL VS. SYSTEMC 513 when designing complex IPs like ANNs. ple, for inserting it directly on the FPGA programming tool The contents of this paper are organized as follows. like Vivado without needing to call an external tool to re- First, a summary of related work on HW ANNs is given in write the IP code every time that it is reconfigured. Besides, Sect. 2. Then, background information about ANNs is given it allows to make changes or add new functionality directly in Sect. 3. Then, the implementation at the RTL (VHDL) is into the source code, and reuse the code in other projects. shown on Sect. 4. Basic knowledge of VHDL is expected by On the other hand, frameworks obscure the source code or the reader. Nevertheless, advanced and key points of VHDL make it inaccessible. are explained. Section 5 is divided on three parts. The first, In summary, much work in the area of hardware im- introduces main concepts of HLS, the second one describes plementations of ANNs is currently being done. We believe SystemC, and the third one shows the ANN description in that this work is complementary to this previous work as it SystemC. The next section compares both approaches and not only describes in detailed how to design highly flexible analysis the two methodologies in Sect. 6. The last section ANNs at the behavioral and RT-Level, but also compares summarizes and concludes the presented work. both approaches and finally exposes some of the limitations in current methodologies, making suggestions on how to re- 2. Related Work lieve these. Although the ANN implementation into an FPGA is used in 3. Artificial Neuronal Network (ANN) Background this paper as an application example of a complex param- eterizable design for the methodology and language anal- The mathematical model of a neuron is shown in Eq. (1). ysis, it is still a hot-topic. A large variety of ANN hard- This model performs a weighted sum of the inputs and then ware implementations have been published targeting FP- applies an activation function to the output. The activation GAs, ASICs, or both [4]–[6]. In most of this previous work, function is usually a linear function or a sort of saturation the ANN is described at the RT-level, using either VHDL or function like sigmoid functions. 0 1 Verilog. More recent work use HLS to construct the ANNs. BXM C B C Some examples include [7]–[14], of which [15], [16] make yi = f @B wi j · x j + biAC ; (1) use of SystemC. j=1 The contribution of this paper in not only the improved with i = 1;:::; N, where x j are the inputs, wi j the weights, level of configurability of the ANN, but also the analysis and bi the bias, f () the activation function, yi the outputs, M the comparison of both design methodologies (Behavioral vs. number of inputs, and N the number of neurons. RTL); and more important, the points of improvement for One neuron alone can do very few things, but com- future HLS tools, as a conclusion of this analysis. Achieving bined together, they can perform complicated tasks. As in a a good level of configurability at the RTL, as will be shown brain, neurons are grouped by layers and connected in a way in Sect. 4, is not complicated. A good example is [17]. In that the outputs of a layer become inputs for the next layer. this previous work, the authorts parameterize an ANN in a Certain kind of ANNs called Recurrent Neural Networks similar way using generics and generate statements. How- (RNN) allow feedback connections, although both of the ever, our VHDL IP includes three kinds of layers in order to implementations described on this paper only allow feed- make it even more flexible in terms of area vs. performance forward connections. Every neuron in a layer uses the same trade-off. In [18], the authors also use a parameterizable activation function. Figure 1 shows a general feedforward VHDL IP to perform a DSE with their own tool. ANN architecture. The small nodes represent the inputs of In addition in [19], the authors have a parameterizable the network, and the large ones perform the Eq. (1). SystemC-TML code for DSE and simulation, however they The last layer is called output layer, since is the one have to convert it to synthesizable SystemC for the selected which generates the network’s outputs.
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