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UNIVERSITY of CALIFORNIA RIVERSIDE Emulation of Systemc UNIVERSITY OF CALIFORNIA RIVERSIDE Emulation of SystemC Applications for Portable FPGA Binaries A Dissertation submitted in partial satisfaction of the requirements for the degree of Doctor of Philosophy in Computer Science by Scott Spencer Sirowy June 2010 Dissertation Committee: Dr. Frank Vahid, Chairperson Dr. Tony Givargis Dr. Sheldon X.-D. Tan Copyright by Scott Spencer Sirowy 2010 The Dissertation of Scott Spencer Sirowy is approved: Committee Chairperson University of California, Riverside ABSTRACT OF THE DISSERTATION Emulation of SystemC Applications for Portable FPGA Binaries by Scott Spencer Sirowy Doctor of Philosophy, Graduate Program in Computer Science University of California, Riverside, June 2010 Dr. Frank Vahid, Chairperson As FPGAs become more common in mainstream general-purpose computing platforms, capturing and distributing high-performance implementations of applications on FPGAs will become increasingly important. Even in the presence of C-based synthesis tools for FPGAs, designers continue to implement applications as circuits, due in large part to allow for capture of clever spatial, circuit-level implementation features leading to superior performance and efficiency. We demonstrate the feasibility of a spatial form of FPGA application capture that offers portability advantages for FPGA applications unseen with current FPGA binary formats. We demonstrate the portability of such a distribution by developing a fast on-chip emulation framework that performs transparent optimizations, allowing spatially-captured FPGA applications to immediately run on FPGA platforms without costly and hard-to-use synthesis/mapping tool flows, and sometimes faster than PC-based execution. We develop several dynamic and transparent optimization techniques, including just-in-time compilation , bytecode acceleration , and just-in-time synthesis that take advantage of a platform’s available resources, resulting in iv orders of magnitude performance improvement over normal emulation techniques and PC-based execution. v Table of Contents Chapter 1............................................................................................................................. 1 Chapter 2........................................................................................................................... 11 2.1 Overview........................................................................................................... 11 2.2 C is for Circuits................................................................................................. 11 2.2.1 Overview................................................................................................... 11 2.2.2 A Motivating Example – Sorting.............................................................. 15 2.2.3 Study Methodology................................................................................... 16 2.2.4 Example – Gaussian Noise Generator ...................................................... 21 2.2.5 Example – Molecular Dynamics Simulator.............................................. 27 2.2.6 Example - Cellular Learning Automata-Based Evolutionary Computing 29 2.2.7 More Experiments..................................................................................... 31 2.3 Other Related Work.......................................................................................... 37 2.3.1 C-based Synthesis Tools........................................................................... 37 2.3.2 Parallel Languages.................................................................................... 38 2.3.3 Portability.................................................................................................. 38 2.4 Requirements of a Language for Spatial Capture............................................. 39 2.4.1 POSIX....................................................................................................... 41 2.4.2 Other Thread-Based Approaches.............................................................. 43 2.4.3 SystemC.................................................................................................... 44 Chapter 3........................................................................................................................... 47 3.1 Overview........................................................................................................... 47 3.2 Related Work .................................................................................................... 50 3.3 SystemC-on-a-Chip Components ..................................................................... 51 3.3.1 SystemC Bytecode Compiler.................................................................... 51 3.3.2 SystemC Bytecode Format ....................................................................... 53 3.3.3 USB Download Interface.......................................................................... 57 3.3.4 SystemC Emulation Engine...................................................................... 58 3.4 Experiments ...................................................................................................... 61 Chapter 4........................................................................................................................... 65 4.1 Overview........................................................................................................... 65 4.2 Related Work .................................................................................................... 68 4.3 Online SystemC Emulation Architecture.......................................................... 70 4.3.1 Base Architecture with Acceleration Engines .......................................... 70 4.3.2 Kernel Bypass........................................................................................... 72 4.4 Online Acceleration Assignment...................................................................... 73 4.4.1 Problem Definition.................................................................................... 73 4.4.2 Communication Overhead........................................................................ 76 4.5 Online Heuristics .............................................................................................. 76 4.5.1 Upper and Lower Bounds......................................................................... 76 vi 4.5.2 Accelerator Static Assignment.................................................................. 77 4.5.3 Greedy Heuristic....................................................................................... 77 4.5.4 Aggregate Gain......................................................................................... 78 4.6 Experiments ...................................................................................................... 79 4.6.1 Framework................................................................................................ 79 4.6.2 Evaluation................................................................................................. 81 Chapter 5........................................................................................................................... 84 5.1 Overview........................................................................................................... 84 5.2 Related Work .................................................................................................... 86 5.3 Experimental Setup........................................................................................... 87 5.4 Just-in-Time Compilation of SystemC ............................................................. 89 5.4.1 Compilation............................................................................................... 89 5.4.2 JIT Compilation with Dedicated JIT Memory Resources ........................ 91 5.4.3 Emulation Memory Controller.................................................................. 94 Chapter 6........................................................................................................................... 98 6.1 Overview........................................................................................................... 98 6.2 Related Work .................................................................................................... 99 6.3 Just-in-Time Synthesis.................................................................................... 101 6.3.1 Server-Side Synthesis Framework.......................................................... 101 6.3.2 Decompilation and Synthesis.................................................................. 104 6.3.3 SystemC-on-a-Chip Architectural Support............................................. 105 6.4 Experiments .................................................................................................... 108 Chapter 7......................................................................................................................... 111 7.1 Overview......................................................................................................... 111 7.2 SystemC for Synchronized Physiological Models.......................................... 115 7.3 Related Work .................................................................................................. 118 7.4 Time-Controllable Digital Mockup Execution............................................... 119 7.5 Experiments ...................................................................................................
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