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System Modeling & HW/SW Co-Verification

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System Modeling & HW/SW Co-Verification System Modeling & HW/SW Co-Verification Prof. Chien-Nan Liu TEL: 03-4227151 ext:4534 Email: [email protected] 1 Outline l Introduction l System Modeling Languages l SystemC Overview l Data-Types l Processes l Interfaces l Simulation Supports l System Design Environments l HW/SW Co-Verification l Conclusion 2 Outline l Introduction l System Modeling Languages l SystemC Overview l Data-Types l Processes l Interfaces l Simulation Supports l System Design Environments l HW/SW Co-Verification l Conclusion 3 Design Challenges Reference http://www.doulos.com 4 Silicon complexity v.s Software complexity Silicon complexity is growing 10x Software in systems is growing faster every 6 years than 10x every 6 years Reference http://www.doulos.com 5 Increasing Complexity in SoC Designs l One or more processors l 32-bit Microcontrollers l DSPs or specialized media processors l On-chip memory l Special function blocks l Peripheral control devices l Complex on-chip communications network (On-chip busses) l RTOS and embedded software which are layering architecture l …… 6 How to Conquer the Complexity ? l Modeling strategies – Using the appropriate modeling for different levels – The consistency and accuracy of the model l Reuse existing designs – IP reuse – Architecture reuse (A platform based design) l Partition – Based on functionality – Hardware and software 7 Traditional System Design Flow (1/2) l Designers partition the system into hardware and software early in the flow l HW and SW engineers design their respective components in isolation l HW and SW engineers do not talk to each other l The system may not be the suitable solution l Integration problems l High cost and long iteration 8 Traditional System Design Flow (2/2) nn System System Level Level D Designesign nn Hardware Hardware and and Software Software nn Algorithm Algorithm Developm Developmentent nn Processor Processor Selection Selection nn Done Done mainly mainly in in C/C++ C/C++ C/C++C/C++ Environment Environment nn IC IC Development Development Verification Process ww Software Software Design Design nn Hardware Hardware ww Code Code Development Development nn Implementation Implementation ww R RTTOOSS details details nn Decisions Decisions $ $ $ ww Done Done mainly mainly in in C/C++ C/C++ nn Done Done mainly mainly in in HDL HDL EDAEDA Environment Environment C/C++C/C++ Environment Environment Reference : Synopsys 9 Typical Project Schedule System Design Hardware Design Prototype Build Hardware Debug Software Design Software Coding Software Debug Reference : Mentor Graphic Project Complete 10 Former Front-End Design Flow Convert by Hand C/C++C/C++ System System LevelLevel Model Model Verilog Verilog Verilog TestbenchTestbench AnalysisAnalysis SimulationSimulation ResultsResults Refine SynthesisSynthesis Reference : DAC 2002 SystemC Tutorial 11 Problems with the Design Flow Convert by Hand C/C++C/C++ System System LevelLevel Model Model Verilog Verilog Verilog TestbenchTestbench AnalysisAnalysis Not reusable SimulationSimulation ResultsResults Refine SynthesisSynthesis ˝ Not done by designers ˝ The netlist is not preserved Reference : DAC 2002 SystemC Tutorial 12 Shortcoming of Current System Design Flow l Use natural language to describe the system specification – Cannot verify the desired functions directly l Require many experts in system architecture for the partition of software and hardware parts – The partition may not be the optimal solution l Hardware designers have to restart the design process by capturing the designs using the HDLs – May have unmatched problems l Hardware and software integration is often painful – Hardware and software cannot work together – Co-verification of hardware and software is inefficient 13 Concurrent HW/SW Design l Can provide a significant performance improvement for embedded system design – Allows earlier architecture closure – Reduce risk by 80% l Allows HW/SW engineering groups to talk together l Allows earlier HW/SW Integration l Reduce design cycle – Develop HW/SW in parallel – 100x faster than RTL 14 Project Schedule with HW/SW Co-design System Design Hardware Design Prototype Build Hardware Debug Software Design Software Coding Software Debug Reference : Mentor Graphic Project Complete 15 Modern System Design Flow Specification of the System System Level Modeling Hardware and Software Partitioning Architectural Exploration H/W Model S/W Model H/W Design Flow S/W Development Integration and Verification 16 Outline l Introduction l System Modeling Languages l SystemC Overview l Data-Types l Processes l Interfaces l Simulation Supports l System Design Environments l HW/SW Co-Verification l Conclusion 17 Motivation to Use a Modeling Language l The increasing system design complexity l The demand of higher level abstraction and modeling l Traditional HDLs (verilog, VHDL, etc) are suitable for system level design – Lack of software supports l To enable an efficient system design flow 18 Requirements of a System Design Language l Support system models at various levels of abstraction l Incorporation of embedded software portions of a complex system – Both models and implementation-level code l Creation of executable specifications of design intent l Creation of executable platform models – Represent possible implementation architectures on which the design intent will be mapped 19 Requirements of a System Design Language l Fast simulation speed to enable design-space exploration – Both functional specification and architectural implementation alternatives l Constructs allowing the separation of system function from system communications – In order to allow flexible adaptation and reuse of both models and implementation l Based on a well-established programming language – In order to capitalize on the extensive infrastructure of capture, compilation, and debugging tools already available 20 Model Accuracy Requirements l Structural accuracy l Timing accuracy l Functional accuracy l Data organization accuracy l Communication protocol accuracy 21 System Level Language SystemC Cynlib C/C++ Based SoC++ Handel-C A/RT (Library) VHDL/Verilog VHDL+ Replacements System-Level Modeling System Language Verilog Higher-level Languages SDL SLDL Entirely New Languages SUPERLOG Java-Based Java 22 Language Use C/C++ SystemC TestBuilder, Verilog SUPERLOG 2.0 OpenVer,e VHDL Very Embedded Good NO NO NO SW Good System Very Level OK Excel NO Good Design Poor Very Verification OK Good Excel OK Good RTL Design NO Good NO Excel Excel Reference : DAC 2002 SystemC Tutorial 23 Trend of System-Level Languages l Extend existing design languages (ex: SystemVerilog) – Pros: • Familiar languages and environments to designers • Allow descriptions of prior version of Verilog – Cons: • Not standardized yet • Become more and more complex to learn l Standard C/C++ based languages (ex: SystemC) – Pros: • Suitable for very abstract descriptions • Suitable to be an executable specification – Cons: • A new language to learn • Need solutions for the gap to traditional design flow 24 Evolution of Verilog Language l Proprietary design description language developed by Gateway, 1990 – Donated to OVI(Open Verilog International) by Cadence l Verilog Hardware Description Language LRM by OVI, V2.0 1993 l IEEE Std. 1364-1995, “Verilog 1.0” (called Verilog-1995) l Synopsys proposed Verilog-2000, including synthesizable subset l IEEE Std. 1364-2001, “Verilog 2.0” (called Verilog-2001) (1st main enhancement) l SystemVerilog 3.0, approved as an Accellera standard in June 2002 – add system-level architectural modeling l SystemVerilog 3.1, approved as an Accellera standard in May, 2003 – add verification and C language integration (Not yet as standard) l Verilog Standards Group(IEEE 1364) announced a project authorization request for 1364-2005 25 Compatibility of SystemVerilog ANSI C-style ports, named parameter passing, comma-separated sensitivity lists and attributes SystemVerilog 3.0/3.1 Verilog-1995 Verilog- 2001 earliest Verilog initialization of variables, the semantics of "posedge" and "negedge" constructs, record-like constructs, handling of interfaces and various keywords 26 Enhancements in SystemVerilog l C data types l Interfaces to encapsulate l Dynamic processes l A unique top level hierarchy ($root) l Verification functionality l Synchronization l Classes l Dynamic memory l Assertion mechanism l …… 27 Summary about SystemVerilog l More extension in high-level abstraction to the Verilog-2001 standard – Still no much enhancement in transaction-level abstraction l Improves the productivity and readability of Verilog code l Provide more concise hardware descriptions l Extends the verification aspects of Verilog by incorporating the capabilities of assertions – Still no coverage construct within testbench design l 3.0/3.1 LRM are still not very clear in more details l Not yet simulator support – No compiler for trying its syntax l SV is a valuable direction to be watched – Will it become too complex for most designers/verification engineers’ requirement/understanding?? 28 Reference for SystemVerilog l SystemVerilog 3.1, ballot draft: Accellera's Extensions to Verilog? Accellera, Napa, California, April 2003. l Verilog 2001: A Guide to the new Verilog Standard? Stuart Sutherland, Kluwer Academic Publishers, Boston, Massachusetts, 2001 l An overview of SystemVerilog 3.1, By Stuart Sutherland, EEdesign, May 21, 2003 http://www.eedesign.com/story/OEG20030521S0086 URL: 1) http://www.eda.org/sv-ec/ (SystemVerilog Testbench Extension Committee) 2) http://www.eda.org/sv-ec/SV_3.1_Web/index.html
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