An Introduction to High-Level Synthesis
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Die Virtuelle Plattform: Der Einsatz Von Zynq Fuer Die Verifikation Und Das Debugging Von Konfigurierbaren Systemen
Die virtuelle Plattform: Der Einsatz von Zynq fuer die Verifikation und das Debugging von konfigurierbaren Systemen Dr. Endric Schubert Missing Link Electronics Marlene-Dietrich-Straße 5 89231 Neu-Ulm www.missinglinkelectronics.com Tel: +49 (731) 141-149-0 Courtesy Xilinx 1 Challenges of Debugging Your Own ASSP © Missing Link Electronics 12. Juli 2012 2 Another Challenge When Building Your Own ASSP: Making Hardware and Software Work Together. © Missing Link Electronics 12. Juli 2012 3 ASSP System-on-Chip Design – An Embedded Designers Life © Missing Link Electronics 12. Juli 2012 4 What is a Virtual Platform? © Missing Link Electronics 12. Juli 2012 5 Virtual Platform Methodology © Missing Link Electronics 12. Juli 2012 6 Virtual Platforms Can Run Software Fast (Sometimes Faster Than Real) © Missing Link Electronics 12. Juli 2012 7 What is SystemC? Open Source Library managed by Open SystemC Initiative (OSCI) Extension to ISO C++ www.systemc.org Means to express concurrency Communication mechanisms Reactivity Concept of Time Current members: ARM Ltd. Cadence Design Systems, Inc. CoWare, Inc. Forte Design Systems Intel Event driven simulation kernel Corporation Mentor Graphics Corporation NXP Semiconductors STMicroelectronics Synopsys, Inc. Actis Design, LLC Atrenta, Inc. Bluespec, Inc. Broadcom - A modeling methodology Corporation Calypto Design Systems, Inc. Canon Inc. Carbon Design Systems Celoxica Ltd. ChipVision Design Systems AG Denali Software Inc. Doulos Ltd. ESLX, Inc. Fraunhofer Institute for Integrated Circuits Freescale Semiconductor Inc. GreenSocs Ltd. Industrial Technology Research Institute (ITRI) JEDA Technologies Inc. Infineon Technologies AG NEC Corporation Semiconductor Technology Academic Research Center (STARC) SpringSoft, Inc. Synfora Inc. Tenison EDA VaST Systems Technology Corporation © Missing Link Electronics 12. -
Download the Compiled Program File Onto the Chip
International Journal of Computer Science & Information Technology (IJCSIT) Vol 4, No 2, April 2012 MPP SOCGEN: A FRAMEWORK FOR AUTOMATIC GENERATION OF MPP SOC ARCHITECTURE Emna Kallel, Yassine Aoudni, Mouna Baklouti and Mohamed Abid Electrical department, Computer Embedded System Laboratory, ENIS School, Sfax, Tunisia ABSTRACT Automatic code generation is a standard method in software engineering since it improves the code consistency and reduces the overall development time. In this context, this paper presents a design flow for automatic VHDL code generation of mppSoC (massively parallel processing System-on-Chip) configuration. Indeed, depending on the application requirements, a framework of Netbeans Platform Software Tool named MppSoCGEN was developed in order to accelerate the design process of complex mppSoC. Starting from an architecture parameters design, VHDL code will be automatically generated using parsing method. Configuration rules are proposed to have a correct and valid VHDL syntax configuration. Finally, an automatic generation of Processor Elements and network topologies models of mppSoC architecture will be done for Stratix II device family. Our framework improves its flexibility on Netbeans 5.5 version and centrino duo Core 2GHz with 22 Kbytes and 3 seconds average runtime. Experimental results for reduction algorithm validate our MppSoCGEN design flow and demonstrate the efficiency of generated architectures. KEYWORD MppSoC, Automatic code generation; mppSoC configuration;parsing ; MppSoCGEN; 1. INTRODUCTION Parallel machines are most often used in many modern applications that need regular parallel algorithms and high computing resources, such as image processing and signal processing. Massively parallel architectures, in particular Single Instruction Multiple Data (SIMD) systems, have shown to be powerful executers for data-intensive applications [1]. -
ECD.June.2013.Pdf
-community Post Joining the embedded conversation -community Post Joining the embedded conversation ON THE COVER Embedded Computing Design editors have been on the lookout for this year’s Top Embedded Innovators, and – for the first time this year -– thecommunity Most Influential Women in Post Embedded. Our two contests pulled in many inspirational, www.embedded-computing.com highly qualified candidatesJoining who are theforging embedded new ideas conversation and making a difference in the embedded industry. Read June 2013 | Volume 11 • Number 4 about the winners in this edition’s exclusive Q&As, and check out the nominees for Most Innovative Product, winners to be announced in our August edition. 7 Tracking Trends in Embedded Technology 54 -community Post Top Innovators streamline embedded technology Joining the embedded conversation By Warren Webb By Sharon Hess Silicon Software Strategies Multicore processors Finding an operating system Small form factors 8 24 31 Moving target: EEMBC evolves ▲ Choose the right ▲ VPX helps programmable 28 its benchmark suites to keep pace embedded operating system field of dreams become reality with the multicore revolution By Warren Webb By Kevin Roth, Alpha Data Q&A with Markus Levy, Founder and President of EEMBC Case study: 31 Challenges in incarnating a ARM’s big.LITTLE 11 EXPERT PANEL: 14 credit card sized SBC architecture aims to satisfy the Is EDA as easy as By Pete Lomas, Raspberry Pi hunger for power 1, 2, 3 these days? Q&A with John Goodacre, Director, Roundtable discussion with Wally Rhines, Chairman Technology and Systems, ARM Processor Division and CEO, Mentor Graphics; Brett Cline, Vice President, Forte Design Systems; Marc Serughetti, Business Development Director, Synopsys; Michał Siwinski,´ Director of Product Marketing at Cadence; Bill Neifert, 52 Cofounder and CTO, Carbon Design Systems Editor’s Choice By Sharon Hess Top Embedded Innovators Josh Lee, Cofounder, President, and CEO at Uniquify 34 Darren Humphrey, Sr. -
Inside Chips
InsideChips.VenturesTM Tracking Fabless, IP & Design-House Startups Volume 6, Number 7 July 2005 Business Microscope 3-D Chip Trends … For more than 30 years, the yearly conference explores market and technology chipmakers have been riding the Moore’s Law speed opportunities in the 3-D space. and performance wave. Without fail, they have been Universities, institutes/consortia, IDMs and a able to rely on reductions in transistor size used in ICs handful of startups are conducting 3-D research to achieve predicted increases in speed and around the world. Table 1 (page 2) highlights the performance. Moore’s Law, which states that chip notable players. DARPA funds most of the university performance doubles approximately every two years, programs in the U.S. held true because the RC delay has been negligible in comparison with signal propagation delay. For Initial 3-D efforts involved package stacking or submicron technology, however, RC delay becomes chip stacking in a single package with wire bond a dominant factor. As the industry moves to submicron feature interconnects. Amkor is a good illustration of this approach. sizes, shrinking two-dimensional chips will become problematic. Begun in 1998, the technology was primarily used for memory stacks. One emerging solution is 3-D integration. The technology is not new but it is becoming increasingly important as researchers One of the early pioneers of 3-D, Irvine Sensors, developed look for solutions beyond the perceived limits of today’s two- stacked chips in which the connections are made over the edge of dimensional devices. the die. One limitation, however, is that all die must be the same size. -
The Challenges of Hardware Synthesis from C-Like Languages
The Challenges of Hardware Synthesis from C-like Languages Stephen A. Edwards∗ Department of Computer Science Columbia University, New York Abstract most successful C-like languages, in fact, bear little syntactic or semantic resemblance to C, effectively forcing users to learn The relentless increase in the complexity of integrated circuits a new language anyway. As a result, techniques for synthesiz- we can fabricate imposes a continuing need for ways to de- ing hardware from C either generate inefficient hardware or scribe complex hardware succinctly. Because of their ubiquity propose a language that merely adopts part of C syntax. and flexibility, many have proposed to use the C and C++ lan- For space reasons, this paper is focused purely on the use of guages as specification languages for digital hardware. Yet, C-like languages for synthesis. I deliberately omit discussion tools based on this idea have seen little commercial interest. of other important uses of a design language, such as validation In this paper, I argue that C/C++ is a poor choice for specify- and algorithm exploration. C-like languages are much more ing hardware for synthesis and suggest a set of criteria that the compelling for these tasks, and one in particular (SystemC) is next successful hardware description language should have. now widely used, as are many ad hoc variants. 1 Introduction 2 A Short History of C Familiarity is the main reason C-like languages have been pro- Dennis Ritchie developed C in the early 1970 [18] based on posed for hardware synthesis. Synthesize hardware from C, experience with Ken Thompson’s B language, which had itself proponents claim, and we will effectively turn every C pro- evolved from Martin Richards’ BCPL [17]. -
A Compiler Infrastructure for Static and Hybrid Analysis of Discrete Event System Models
UNIVERSITY OF CALIFORNIA, IRVINE A Compiler Infrastructure for Static and Hybrid Analysis of Discrete Event System Models DISSERTATION submitted in partial satisfaction of the requirements for the degree of DOCTOR OF PHILOSOPHY in Computer Engineering by Tim Schmidt Dissertation Committee: Professor Rainer D¨omer,Chair Professor Kwei-Jay Lin Professor Fadi Kurdahi 2018 c 2018 Tim Schmidt TABLE OF CONTENTS Page LIST OF FIGURES v LIST OF TABLES vii LIST OF ALGORITHMS viii LIST OF ACRONYMS ix ACKNOWLEDGMENTS x CURRICULUM VITAE xii ABSTRACT OF THE DISSERTATION xvi 1 Introduction 1 1.1 System Level Design . .1 1.2 SystemC . .3 1.3 Recoding Infrastructure for SystemC (RISC) . .7 1.3.1 Software Stack . .7 1.3.2 Tool Flow . .8 1.4 Segment Graph . 11 1.5 Goals . 19 1.6 Related Work . 22 1.6.1 LECS Group . 22 1.6.2 Other Related Work . 25 2 Static Communication Graph Generation 28 2.1 Introduction . 28 2.1.1 Related work . 31 2.2 Thread Communication Graph . 32 2.3 Static Compiler Analysis . 34 2.3.1 Thread Communication Graph . 34 2.3.2 Module Hierarchy . 37 2.3.3 Optimization and Designer Interaction . 38 2.3.4 Visualization . 38 2.3.5 Accuracy and Limitations . 39 ii 2.4 Experiments . 39 2.4.1 Mandelbrot Renderer . 39 2.4.2 AMBA Bus Model . 41 2.4.3 S2C Testbench . 42 2.5 Summary . 43 3 Static Analysis for Reduced Conflicts 45 3.1 Channel Analysis . 45 3.1.1 Introduction . 46 3.1.2 Conflict Analysis . 49 3.1.3 Port Call Path Sensitive Segment Graphs . -
Exhibition Report
Exhibition Report Japan Electronics and Information Technology Industries Association (JEITA) Contents Exhibition Outline 1 Exhibition Configuration 2 1. Scope of Exhibits 2 2. Conference 2 3. Number of Exhibitors and Booths 2 4. Suite Exhibits 2 5. Exhibitors 3 Conference Activities 4 1. Exhibitor Seminars 4 2. Keynote Speech 4 3. Special Event Stage 4 4. The 13th FPGA/PLD Design Conference 4 5. FPGA/PLD Design Conference User’s Presentations 4 6. IP(Intellectual Property) Flea Market in EDSFair 4 7. System Design Forum 2006 Conference 4 Other Events and Special Projects 5 1. Opening Ceremony 5 2. University Plaza 5 3. Venture Conpany Pavilion 5 4. EDAC Reception 5 5. Press 5 Number of Visitors 6 Results of Visitor Questionnaire 6-7 Exhibition Outline Name . Electronic Design and Solution Fair 2006 (EDSFair2006) Duration . Thursday, January 26 and Friday, January 27, 2006 (2 days) 10:00 a.m. to 6:00 p.m. Location . Pacifico Yokohama (Halls C-D hall and Annex Hall) 1-1-1 Minato Mirai, Nishi-ku, Yokohama 220-0012, Japan Admission. Exhibition: Free (registration required at show entrance) Conference: Fees charged for some sessions Sponsorship . Japan Electronics and Information Technology Industries Association (JEITA) Cooperation . Electronic Design Automation Consortium (EDAC) Support . Ministry of the Economy, Trade and Industry, Japan (METI) Embassy of the United States of America in Japan Distributors Association of Foreign Semiconductors (DAFS) City of Yokohama Assistance . Institute of Electronics, Information and Communication Engineers (IEICE) Information Processing Society of Japan (IPSJ) Japan Printed Circuit Association (JPCA) Spacial Assistance. Hewlett-Packard Japan, Ltd. Sun Microsystems K.K Management . -
Xcell Journal Issue 50, Fall 2004
ISSUE 50, FALL 2004ISSUE 50, FALL XCELL JOURNAL XILINX, INC. Issue 50 Fall 2004 XcellXcelljournaljournal THETHE AUTHORITATIVEAUTHORITATIVE JOURNALJOURNAL FORFOR PROGRAMMABLEPROGRAMMABLE LOGICLOGIC USERSUSERS MEMORYMEMORY DESIGNDESIGN Streaming Data at 10 Gbps Control Your QDR Designs PARTNERSHIP 20 Years of Partnership Author! Author! Programmable WorldWorld 20042004 SOFTWARE Algorithmic C Synthesis The Need for Speed MANUFACTURING Lower PCB Mfg. Costs Optimize PCB Routability R COVER STORY FPGAs on Mars The New SPARTAN™-3 Make It You r ASIC The world’s lowest-cost FPGAs Spartan-3 Platform FPGAs deliver everything you need at the price you want. Leading the way in 90nm process technology, the new Spartan-3 devices are driving down costs in a huge range of high-capability, cost-sensitive applications. With the industry’s widest density range in its class — 50K to 5 Million gates — the Spartan-3 family gives you unbeatable value and flexibility. Lots of features … without compromising on price Check it out. You get 18x18 embedded multipliers for XtremeDSP™ processing in a low-cost FPGA. Our unique staggered pad technology delivers a ton of I/Os for total connectivity solutions. Plus our XCITE technology improves signal integrity, while eliminating hundreds of resistors to simplify board layout and reduce your bill of materials. With the lowest cost per I/O and lowest cost per logic cell, Spartan-3 Platform FPGAs are the perfect fit for any design … and any budget. MAKE IT YOUR ASIC The Programmable Logic CompanySM For more information visit www.xilinx.com/spartan3 Pb-free devices available now ©2004 Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124. -
Using Systemc for High-Level Synthesis and Integration with TLM
Using SystemC for high-level synthesis and integration with TLM Presented at India SystemC User Group (ISCUG) http://www.iscug.in April 14, 2013 Mike Meredith – VP Strategic Marketing Forte Design Systems © 2013 Forte Design Systems Agenda • High-level synthesis • Keys to raising abstraction level – A brief history of high-level – Implicit state machine synthesis vs explicit state machine – What is HLS? – Design exploration – HLS Basics – HLS and Arrays • Synthesizability – HLS and I/O protocols – Introduction to the • Integrating synthesizable code synthesizable subset standard in TLM models draft • User Experience – Recommendations and extensions © 2013 Forte Design Systems 2 A Brief History Of High-level Synthesis © 2013 Forte Design Systems 3 What’s In A Name? Algorithmic Behavioral Synthesis Synthesis ESL Synthesis High-level Synthesis © 2013 Forte Design Systems 4 Synthesizing Hardware From A High-level Description -- Not a New Idea! Generation 0 Generation 1 Generation 2 Research First Industrial Tools C-based Tools 1970’s 1980’s 1990’s 2000’s Today • Generation 0 - Research – 1970’s - 1990 – First mention (that I can find) - 1974 • CMU: Barbacci, Siewiorek “Some aspects of the symbolic manipulation of computer descriptions” – A sampling of key researchers: • Thomas, Paulin, Gajski, Wakabayashi, DeMann – Academic implementations • 1979 CMU - CMU-DA • 1988 Stanford Hercules – Most research focused on scheduling and allocation for datapath-dominated designs © 2013 Forte Design Systems 5 Generation 1 - 1990’s Generation 0 Generation -
Catapult DS 1-10 2PG Datasheet US.Qxd
C-B ase d D e s i g n Catapult C Synthesis D ATASHEET Major product features: • Mixed datapath and control logic synthesis from both pure ANSI C++ and SystemC • Multi-abstraction synthesis supports untimed, transaction-level, and cycle-accurate modeling styles • Full-chip synthesis capabilities including pipelined multi-block subsystems and SoC interconnects • Power, performance, and area exploration and optimization • Push button generation of RTL verification infrastructure • Advanced top-down and bottom-up hierarchical design management Catapult C Synthesis produces high-quality RTL implementations from abstract • Full and accurate control over design specifications written in C++ or SystemC, dramatically reducing design and interfaces with Interface Synthesis verification efforts. technology and Modular IO • Interactive and incremental design Tackle Complexity, Accelerate Time to RTL, Reduce Verification Effort methodology achieves fastest path to optimal hardware Traditional hardware design methods that require manual RTL development and debugging are too time consuming and error prone for today’s complex designs. • Fine-grain control for superior The Catapult® C Synthesis tool empowers designers to use industry standard ANSI quality of results C++ and SystemC to describe functional intent, and move up to a more productive • Built-in analysis tools including abstraction level. From these high-level descriptions Catapult generates production Gantt charts, critical path viewer, and quality RTL. With this approach, full hierarchical systems comprised of both cross-probing control blocks and algorithmic units are implemented automatically, eliminating the typical coding errors and bugs introduced by manual flows. By speeding time • Silicon vendor certified synthesis to RTL and automating the generation of bug free RTL, the Catapult C Synthesis libraries and integration with RTL tool significantly reduces the time to verified RTL. -
An Introduction to High-Level Synthesis
[3B2-8] mdt2009040008.3d 17/7/09 13:24 Page 8 High-Level Synthesis An Introduction to High-Level Synthesis Philippe Coussy Michael Meredith Universite´ de Bretagne-Sud, Lab-STICC Forte Design Systems Daniel D. Gajski Andres Takach University of California, Irvine Mentor Graphics today would even think of program- Editor’s note: ming a complex software application High-level synthesis raises the design abstraction level and allows rapid gener- solely by using an assembly language. ation of optimized RTL hardware for performance, area, and power require- In the hardware domain, specification ments. This article gives an overview of state-of-the-art HLS techniques and languages and design methodologies tools. 1,2 Tim Cheng, Editor in Chief have evolved similarly. For this reason, ÀÀ until the late 1960s, ICs were designed, optimized, and laid out by hand. Simula- THE GROWING CAPABILITIES of silicon technology tion at the gate level appeared in the early 1970s, and and the increasing complexity of applications in re- cycle-based simulation became available by 1979. Tech- cent decades have forced design methodologies niques introducedduring the 1980s included place-and- and tools to move to higher abstraction levels. Raising route, schematic circuit capture, formal verification, the abstraction levels and accelerating automation of and static timing analysis. Hardware description lan- both the synthesis and the verification processes have guages (HDLs), such as Verilog (1986) and VHDL for this reason always been key factors in the evolu- (1987), have enabled wide adoption of simulation tion of the design process, which in turn has allowed tools. These HDLs have also served as inputs to logic designers to explore the design space efficiently and synthesis tools leading to the definition of their synthe- rapidly. -
High Level Synthesis with Catapult
High Level Synthesis with Catapult 8.0 Richard Langridge European AE Manager 21 st January 2015 Calypto Overview • Background – Founded in 2002 – SLEC released 2005 & PowerPro 2006 – Acquired Mentor’s Catapult HLS technology and team in 2011 • Operations – Headquarters in San Jose with R&D in California, Oregon, NOIDA India – Sales and support worldwide, with new support office opened in Korea • Technology – Patented Deep Sequential Analysis Technology for verification and power optimization – Industry leading High-Level Synthesis technology – 30 patents granted; 17 pending • Customers – Over 130 customers worldwide • FY14 Results - Record revenue 2 Calypto Design Systems Calypto Design Systems’ Platforms Catapult HL Design & Verification Platform PowerPro RTL Low Power Platform 3 Calypto Design Systems Why Teams Want to Adopt HLS • Accelerate design time by working at higher level of void func (short a[N], abstraction for (int i=0; i<N; i++) { if (cond) – z+=a[i]*b[i]; New features added in days not weeks else – Address complexity through abstraction • Cut verification costs with 1000x speedup vs RTL – Faster design simulation in higher level languages – Easier functional verification and debug • Determine optimal microarchitecture – Rapidly explore multiple options for optimal Power Performance Area (PPA) • Facilitate collaboration, reuse and creation of derivatives – Technology and architectural neutral design descriptions RTL are easily shared, modified and retargeted – HLS becoming an IP enabler 4 Calypto Design Systems Catapult Delivers