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High Level Synthesis with Catapult

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High Level Synthesis with Catapult High Level Synthesis with Catapult 8.0 Richard Langridge European AE Manager 21 st January 2015 Calypto Overview • Background – Founded in 2002 – SLEC released 2005 & PowerPro 2006 – Acquired Mentor’s Catapult HLS technology and team in 2011 • Operations – Headquarters in San Jose with R&D in California, Oregon, NOIDA India – Sales and support worldwide, with new support office opened in Korea • Technology – Patented Deep Sequential Analysis Technology for verification and power optimization – Industry leading High-Level Synthesis technology – 30 patents granted; 17 pending • Customers – Over 130 customers worldwide • FY14 Results - Record revenue 2 Calypto Design Systems Calypto Design Systems’ Platforms Catapult HL Design & Verification Platform PowerPro RTL Low Power Platform 3 Calypto Design Systems Why Teams Want to Adopt HLS • Accelerate design time by working at higher level of void func (short a[N], abstraction for (int i=0; i<N; i++) { if (cond) – z+=a[i]*b[i]; New features added in days not weeks else – Address complexity through abstraction • Cut verification costs with 1000x speedup vs RTL – Faster design simulation in higher level languages – Easier functional verification and debug • Determine optimal microarchitecture – Rapidly explore multiple options for optimal Power Performance Area (PPA) • Facilitate collaboration, reuse and creation of derivatives – Technology and architectural neutral design descriptions RTL are easily shared, modified and retargeted – HLS becoming an IP enabler 4 Calypto Design Systems Catapult Delivers QoR and Crushes RTL Design Time Catapult results on customer designs 5 Calypto Design Systems High-Level Synthesis : Evolution 6 Calypto Design Systems Early Generations of HLS Circa 1997 • Generation 1 (1997) Synopsys Behavioral Complier 1 Monet – Incremental raising of abstraction – Limited value Circa 2004 Mentor Catapult C Forte 2 Circa 2009 • Generation 2 (2004) Calypto Catapult Cadence C2S – Move to standardized high level Forte languages – Raised abstraction level – Big gain in top down optimization algorithms – Circa 2009: Control logic improvements 7 Calypto Design Systems 3rd Generation HLS – Introducing Catapult 8 Circa 1997 • Control and predictability required Synopsys Behavioral Complier Monet to achieve design closure 1 – Configurable design hierarchy with 10x capacity Circa 2004 Mentor Catapult C • Integration with corporate and Forte standard RTL methodologies 2 Circa 2009 Calypto Catapult – Creates verification-optimized RTL Cadence C2S Forte • Native unified SystemC and C++ support – Teams can choose, companies use both • New “Catware” IP design libraries 2014 3 Calypto Catapult 8 8 Calypto Design Systems Catapult 8 – Customer Reception The Third Generation High-Level Synthesis and Verification Platform Enabling Widespread Adoption of HLS “Catapult 8 allows rapidly evolving “We write either C++ or SystemC, depending C++ algorithms to be explored and on the design and verification needs of each optimized to meet our area, power project, and then use Catapult’s configurable and performance goals.” hierarchy technology, which makes it possible to synthesize much bigger designs.” Michael Giovannini, Hardware project leader in Front-End team of Unified Platform Division for Emmanuel Liégeon, Head of ASIC/FPGA Design Group at STMicroelectronics Thales Alenia Space France 9 Calypto Design Systems High-level Synthesis : Catapult 8 10 Calypto Design Systems What is High -level Synthesis? • Two core capabilities define HLS 1. Mapping from abstract transactions to pin-accurate protocols Control i/f A A X X I I 2. Optimizing C/SystemC for performance/area/power in target technology TP = 1 Control i/f LT < 100 300MHz i o = f(i,s) o 11 Calypto Design Systems Catapult HLS – Design at a Higher Level • Introduced in 2004 – 1000s of tape outs void func (short a[N], for (int i=0; i<N; i++) { • if (cond) Automatic generation of high quality RTL z+=a[i]*b[i]; from high level descriptions else – ANSI C/C++ and SystemC support – Designs are correct-by-construction – Manual errors are avoided – Time-consuming iterations are eliminated • Focus on function, not implementation – Fewer lines of code • Easier to understand • Easier to modify • Easier to maintain – Easy migration to new technology – Bridges the gap between specification & design RTL 12 Calypto Design Systems Catapult 8.0 : Native Dual -language Support • User choice of C++ or SystemC – Catapult has dual-language architecture – Projects may use either based on requirements • C/C++ provides intuitive algorithm implementation flow – Fewer lines of code – Untimed description – Streamlined flow • Robust SystemC support – Support OSCI synthesis subset – Calypto leads Accelera working group – Used for designs with complex timing dependent control and interface protocols 13 Calypto Design Systems Synthesizing to Hardware • Flow is the same for FPGA & ASIC technologies – Same C++/SystemC source code for synthesis irrespective of target technology – Technology libraries for FPGA base operators are provided in the Catapult installation – Additional libraries for hard macros/DSPs & memories – Catapult Library Builder provided to characterize ASIC libraries 14 Calypto Design Systems Supported FPGA Families (Catapult 8.0) • Altera • Xilinx – Arria GX, II GX, V – Artix-7 – Cyclone, II, III, III LS, IV E, IV – Kintex-7 GX, V – Spartan 2, 2E, 3, 3A, – Stratix, GX, II, II GX, III, IV, V 3ADSP, 3E, 6 – Excalibur ARM – Virtex, -E, -II, -II Pro, 4, 5, 6, 7 – Apex 20K, 20KC, 20KE, II • New libraries added to meet Customer requests 15 Calypto Design Systems User Constrained Technology Based Scheduling • User provides constraints to scheduler in GUI or as TCL script • Scheduler uses technology information to allocate operations to clock cycles – Source is independent of target technology timing characteristics – Same source code gives different schedule based on constraints / technology • Scheduler facilitates technology migration by re-scheduling to different target library – Migrate FPGA fabric or family – Migration to SOC FPGA: Xilinx Kintex7 ASIC: @ 200MHz Sample 65nm @ 200MHz 16 Calypto Design Systems RTL Extraction/Generation • RTL Generation creates : – Data & control path/state machine RTL – Bill of materials reports – Estimation of area & timing critical paths – Scripts for running backend synthesis/P&R – SCVerify testbench & execution scripts 17 © 2014, Calypto Design Systems Catapult 8 : Verification 18 Calypto Design Systems Catapult 8 Speeds Verification Closure • Catapult 8 re-architected for Verification Closure – Developed in partnership with leading Catapult customers – Engineered for a “drop-in” fit into existing verification flows – Considers verification coverage during synthesis – Extracts and passes design knowledge to verification tools and users • New capabilities to assist in closing verification – Synthesizes assertions and cover points – Identifies and guarantees key equivalent points – Easily cross-probe between RTL and C++/SystemC – Integration with formal tools to identify unreachable states 19 Calypto Design Systems RTL Block Level Testing with SCVerify • Catapult provides SCVerify, Original automated C-RTL co-simulation Testbench • Generated RTL Optimized for verification Driver – Embedded Assertions – Preserved probe points • Generated Test Infrastructure Original Generated RTL C++/SystemC – Leverages original C++/SystemC testbench – Verification of generated RTL vs original Monitor source – Checks assertions, probes and IO Golden DUT • Push-button Co-Simulation results Comparator results – Supports VCS, Incisive, Questa • 2020Easy testing of RTL before handoffCalypto Design Systems SLEC -HLS – High Level Formal Verification • C-to-RTL formal verification void func (short a[N], for (int i=0; i<N; i++) { if (cond) z+=a[i]*b[i]; • Sequential Logic Equivalence else Checker – Handles timing differences in internal computation and at interfaces SLEC equivalence proof or • Total verification confidence counter example – Identifies design inconsistencies – No need for lengthy simulation runs – Unlocks the full potential of HLS RTL 21 Calypto Design Systems Catapult 8 : Implementation 22 Calypto Design Systems Output Generated by FPGA Flow • HDL outputs – VHDL and/or Verilog – Synthesizable RTL – “concat” RTL containing whole design in a single file • Synthesis scripts for backend RTL synthesis – Precision, SynplifyPro, Xilinx XST – Easy synthesis of generated RTL • Customer free to integrate RTL into upper levels of system as needed – Manual integration 23 Calypto Design Systems Migration • Catapult allows source code to be re-targeted to alternative technology – Scheduler is aware of target technology characteristics • Many design teams using : – FPGA targets for prototyping, then ASIC for production – FPGA for early access to algorithms in hardware, ASIC implementation lags due to lead time – IP blocks are independent of implementation target • Production quantities may necessitate migration from FPGA to ASIC – How to reduce power once in ASIC? 24 Catapult LP Synthesizes Power Optimized RTL • Available to support ASIC/SOC migration • PowerPro technology “under the hood” High-Level Synthesis – Leading RTL Power Optimization Technology Power Optimization Simulation • Built-in power analysis/measurement Power Analysis • Closed loop PPA exploration – PPA: Power, performance, area – Frequency exploration – Clock-gating – Memory access minimization Use Mode Power • Use Mode Power Automatic clock gating Active 1.0 mw – Deep sequential
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