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Catapult C Synthesis Work Flow Tutorial Catapult C Synthesis Work Flow Tutorial ELEC 522 Advanced VLSI Design, Rice University Version 1.3 10/14/2010, Guohui Wang Introduction In this tutorial, you will go through the complete work flow of Catapult C Synthesis, including bit accurate C program simulation, HDL generation, ModelSim/ISE Simulator simulation/verification, and integration with System Generator. You will build a simple sum of square computation block using Catapult C tool. Objectives After this tutorial lab, you will be able to: Write C/C++ code in Catapult C. Compile and simulate the C/C++ code using GCC; Use Catapult C to generate HDL code; Simulate/Verify the generated HDL model in ModelSim/ISE built-in Simulator; Integrate the HDL model into System Generator design by using the Black-box block. Then simulate a complete system in System Generator. Design Description Use Catapult C Synthesis to implement a “sum of square” computation: Computation equation: c = a*a + b*b; Data type: a and b are both 16bit fixed-point numbers; c is 34bit number. Tools Used in This Lab In this lab, we will use the following tools: Mentor Graphics Catapult C Synthesis 2009a.85 GCC 4.2.2 Xilinx ISE 10.1.3 ModelSim SE6.5c Xilinx System Generator 10.1 MATLAB 2008a ELEC 522 Catapult C Synthesis Work Flow Tutorial ECE Department, Rice University Page 1 Procedure This tutorial comprises 6 primary steps: 1. Create a new Catapult project. Write C++ code in Catapult C; 2. Simulate C++ code using GCC; 3. Generate Verilog HDL code in Catapult; 4. Simulate/Verify HDL model in ModelSim/ISE-simulator; 5. Synthesize your HDL model using Xilinx ISE; 6. Use black-box to integrate the HDL model into System Generator and simulate the complete system in System Generator. Please notice that the goal of this document is only to show the basic tool flow. Therefore, we do not optimize our design. In your project design, you might need to go back and forth for a couple of iterations between step 1 and step 4 to optimize your design. Besides, in this simple tutorial I have not considered the interface optimization. In your project, you need to consider the interface design, for example, pointer VS non-pointer interfaces. STEP 1: C Programming in Catapult C Synthesis Create a new folder. Start the Catapult tool on the Linux server. Then create a new project in Catapult. Click “Set Working Directory”, in the popup dialog select the folder you just created. In the menu, select File->New to create a new file. Type in the code below: Select File->Save as, to save this file as “example.h”. //Include Catapult bit accurate types #include "ac_int.h" int34 sumsquare(int16 a, int16 b); Data type uint34 has been defined in ac_int.h: typedef ac_int<34, true> uint34; Then create another new file, type in the following code, then save it as “example.cpp”. #include "example.h" #pragma hls_design top int34 sumsquare(int16 a, int16 b) { int34 c = 0; c = a * a + b* b; return c; } ELEC 522 Catapult C Synthesis Work Flow Tutorial ECE Department, Rice University Page 2 In the cpp file, the header file is included at the beginning. Then ‘hls_design top’ pragma is used to tell Catapult tool that this kernel function is the top level design for the HDL model. Finally, the function sumsquare( ) is defined. From the task bar, click “Setup Design”. If Catapult says “Passed Analyze”, it means there is no syntax error in your code. Otherwise, the tool shows you the error(s). This could help you quicckly debug the syntax error in your code. SStep 2: Simulate C++ Code Using GCC Then we need to use GCC to simulate your C++ code. Create a new file, type the following code, and savee it as “example_tb.cpp”. This is our testbench in C++ language. Basically, in this testbench, we generate some test values, and then print the calculation results on the terminal. #include <stdio.h> #include "example.h" int main() { int16 aa = 0; int16 bb = 0; int34 cc = 0; for ( int i = 0; i < 10; i++ ) { aa = i; bb = i+1; cc = sumsquare(aa, bb); printf ( "#%d: %d^2 + %d^2 = %d\r\n", i, aa.to_int(), bb.to_int(),// cc.to_int64()); } return 0; } o In this file, ‘//’ is used when you need to break one statements into two lines, and it tells the compiler that the statement is not finished and will continue in the next line. ELEC 522 Catapult C Synthesis Work Flow Tutorial ECE Departmentt, Rice University Page 3 o Since aa, bb, cc are all Algorithmic C datatypes, they are not supported by standard printf( ) function. In order to print the values of aa and bb, you need to use a member method to_int( ) of the Class int16 to convert int16 datatype to the C++ int datatype, so that we could print the value through printf( ) function. Because cc is a 34bit number, if you convert it to the C++ int type, you will lose 2bits’ information. Therefore, you should use the member method to_int64( ) to convert int34 into C++ long long int datatype. (Please refer to the Chapter 2 in the document “Algorithmic C Datatypes”) In order to compile the code using GCC, we need a Makefile. We could modify the Makefile from tutorial lab2. Finally, your Makefile will look like this: # Makefile for example_tb.cpp CPP = /usr/bin/g++ INCLUDE = -I ${MGC_HOME}/shared/include TARGET = example OBJECTS = example.o example_tb.o ${TARGET}: ${OBJECTS} ${OBJECTS}: example.cpp example_tb.cpp example.h Makefile %.o : %.cpp ${CPP} -c ${INCLUDE} $< ${TARGET}: ${OBJECTS} ${CPP} ${OBJECTS} ${LINKARGS} -o $@ clean: rm -rf *.o ${TARGET} Notice that, ${MGC_HOME} is an environment variable that points to the install path of Mentor Graphics Catapult C Synthesis. This environment varialble has been set when you log in the Linux server. In the .tcshrc file under your home directory, you source several setup scripts, and one of them sets the MGC_HOME environment variable. At the Linux prompt, use “make” command to compile the testbench code. You will get an executable file named “example”. Run the executable file, you can see the printed results. ELEC 522 Catapult C Synthesis Work Flow Tutorial ECE Department, Rice University Page 4 It is clear that the simulation results are correct. So far, we have finished the C++ code simulation. SStep 3: Generate Verilog HDL Code in Catapult C Synthesis Configure your design for Xiilinx FPGA, Virtex-II Pro 2VP30ff896-7, set the frequency to 100MHz. Then click Apply button. ELEC 522 Catapult C Synthesis Work Flow Tutorial ECE Departmentt, Rice University Page 5 Sincce you have more than one cpp file, you need to set one as the HLS top level file. Select “Int sumsquare” function, and check the “Top Design” box. Then click Apply. Click “Architecture constraints” in the task bar on the left. Configure the architecture parameters. Then click “Schedule” to check the Gantt chart. In your project design, you need to check the timing schedule in the Gantt chart. Based on the schedule results, you might need to go back to “Architecture constraints” to change the architecture parameters to optimize your design. Here, we just simply change the Design goal from ‘area’ to ‘latency’. Then we pipeline the ‘sumsquare_main’ loop. From the menu, in Tools->Set options->Output->Output format, check the box for “Verilog”. Then click Apply & Save. ELEC 522 Catapult C Synthesis Work Flow Tutorial ECE Departmentt, Rice University Page 6 Finally, click “Generate RTL”. In the Output Files folder, you can check the reports for timing and resource usage. Verilog HDL RTL model is generated. You can also check the schematics for your design as well as the critical path. SStep 4: Simulate//Verify HDL Model in ModelSim/ISE-simulator In order to simulate/verify the Verilog HDL code generated by Catapult, you could write a Verilog HDL testbench. However, the ISE tool provides a graphic-based testbennch editor that could help you generate the testbench easily. In this step, you will use ISE to generate a testbench waveform. Then you can edit the waveform and use it to simulate the HDL model. Afteer that, you will generate a Verilog HDL testbench based on the testbench waveform. You will modiify the testbench file and use it to simulate our model. The reason why you still need a Verilog HDL testbench is that the text-baased testbench is much more flexible so that you could generate more complicated test vectors. Another reason is that by using a text-based testbench you could insert breakpoints in the testbench and debug the testbench just like debugging a C++ program in Visual C++. You are allowed to step over your testbench and check the value in each register. ELEC 522 Catapult C Synthesis Work Flow Tutorial ECE Departmentt, Rice University Page 7 Step (1): Step (2): Step (3): Step (4): Create a new Import RTL Create a Simulate ISE project file testbench using the waveform waveform Step (5): Step (6): Step (7): Generate Modify the Simulate using Verilog Verilog the Verilog Testbench Testbench Testbench In this step, you will learn to use Xilinx ISE, ISE simulator and ModelSim to simulate your HDL model. ISE simulator (ISim) is a simulation tools which is buuilt in the Xilinx ISE tool. It has a waveform editor that allows you to generate a simulation testbench quiickly in an interactive way. The HDL simulation can be an even more fundamental step within your design flow with the tight integration of the ISE Simulator within your design environment. For more details, please check http://www.xilinx.com/tools/isim.htm.
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