HDL and Programming Languages ■ 6 Languages ■ 6.1 Analogue Circuit Design ■ 6.2 Digital Circuit Design ■ 6.3 Printed Circuit Board Design ■ 7 See Also
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From Signal Temporal Logic to FPGA Monitors
From Signal Temporal Logic to FPGA Monitors Stefan Jaksiˇ c´∗, Ezio Bartocci†, Radu Grosu†, Reinhard Kloibhofer∗, Thang Nguyen‡ and Dejan Nickoviˇ c´∗ ∗AIT Austrian Institute of Technology, Austria †Faculty of Informatics, Vienna University of Technology, Austria ‡Infineon Technologies AG, Austria Abstract— allows very long tests that are not possible with simulation- based methods. Design emulation is used both to explore Due to the heterogeneity and complexity of systems-of- systems (SoS), their simulation is becoming very time consuming, the behavior of digital and analog components. In the latter expensive and hence impractical. As a result, design simulation is case, the (possibly mixed signal) component is approximated increasingly being complemented with more efficient design em- with its discretized behavioral model. By combining these two ulation. Runtime monitoring of emulated designs would provide approaches, we provide a rigorous method for runtime verifi- a precious support in the verification activities of such complex cation of long executions resulting from mixed signal design systems. emulations. In addition to design emulations, our proposed We propose novel algorithms for translating signal temporal solution can be used to monitor real mixed-signal devices in logic (STL) assertions to hardware runtime monitors imple- post-silicon validation in real-time. mented in field programmable gate array (FPGA). In order to We choose Signal Temporal Logic (STL) [13] as our accommodate to this hardware specific setting, we restrict our- selves to past and bounded future temporal operators interpreted specification language. STL allows describing complex timing over discrete time. We evaluate our approach on two examples: relations between digital and analog “events”, where the latter the mixed signal bounded stabilization property; and the serial are specified via numerical predicates. -
MACABEL ABEL for the APPLE MACINTOSH Nor IIX WORKSTATION A/UX VERSION
SPECIFICATIONS MACABEL ABEL FOR THE APPLE MACINTOSH nOR IIX WORKSTATION A/UX VERSION GENERAL DESCRIPTION ABEL.'" the industry standard PLD design software, is now available on the Apple Macintosh® II or IIx workstation. MacABEL allows you to take advantage of the personal productivity features of the Macintosh to easily describe and implement logic designs in programmable logic devices (PLDs) and PROMs. Like ABEL Version 3.0 for other popular workstations, MacABEL combines a natural high-level design language with a language processor that converts logic descriptions to programmer load files. These files contain the required information to program and test PLDs. MacABEL allows you to describe your design in any combi nation of Boolean equations, truth tables or state diagrams whichever best suits the logic you are describing or your comfort level. Meaningful names can be assigned to signals; signals grouped into sets; and macros used to simplify logic descriptions - making your logic design easy to read and • Boolean equations understand. • State machine diagram entry, using IF-THEN-ELSE, CASE, In addition, the software's language processor provides GOTQ and WITH-ENDWITH statements powerful logic reduction, extensive syntax and logic error • Truth tables to specify input to output relationships for both checking - before your device is programmed. MacABEL combinatorial and registered outputs supports the most powerful and innovative complex PLDs just • High-level equation entry, incorporating the boolean introduced on the market, as well as many still in development. operators used in most logic designs < 1 1 & 1 # 1 $ 1 1 $ ) , MacABEL runs under the Apple A/UX'" operating system arithmetic operators <- I + I * I I I %I < < I > > ) , relational utilizing the Macintosh user interface. -
An Introduction to High-Level Synthesis
High-Level Synthesis An Introduction to High-Level Synthesis Philippe Coussy Michael Meredith Universite´ de Bretagne-Sud, Lab-STICC Forte Design Systems Daniel D. Gajski Andres Takach University of California, Irvine Mentor Graphics today would even think of program- Editor’s note: ming a complex software application High-level synthesis raises the design abstraction level and allows rapid gener- solely by using an assembly language. ation of optimized RTL hardware for performance, area, and power require- In the hardware domain, specification ments. This article gives an overview of state-of-the-art HLS techniques and languages and design methodologies tools. 1,2 ÀÀTim Cheng, Editor in Chief have evolved similarly. For this reason, until the late 1960s, ICs were designed, optimized, and laid out by hand. Simula- THE GROWING CAPABILITIES of silicon technology tion at the gate level appeared in the early 1970s, and and the increasing complexity of applications in re- cycle-based simulation became available by 1979. Tech- cent decades have forced design methodologies niques introduced during the 1980s included place-and- and tools to move to higher abstraction levels. Raising route, schematic circuit capture, formal verification, the abstraction levels and accelerating automation of and static timing analysis. Hardware description lan- both the synthesis and the verification processes have guages (HDLs), such as Verilog (1986) and VHDL for this reason always been key factors in the evolu- (1987), have enabled wide adoption of simulation tion of the design process, which in turn has allowed tools. These HDLs have also served as inputs to logic designers to explore the design space efficiently and synthesis tools leading to the definition of their synthe- rapidly. -
An Implementation of Lola-2 Or Translating from Lola to Verilog
An Implementation of Lola-2 or Translating from Lola to Verilog N.Wirth, 30.11.2014 1. Introduction The hardware description language Lola (Logic Language) was designed in 1990 as an effort to present a simple and effective textual description of digital circuits. At that time, the conventional style was still graphical (circuit charts), and it was not evident that textual descriptions would replace them entirely within 20 years. Also, there were no means available to automatically transfer them into physical circuits of electronic components. However, field-programmable gate arrays (FPGA) appeared, and although they were far too restrictive (small) for most practical purposes, they seemed to be a promising gateway towards introducing textual specifications with the hope of future automatic generation of real circuits. That this hope was well-founded is now evident. The difficult part of implementation in 1990 was not the compilation of the textual descriptions into net lists of gates and wires. It was rather the placement of components and routing of wires. And this still remains so. But even if this task is achieved, the compiled output is to be down-loaded into the FPGA. For this purpose, the format of the data, the bit-stream format, must be known. Whereas at the time we obtained this information from two FPGA manufacturers, it is now strictly proprietary in the case of the dominating manufacturers, a severe case of interface secrecy. In the course of reviving activities of 25 years ago around Oberon, also the hardware description language (HDL) Lola reappeared. Now textual descriptions of hardware are common place, the preferred languages being Verilog and VHDL. -
A Language for Parametrised and Reconfigurable Hardware Design
Pebble: A Language For Parametrised and Reconfigurable Hardware Design Wayne Luk and Steve McKeever Department of Computing, Imperial College, 180 Queen’s Gate, London SW7 2BZ, UK Abstract. Pebble is a simple language designed to improve the pro- ductivity and effectiveness of hardware design. It improves productivity by adopting reusable word-level and bit-level descriptions which can be customised by different parameter values, such as design size and the number of pipeline stages. Such descriptions can be compiled without flattening into various VHDL dialects. Pebble improves design effectiven- ess by supporting optional constraint descriptions, such as placement attributes, at various levels of abstraction; it also supports run-time re- configurable design. We introduce Pebble and the associated tools, and illustrate their application to VHDL library development and reconfigu- rable designs for Field Programmable Gate Arrays (FPGAs). 1 Introduction Many hardware designers recognise that their productivity can be enhanced by reusable designs in the form of library elements, macros, modules or intellectual property cores. These components are developed carefully to ensure that they are efficient, validated and easy to use. Several development systems based on Java [1], Lola [2], C [3], ML [5], VHDL and Ruby [7] have been proposed. While the languages in these systems have their own goals and merits, none seems to meet all our requirements of: 1. having a simple syntax and semantics; 2. allowing a wide range of parameters in design descriptions; 3. providing support for both word-level design and bit-level design; 4. supporting optional constraint descriptions, such as placement attributes, at various levels of abstraction; 5. -
A Classification and Comparison Framework for Software Architecture Description Languages
A Classification and Comparison Framework for Software Architecture Description Languages Neno Medvidovic Technical Report UCI-ICS-97-02 Department of Information and Computer Science University of California, Irvine Irvine, California 92697-3425 [email protected] February 1996 Abstract Software architectures shift the focus of developers from lines-of-code to coarser- grained architectural elements and their overall interconnection structure. Architecture description languages (ADLs) have been proposed as modeling notations to support architecture-based development. There is, however, little consensus in the research community on what is an ADL, what aspects of an architecture should be modeled in an ADL, and which of several possible ADLs is best suited for a particular problem. Furthermore, the distinction is rarely made between ADLs on one hand and formal specification, module interconnection, simulation, and programming languages on the other. This paper attempts to provide an answer to these questions. It motivates and presents a definition and a classification framework for ADLs. The utility of the definition is demonstrated by using it to differentiate ADLs from other modeling notations. The framework is also used to classify and compare several existing ADLs. One conclusion is that, although much research has been done in this area, no single ADL fulfills all of the identified needs. I. Introduction Software architecture research is directed at reducing costs of developing applications and increasing the potential for commonality between different members of a closely related product family [GS93, PW92]. Software development based on common architectural idioms has its focus shifted from lines-of-code to coarser-grained architectural elements (software components and connectors) and their overall interconnection structure. -
Mexican Sentimiento and Gender Politics A
UNIVERSITY OF CALIFORNIA Los Angeles Corporealities of Feeling: Mexican Sentimiento and Gender Politics A dissertation submitted in partial satisfaction of the requirements for the degree Doctor of Philosophy in Culture and Performance by Lorena Alvarado 2012 © Copyright by Lorena Alvarado 2012 ABSTRACT OF THE DISSERTATION Corporealities of Feeling: Mexican Sentimiento and Gender Politics by Lorena Alvarado Doctor of Philosophy in Culture and Performance University of California, Los Angeles, 2011 Professor Alicia Arrizón, co-chair Professor Susan Leigh Foster, co-chair This dissertation examines the cultural and political significance of sentimiento, the emotionally charged delivery of song in ranchera genre musical performance. Briefly stated, sentimiento entails a singer’s fervent portrayal of emotions, including heartache, yearning, and hope, a skillfully achieved depiction that incites extraordinary communication between artist and audience. Adopting a feminist perspective, my work is attentive to the elements of nationalism, gender and sexuality connected to the performance of sentimiento, especially considering the genre’s historic association with patriotism and hypermasculinity. I trace the logic that associates representations of feeling with nation-based pathology and feminine emotional excess and deposits this stigmatized surplus of affect onto the singing body, particularly that of the mexicana female singing body. In this context, sentimiento is represented in film, promotional material, and other mediating devices as a bodily inscription of personal and gendered tragedy, ii as the manifestation of exotic suffering, or as an ancestral and racial condition of melancholy. I examine the work of three ranchera performers that corroborate these claims: Lucha Reyes (1906-1944), Chavela Vargas (1919) and Lila Downs (1964). -
Automatic Generation of Hardware for Custom Instructions
Automatic Generation of Hardware for Custom Instructions by Philip Ioan Necsulescu Thesis submitted to the Faculty of Graduate and Postdoctoral Studies in partial fulfillment of the requirements for the degree of Master of Science in Systems Science Interdisciplinary studies Faculty of Graduate and Postdoctoral Studies © Philip Ioan Necsulescu, Ottawa, Canada, 2011 Table of Contents List of Figures ................................................................................................................................................ 3 Acknowledgements ....................................................................................................................................... 4 Abstract ......................................................................................................................................................... 5 Glossary ......................................................................................................................................................... 6 1 - Introduction ............................................................................................................................................. 8 2 - Background (Literature Review) ............................................................................................................ 12 2.1 – Applications of Custom Instructions .............................................................................................. 12 2.2 – Comparison of Automated HDL Generation Porjects ................................................................... -
An Architectural Description Language for Secure Multi-Agent Systems
An Architectural Description Language for Secure Multi-Agent Systems Haralambos Mouratidis1,a, Manuel Kolpb, Paolo Giorginic, Stephane Faulknerd aInnovative Informatics Group, School of Computing, IT and Engineering, University of East London, England b Information Systems Research Unit, Catholic University of Louvain (UCL), Belgium c Department. of Information and Communication Technology, University of Trento, Italy d Information Management Research Unit, University of Namur, Belgium Abstract. Multi-Agent Systems (MAS) architectures are gaining popularity for building open, distributed, and evolving information systems. Unfortunately, despite considerable work in the fields of software architecture and MAS during the last decade, few research efforts have aimed at defining languages for designing and formalising secure agent architectures. This paper proposes a novel Architectural Description Language (ADL) for describing Belief-Desire-Intention (BDI) secure MAS. We specify each element of our ADL using the Z specification language and we employ two example case studies: one to assist us in the description of the proposed language and help readers of the article to better understand the fundamentals of the language; and one to demonstrate its applicability. Keyword: Architectural Description Language, Multi-Agent Systems, Security, BDI Agent Model, Software Architecture 1 Corresponding Author: [email protected] 1 1. Introduction However, as the expectations of business stakeholders are changing day after day; and The characteristics and expectations of as the complexity of systems, information new application areas for the enterprise, and communication technologies and such as e-business, knowledge management, organisations is continually increasing in peer-to-peer computing, and web services, today’s dynamic environments; developers are deeply modifying information systems are expected to produce architectures that engineering. -
Review of FPD's Languages, Compilers, Interpreters and Tools
ISSN 2394-7314 International Journal of Novel Research in Computer Science and Software Engineering Vol. 3, Issue 1, pp: (140-158), Month: January-April 2016, Available at: www.noveltyjournals.com Review of FPD'S Languages, Compilers, Interpreters and Tools 1Amr Rashed, 2Bedir Yousif, 3Ahmed Shaban Samra 1Higher studies Deanship, Taif university, Taif, Saudi Arabia 2Communication and Electronics Department, Faculty of engineering, Kafrelsheikh University, Egypt 3Communication and Electronics Department, Faculty of engineering, Mansoura University, Egypt Abstract: FPGAs have achieved quick acceptance, spread and growth over the past years because they can be applied to a variety of applications. Some of these applications includes: random logic, bioinformatics, video and image processing, device controllers, communication encoding, modulation, and filtering, limited size systems with RAM blocks, and many more. For example, for video and image processing application it is very difficult and time consuming to use traditional HDL languages, so it’s obligatory to search for other efficient, synthesis tools to implement your design. The question is what is the best comparable language or tool to implement desired application. Also this research is very helpful for language developers to know strength points, weakness points, ease of use and efficiency of each tool or language. This research faced many challenges one of them is that there is no complete reference of all FPGA languages and tools, also available references and guides are few and almost not good. Searching for a simple example to learn some of these tools or languages would be a time consuming. This paper represents a review study or guide of almost all PLD's languages, interpreters and tools that can be used for programming, simulating and synthesizing PLD's for analog, digital & mixed signals and systems supported with simple examples. -
Xcell Journal Issue 50, Fall 2004
ISSUE 50, FALL 2004ISSUE 50, FALL XCELL JOURNAL XILINX, INC. Issue 50 Fall 2004 XcellXcelljournaljournal THETHE AUTHORITATIVEAUTHORITATIVE JOURNALJOURNAL FORFOR PROGRAMMABLEPROGRAMMABLE LOGICLOGIC USERSUSERS MEMORYMEMORY DESIGNDESIGN Streaming Data at 10 Gbps Control Your QDR Designs PARTNERSHIP 20 Years of Partnership Author! Author! Programmable WorldWorld 20042004 SOFTWARE Algorithmic C Synthesis The Need for Speed MANUFACTURING Lower PCB Mfg. Costs Optimize PCB Routability R COVER STORY FPGAs on Mars The New SPARTAN™-3 Make It You r ASIC The world’s lowest-cost FPGAs Spartan-3 Platform FPGAs deliver everything you need at the price you want. Leading the way in 90nm process technology, the new Spartan-3 devices are driving down costs in a huge range of high-capability, cost-sensitive applications. With the industry’s widest density range in its class — 50K to 5 Million gates — the Spartan-3 family gives you unbeatable value and flexibility. Lots of features … without compromising on price Check it out. You get 18x18 embedded multipliers for XtremeDSP™ processing in a low-cost FPGA. Our unique staggered pad technology delivers a ton of I/Os for total connectivity solutions. Plus our XCITE technology improves signal integrity, while eliminating hundreds of resistors to simplify board layout and reduce your bill of materials. With the lowest cost per I/O and lowest cost per logic cell, Spartan-3 Platform FPGAs are the perfect fit for any design … and any budget. MAKE IT YOUR ASIC The Programmable Logic CompanySM For more information visit www.xilinx.com/spartan3 Pb-free devices available now ©2004 Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124. -
Dissertation Applications of Field Programmable Gate
DISSERTATION APPLICATIONS OF FIELD PROGRAMMABLE GATE ARRAYS FOR ENGINE CONTROL Submitted by Matthew Viele Department of Mechanical Engineering In partial fulfillment of the requirements For the Degree of Doctor of Philosophy Colorado State University Fort Collins, Colorado Summer 2012 Doctoral Committee: Advisor: Bryan D. Willson Anthony J. Marchese Robert N. Meroney Wade O. Troxell ABSTRACT APPLICATIONS OF FIELD PROGRAMMABLE GATE ARRAYS FOR ENGINE CONTROL Automotive engine control is becoming increasingly complex due to the drivers of emissions, fuel economy, and fault detection. Research in to new engine concepts is often limited by the ability to control combustion. Traditional engine-targeted micro controllers have proven difficult for the typical engine researchers to use and inflexible for advanced concept engines. With the advent of Field Programmable Gate Array (FPGA) based engine control system, many of these impediments to research have been lowered. This dissertation will talk about three stages of FPGA engine controller appli- cation. The most basic and widely distributed is the FPGA as an I/O coprocessor, tracking engine position and performing other timing critical low-level tasks. A later application of FPGAs is the use of microsecond loop rates to introduce feedback con- trol on the crank angle degree level. Lastly, the development of custom real-time computing machines to tackle complex engine control problems is presented. This document is a collection of papers and patents that pertain to the use of FPGAs for the above tasks. Each task is prefixed with a prologue section to give the history of the topic and context of the paper in the larger scope of FPGA based engine control.