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A Language for Parametrised and Reconfigurable Hardware Design

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A Language for Parametrised and Reconfigurable Hardware Design Pebble: A Language For Parametrised and Reconfigurable Hardware Design Wayne Luk and Steve McKeever Department of Computing, Imperial College, 180 Queen’s Gate, London SW7 2BZ, UK Abstract. Pebble is a simple language designed to improve the pro- ductivity and effectiveness of hardware design. It improves productivity by adopting reusable word-level and bit-level descriptions which can be customised by different parameter values, such as design size and the number of pipeline stages. Such descriptions can be compiled without flattening into various VHDL dialects. Pebble improves design effectiven- ess by supporting optional constraint descriptions, such as placement attributes, at various levels of abstraction; it also supports run-time re- configurable design. We introduce Pebble and the associated tools, and illustrate their application to VHDL library development and reconfigu- rable designs for Field Programmable Gate Arrays (FPGAs). 1 Introduction Many hardware designers recognise that their productivity can be enhanced by reusable designs in the form of library elements, macros, modules or intellectual property cores. These components are developed carefully to ensure that they are efficient, validated and easy to use. Several development systems based on Java [1], Lola [2], C [3], ML [5], VHDL and Ruby [7] have been proposed. While the languages in these systems have their own goals and merits, none seems to meet all our requirements of: 1. having a simple syntax and semantics; 2. allowing a wide range of parameters in design descriptions; 3. providing support for both word-level design and bit-level design; 4. supporting optional constraint descriptions, such as placement attributes, at various levels of abstraction; 5. including facilities for developing designs reconfigurable at run time. From our previous work [7] and others, it is also important for design tools to: 6. produce reusable hardware libraries in industrial-standard languages; 7. facilitate multiple means of validation, from formal verification to executing on a hardware platform; 8. enable automatic generation of documentations. The purpose of this paper is to introduce a language, called Pebble, which is designed to meet the above requirements. Section 2 provides an overview of Peb- ble, showing how it meets requirements 1–3. Section 3 outlines the development R.W. Hartenstein, A. Keevallik (Eds.): FPL’98, LNCS 1482, pp. 9–18, 1998. c Springer-Verlag Berlin Heidelberg 1998 10 W. Luk and S. McKeever tools for Pebble on which the design flow is based, showing how requirements 6–8 can be satisfied. Section 4 deals with requirement 4: it describes how placement constraints can be captured and how descriptions such as ABOVE and BESIDE provide a useful abstraction. Section 5 presents an approach for developing re- configurable designs in Pebble, covering requirement 5. User experience with Pebble is reported in Section 6, while concluding remarks are given in Section 7. 2 Language Overview Pebble is an alias for Parametrised Block Language. The two primary objectives for Pebble are to facilitate the development of efficient and reusable designs, and to support the development of designs involving run-time reconfiguration. Much of our previous work is based on VHDL, which has been used for both library development [7] and simulation of reconfigurable components [11]. The complexity of VHDL and the associated tools, however, has led us to believe that a simpler approach will provide a better foundation on which to build abstractions and tools. A simple language would be both easy to learn and to use. More importantly, it would form a core language satisfying our immediate requirements while amenable to extensions. Moreover, since most VHDL vendors have their own dialect of VHDL, it would be easier to generate vendor-specific VHDL from a single standard library database than to maintain different library databases, one for each VHDL dialect. In any case, the complexity of existing industrial languages such as Verilog or VHDL makes them difficult to include experimental features, such as language support for run-time reconfiguration. Pebble can be regarded as a much simplified variant of structural VHDL. It provides a means of representing block diagrams hierarchically and parametri- cally. The basic features of Pebble are outlined below [10]. • A Pebble program is a block, defined by its name, parameters, interfaces, local definitions, and its body. • The block interfaces are given by two lists, usually interpreted as the inputs and outputs. An input or an output can be of type WIRE, or it can be a multi- dimensional vector of wires. A wire can carry integer or boolean values. • A primitive block has an empty body; a composite block has a body contai- ning the instantiation of composite or primitive blocks in any order. Blocks connected to each other share the same wire in the interface instantiation. • For hardware designs, the primitive blocks can be bit-level logic gates and registers, or they can, like an adder, process word-level data such as integers or fixed-point numbers; the primitives depend on the availability of corre- sponding components in the domain targeted by the Pebble compiler. • The GENERATE-IF statement enables conditional compilation, while the GENERATE-FOR statement allows the concise description of regular cir- cuits. Pebble has a simple, block-structured syntax. As examples, Fig. 1 contains a Pebble description of a multiplexor which is a primitive component for Xilinx Pebble: A Language For Parametrised and Reconfigurable Hardware Design 11 BLOCK mux [c,x,y:WIRE] [z:WIRE] BEGIN END; Fig. 1. A multiplexor description in Pebble, with control input c, data inputs x and y and output z. The empty body indicates that it is a primitive block. x0 x1 x2 x3 c mux mux mux mux z0 y0 z1 y1 z2 y2 z3 y3 Fig. 2. An array of multiplexors described by the Pebble program in Fig. 3. 6200 FPGAs, while Fig. 3 describes the multiplexor array in Fig. 2, provided that the size parameter n is 4. In more complex descriptions, the parameters in a Pebble program can in- clude the number of pipeline stages or the pitch between neighbouring interface connections [7]. Different network structures, such as tree- or butterfly-shaped circuits, can be described parametrically by indexing the components and wires. Pebble supports the use of annotations and constraint descriptions. Annota- tions contain optional information that does not affect the functional behaviour of Pebble programs. The use of annotations for guiding the Pebble compiler and for automatic documentation generation will be described in Section 3. The use of constraint descriptions to provide, for instance, abstract and concrete place- ment information will be presented in Section 4. The semantics of Pebble depends on the behaviour of the primitive blocks and their composition in the target technology. Currently a synchronous circuit BLOCK muxarray (n:GENERIC) [c:WIRE, x,y:VECTOR (n-1..0) OF WIRE] [z:VECTOR (n-1..0) OF WIRE] VAR i BEGIN GENERATE FOR i = 0..(n-1) DO mux [c,x(i),y(i)] [z(i)] END; Fig. 3. A description of an array of multiplexors (Fig. 2) in Pebble. The external input c is used to provide a common control input for each mutiplexor. 12 W. Luk and S. McKeever model is used in our tools (Section 3), and special control components for mo- delling run-time reconfiguration are also supported (Section 5). However, other models can be used if desired. Indeed Pebble can be used in modelling any block-structured systems, not just electronic circuits. Advanced features of Pebble include support for modules which improves reusability and facilitates interface to components in other languages, including behavioural descriptions. Discussions about these features are beyond the scope of this paper. 3 Development Tools and Design Flow We have developed a compiler for Pebble which can produce either a flattened netlist for simulation, or a parametrised description in structural VHDL. Pebble programs can be compiled into the netlist format for the Rebecca simulator, which can be used for cycle-accurate numerical or symbolic simulation at word- level, bit-level, or a mixture [7]. Automatic mapping between word-level and bit-level blocks is under development. Pebble descriptions can also be translated into formats suitable for verification systems such as HOL [4]. Pebble programs can be compiled into parametrised VHDL while preserving their hierarchy and parametrisation. The resulting VHDL code may contain compiler-generated names, but they can be replaced by user-specified names annotated in the Pebble source code. Section 6 includes more details about the parametrised VHDL libraries generated from Pebble; users of these VHDL libraries do not need to know Pebble. Functional and Place and route, performance bitstream generation measurements (XACTstep Series 6000) (PCI board) Simulation, Testbench transformation validation (Pebble) (Synopsys) FPGA FPGA Config. Netlist bitstream Pebble Synopsys or Program Velab VHDL Postscript or HTML Document Fig. 4. Design flow for our Pebble-based system. Synopsys and Velab are VHDL tools, and XACTstep Series 6000 is the implementation tool for Xilinx 6200 FPGAs. Fig. 4 shows the major elements in our design flow. Synopsys is a well-known industrial system which deals with VHDL synthesis; Velab and XACTstep Series Pebble: A Language For Parametrised and Reconfigurable Hardware Design 13 6000 are implementation tools for Xilinx 6200 FPGAs; and a PCI-based platform [9] for evaluating designs. We have also developed a Library Documentation Tool (LDT), which automatically produces library documentation in various formats such as Postscript and HTML [7]. The documentation is generated from information annotated in a specific format in the Pebble source; this method reduces the number of files to be maintained. 4 Constraint Description and Abstraction It is often useful to have the ability to include information about layout or timing in a hardware description. Such information provides a means of guiding design tools to produce an optimised design, or to generate improved estimates of design properties such as critical path delay or reconfiguration time.
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