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MACHXL Software User's Guide MACHXL Software User's Guide © 1993 Advanced Micro Devices, Inc. TEL: 408-732-2400 P.O. Box 3453 TWX: 910339-9280 Sunnyvale, CA 94088 TELEX: 34-6306 TOLL FREE: 800-538-8450 APPLICATIONS HOTLINE: 800-222-9323 (US) 44-(0)-256-811101 (UK) 0590-8621 (France) 0130-813875 (Germany) 1678-77224 (Italy) Advanced Micro Devices reserves the right to make changes in specifications at any time and without notice. The information furnished by Advanced Micro Devices is believed to be accurate and reliable. However, no responsibility is assumed by Advanced Micro Devices for its use, nor for any infringements of patents or other rights of third parties resulting from its use. No license is granted under any patents or patent rights of Advanced Micro Devices. Epson® is a registered trademark of Epson America, Inc. Hewlett-Packard®, HP®, and LaserJet® are registered trademarks of Hewlett-Packard Company. IBM® is a registered trademark and IBM PCä is a trademark of International Business Machines Corporation. Microsoft® and MS-DOS® are registered trademarks of Microsoft Corporation. PAL® and PALASM® are registered trademarks and MACHä and MACHXL ä are trademarks of Advanced Micro Devices, Inc. Pentiumä is a trademark of Intel Corporation. Wordstar® is a registered trademark of MicroPro International Corporation. Document revision 1.2 Published October, 1994. Printed inU.S.A. ii Contents Chapter 1. Installation Hardware Requirements 2 Software Requirements 3 Installation Procedure 4 Updating System Files 6 AUTOEXEC.BAT 7 CONFIG.SYS 7 Creating a Windows Icon for MACHXL 8 Chapter 2. Processing a Design Design Flow 12 Program Module Descriptions 13 Structure of a MACHXL Design File 15 Creating a New Design 16 Using the New Design Form 16 Creating a New Design with the Text Editor 20 Opening an Existing Design 20 Using the Text Editor 21 Compiling the Design 24 Viewing Compilation Results 25 Back-Annotating the Design File 25 Simulating the Design 26 Downloading the JEDEC File 28 Standard PLD Programmer 28 JTAG Programming Cable 28 Disassembling a Compiled Design 28 Processing a Simple Design 30 Creating the Declaration Segment 31 Writing the Equations 39 Writing the Simulation Statements 40 Compiling the Design 41 Getting a Problem Design to Fit 43 Chapter 3. Design Examples Multiplexer 50 Comparator 51 Left/Right Shifter 52 Barrel Shifter 53 Simple 3-Bit Counter 54 iii Decoder 56 Up-Down Counter and Up-Counter with Parallel Load 57 Data Acquisition System 58 Moore State Machine 60 Chapter 4. Menu Reference Overview 65 Screen Layout 65 Choosing Menu Commands 66 Preserving Menu Settings 69 File Menu 70 Begin New Design 70 Retrieve Existing Design 71 Change Directory 72 Set Up 73 Working Environment 73 Compilation Options 75 Compilation Options Form 76 MACH Fitting Options Form 77 Simulation Options 87 Logic Synthesis Options 89 Go To System 95 Quit 96 Edit Menu 97 Text File 97 Auxiliary Simulation File 97 Other File 98 Run Menu 98 Compilation 99 Compilation Options 100 Logic Synthesis Options 100 MACH Fitting Options 101 Run-Time Status Display 101 Output Files 102 Simulation 102 Both 103 Other Operations 103 Modify Pin & Node Numbers 104 iv Disassemble From 105 Intermediate File 105 Jedec 105 Recalculate JEDEC Checksum 107 View Menu 108 Execution Log File 108 Design File 109 Fitter Reports 109 Fitting 109 Place/Route Data 109 Timing Analysis 109 JEDEC Data 110 Simulation Data 110 All Signals 111 Trace Signals Only 111 Printing the Simulation History 112 Waveform Display 113 All Signals 113 Trace Signals Only 114 Printing a Waveform 114 Current Disassembled File 115 Other File 115 Download Menu 116 Download to Programmer 116 Program via Cable 117 View Configuration File 117 Create/Edit Configuration File 118 Chain File Editor Modes 120 Completing the JTAG File Editor Form 123 Program device 126 Review JTAG results 127 Review JTAG status 127 View/edit output file(s) 127 Chapter 5. Language Reference Symbols and Operators 129 Keywords 131 Chapter 6. Equations Segment In Depth Pairing 193 Implicit Pairing Rules and Behavior 193 v Output Pairing 195 Input Pairing 196 MACH 1xx Designs 196 MACH 2xx (Except MACH215) Designs 198 MACH 4xx and MACH215 Designs 199 Explicit Pairing Rules and Behavior 199 Copying Logic with Braces { } 200 Output Pairing 200 Input Pairing 203 Polarity 205 The Two Components of Polarity 205 Controlling Polarity from the Equation 205 Controlling Polarity from the Pin Statement 206 Controlling Polarity from CASE Statements 206 Functional Equations 209 Controlling Three-State Output Buffers 209 Controlling Clocks 210 Specifying a Rising-Edge Clock 211 Specifying a Falling-Edge Clock 211 Specifying a Product-Term Clock 212 Global Clock Acquisition 212 Controlling Set and Reset 214 Sharing Set and Reset 215 Vectors 216 Ranges of Pins or Nodes 216 Comma-Delimited Vectors 218 Radix Operators 219 IF-THEN-ELSE Statements 221 CASE Statements 222 Building State Machines with CASE Statements 224 Multiple State Machines 230 The "Don't-Care" Logic-Synthesis Option 237 MINIMIZE_ON and MINIMIZE_OFF 241 Chapter 7. Simulation Segment In Depth Overview 245 Creating a Simulation File 246 Simulation Command Summary 246 Simulation Segment vs. Auxiliary File 248 Considerations 249 Vectors In Simulation 250 vi SETF and PRELOAD 250 CHECK and CHECKQ 251 CLOCKF 252 TRACE_ON 252 Flip-Flops 252 Buried Nodes 253 Latches 253 Output Enable 253 Preloaded Registers 254 Verified Signal Values 254 Viewing Simulation Results 254 All Signals 255 Trace Signals Only 257 Text Display, Non-Vectored 258 Text Display, Vectored 259 Waveform Display, Non-Vectored 260 Waveform Display, Vectored 261 Using Simulation Constructs 261 For Loop 261 While Loop 262 If-Then-Else 262 Design Examples 263 Boolean Equation Design 263 State Machine Design 266 Notes On Using the Simulator 267 Modeling of Registers and Latches 268 Programmer Emulation at Power-Up 268 Power-Up Sequence 269 Software Preload Sequence 269 Full Evaluation of Input Pins 270 Clock Polarity 270 Driving Active-Low Clocks 271 Product Term-Driven Clocks 273 Simultaneous Events 274 Power-Up Preload On Floating Pins 274 Output Buffers 274 Input Signal Ordering 275 Preventing Unexpected Simulation Behavior 276 Placement Information Missing 276 Set/Reset Signals Swapped 276 Set/Reset Signals Treated As "Don't Care" 277 Uncontrollable Power-Up Conditions 277 vii Chapter 8. Using the Fitter Overview 281 The Fitting Process 281 Initialization 281 Normalization 282 Design Rule Check 282 Block Partitioning 282 Iterative versus Non-Iterative Partitioning 283 Manual Partitioning 284 Resource Assignment (Placement and Routing) 284 Designing to Fit 285 Methodology 285 Analyze Device Resources 286 Clock Signals 286 All Devices 286 MACH 3xx/4xx 286 MACH 215/3xx/4xx 287 Set/Reset Signals 288 Available Set and Reset Lines 288 MACH 3xx/4xx 288 Interaction of Set and Reset Signals (All Devices Except MACH215) 288 Reserving Unused Macrocells and I/O Pins 289 Product Terms 290 Strategies for Fitting Your Designs 291 Fitting with Unconstrained Pinout 293 Fitting with Constrained Pinout 293 Interconnection Resources 295 Oversubscribed Macrocells and/or Inputs 295 Large Functions at the End of a Block 296 Adjacent Macrocell Use 297 Grouping Logic 297 Setting Compilation and Fitting Options 298 Reducing Non-Forced Global Clocks 298 Gate Splitting 298 All MACH Devices 300 MACH 3xx/4xx Devices 300 Failure to Fit on Second Pass 302 Understanding Global Clock Signals 303 viii Balancing Clock Resources and Requirements 303 Global Clock Rules 304 Conditions Forcing Placement at a Global Clock Pin 305 Manually Forcing a Clock Signal to be Global 306 Conditions Forcing Non-Global Clocks 307 Resolving Contradictions 308 Chapter 9. Report Files Overview 311 Log File 312 Fitting Report 318 Header Information 318 MACH Fitter Options 318 Device Resource Summary 320 Block Partitioning Summary 322 Signal Summary 324 PRESET, RESET and OUTPUT ENABLED Signal Summary 327 Tabular Information 328 Fitting Status 338 Place and Route Data Report 339 Unplaceable Designs 340 Unroutable Designs 340 Place and route processing time 341 Place/Route Resource and Usage tables 341 Signal Fan-Out Table 343 Device pin-out list 344 Block information 345 Macrocell (MCell) Cluster Assignments 345 Maximum PT Capacity 350 Node-Pin Assignments 351 IO-to-Node Pin Mapping 353 IO/Node and IO/Input Macrocell Pairing Table 356 Input and Central switch matrix tables 357 Input Multiplexer (IMX) Assignments 357 Logic Array Fan-in 359 Using Place and Route Data to Limit Placements 362 Timing Analysis Report 364 TSU 366 TCO 367 TPD 368 ix TCR 369 Failure Reports 370 Failure to Partition 370 Failure to Place 372 Failure to Route 373 Chapter 10. Device Reference MACH Family Features Summary 377 MACH Features Locator, Part 1 378 MACH Features Locator, Part 2 379 MACH 1xx/2xx Design Considerations 380 Product Term Cluster Steering 380 Default Clock 380 XOR with D-Type Flip-Flops 381 T-Type Flip-Flops 381 Latches 382 MACH 1xx Latch Emulation 382 MACH 2xx Hardware Latches 383 Registered Inputs 384 Node Feedback vs. Pin Feedback 387 Registered Output with Node Feedback or Pin Feedback 388 Combinatorial Output with Node Feedback or Pin Feedback 391 Global Set and Reset 392 PAL22V10-Compatible Set/Reset Behavior 393 MACH 1xx/2xx Power-Up 393 Synchronous vs. Asynchronous Operation 393 Powerdown Feature 393 MACH 3xx/4xx Design Considerations 394 Cluster Size 394 Default Clock 395 XOR with D-Type Flip-Flops 395 T-Type Flip-Flops 396 Latches 399 MACH 3xx/4xx Hardware Latches 399 MACH 2xx/3xx/4xx vs. MACH 1xx Latch Implementation 400 Registered Inputs (MACH 4xx Devices Only) 401 Zero Hold Time for Input Registers 402 Node vs. Pin Feedback 403 x Registered Output with Node Feedback or Pin Feedback 404 Combinatorial Output with Node Feedback or Pin Feedback 407 Flexible Clock Generator 408 Global Set and Reset 409 Set/Reset Compatibility 410 PAL22V10 Register Behavior 411 Controlling MACH 3xx/4xx Set/Reset Behavior 412 Set/Reset in MACH 3xx/4xx Asynchronous Macrocells 413 Higher Block Utilization with the Set/Reset Selector Fuse 414 MACH 3xx/4xx Power-Up 415 MACH 3xx/4xx Asynchronous Macrocell Power-Up Operation 416 Set/Reset Design Recommendations 416 Synchronous vs.
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