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Appendix a GATE-LEVEL DETAILS

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Appendix a GATE-LEVEL DETAILS Appendix A GATE-LEVEL DETAILS Chapters 2 and 3 briefly introduced the built-in primitives. This appendix will briefly describe each of the built-in primitives and the options when instantiating them. The delay and strength options for primitive instances will be explained. PRIMITIVE DESCRIPTIONS Logic Gates AND Figure A-1 AND Gate 282 Verilog Quickstart The and primitive can have two or more inputs, and has one output. When all of the inputs are “1” then the output is “1”. Table A-1 Logic Table for and Primitive 0 1 x z 0 0 0 0 0 1 0 1 x x x 0 x x x z 0 x x x NAND Figure A-2 NAND Gate The nand primitive can have two or more inputs, and has one output. When all of the inputs are “1” then the output is “0”. Table A-2 Logic Table for nand Primitive 0 1 x z 0 1 1 1 1 1 1 0 x x x l x x x z l x x x Gate-Level Details 283 OR Figure A-3 OR Gate The or primitive can have two or more inputs, and has one output. When any of the inputs is “1” then the output is “1”. Table A-3 Logic Table for or Primitive 0 1 x z 0 0 1 x x 1 1 1 1 1 x x l x x z x l x x NOR Figure A-4 NOR Gate The nor primitive can have two or more inputs, and has one output. When any of the inputs is “1” then the output is “0”. Table A-4 Logic Table for nor Primitive 0 1 x z 0 1 0 x x 1 0 0 0 0 x x 0 x x z x 0 x x 284 Verilog Quickstart XOR Figure A-5 XOR Gate Thexor primitive can have two or more inputs, and has one output. When an odd number of inputs is “1” then the output is “1”, unless any input is “x”. When any of the inputs is “x” then the output is “x”. Table A-5 Logic Table for xor Primitive 0 1 x z 0 0 1 x x 1 1 0 x x x x x x x z x x x x XNOR Figure A-6 XNOR Gate The xnor primitive can have two or more inputs, and has one output. When an odd number of inputs is “1” then the output is “0”, unless any input is “x”. When any of the inputs is “x” then the output is “x”. Table A-6 Logic Table for xnor Primitive 0 1 x z 0 1 0 x x 1 0 1 x x x x x x x z x x x x Gate-Level Details 285 Buffers BUF Figure A-7 BUF Gate The buf primitive has one input and can have one or more outputs. The output(s) pass the same value as the input, except an input of “z” produces an output of “x”. Table A-7 Logic Table for buf Primitive Input Output 00 1 1 x x z x NOT Figure A-8 NOT Gate The not primitive has one input and can have one or more outputs. The output(s) pass the opposite value as the input, except an input of “x” or “z” produces an output of “x”. Table A-8 Logic Table for not Primitive Input Output 0 1 1 0 x x z x 286 Verilog Quickstart BUFIF0 Figure A-9 BUFIF0 Gate The bufif0 primitive has two inputs, (data and control) and one output. When the control input is “0” the output passes the same value as the data input, except that an input of “z’ produces an output of “x”. When the control input is “1” the output is “z”. The port order of the primitive is output, input, control. The remaining logic tables in the section show both strength and value. Verilog uses a notation of three characters, two for the strength, and one for the value. Table A-20 lists the two character codes used for the strength and the value is 0, 1, x, or z. Table A-9 Logic Table for bufif0 Primitive Data 0 1 x z 0 St0 HiZ StL StL 1 Stl HiZ StH StH x StX HiZ StX StX z StX HiZ StX StX BUFlF1 Figure A-10 BUFIF1 Gate The bufif1 primitive has two inputs, (data and control) and one output. When the control input is “1” the output passes the same value as the data input, except that an input of “z” produces an output of “x”. When the control input is “0” the output is “z”. The port order of the primitive is output, input, control. Gate-Level Details 287 Table A-10 Logic Table for bufif1 Primitive Data 0 1 x z 1 HiZ St0 StL StL 1 HiZ St1 StH StH x HiZ StX StX StX z HiZ StX StX StX NOTIF0 Figure A-11 NOTIF0 Gate The notif0 primitive has two inputs, (data and control) and one output. When the control input is “0” the output passes the opposite value as the data input, except that an input of “z” produces an output of “x”. When the control input is “1” the output is “z”. The port order of the primitive is output, input, control. Table A-11 Logic Table for notif0 Primitive Data 01xz 0 Stl HiZ StH StH 1 St0 HiZ StL StL x StX HiZ StX StX z StX HiZ StX StX 288 Verilog Quickstart NOTlF1 Figure A-12 NOTIF1 Gate The notif1 primitive has two inputs, data and control and one output. When the control input is “1” the output passes the opposite value as the data input, except that an input of “z” produces an output of “x”. When the control input is “0” the output is “z”. The port order of the primitive is output, input, control. Table A-12 Logic Table for notif1 Primitive Data 0 1 x z 0 HiZ Stl StH StH 1 HiZ St0 StL StL x HiZ StX StX StX Z HiZ StX StX StX PULLDOWN Figure A-13 Pulldown The pulldown primitive has only one terminal. It outputs a 0 of strength pull ( pu0). When nothing else is driving a net stronger than the pulldown, the pulldown will drive the net to 0. Gate-Level Details 289 PULLUP Figure A-14 Pullup The pullup primitive has only one terminal. It outputs a 1 of strength pull ( pul). When nothing else is driving a net stronger than the pullup, the pullup will drive the net to 1. Switches Verilog supports simulating transistors as switches. There are switch models of unidirectional and bi-directional switches. There are model of both ideal and resistive switches. Table A-21 details the signal strength reduction through the switches. 290 Verilog Quickstart NMOS and RNMOS Figure A-15 NMOS or RNMOS Transistor The nmos and rnmos primitives are abstractions of unidirectional switches. When the gate input is 1, this input is passed to the output, otherwise the output is high impedance. The difference between the nmos and rnmos is the nmos passes the input to the output with the strength unchanged, but the rnmos passes the value to the output with a decreased strength. The port order of the primitive is output, input, gate. The output strength from any of the transistor primitives is dependent on the strength of the input. The input strength for the following tables is strong, unless otherwise noted. Table A-13 Logic Table for nmos Primitive Data 01xz 0 HiZ St0 StL StL 1 HiZ Stl StH StH x HiZ StX StX StX z HiZ HiZ HiZ HiZ Table A-14 Logic Table for rnmos Primitive Data 0 1 x z 0 HiZ Pu0 PuL PuL 1 HiZ Pul PuH PuH x HiZ PuX PuX PuX z HiZ HiZ HiZ HiZ Gate-Level Details 291 PMOS and RPMOS Figure A-16 PMOS or RPMOS Transistor The pmos and rpmos primitives are abstractions of unidirectional switches. When the gate input is 0, this input is passed to the output, otherwise the output is high impedance. The difference between the pmos and rpmos is the pmos passes the input to the output with the strength unchanged, but the rpmos passes the value to the output with a decreased strength. The port order of the primitive is output, input, gate. Table A-15 Logic Table for pmos Primitive Data 01xz 0 St0 HiZ StL StL 1 St1 HiZ StH StH X StX HiZ StX StX Z HiZ HiZ HiZ HiZ Data 01xz 0 Pu0 HiZ PuL PuL 1 Pul HiZ PuH PuH x PuX HiZ PuX PuX z HiZ HiZ HiZ HiZ 292 Verilog Quickstart CMOS and RCMOS Figure A-17 CMOS or RCMOS transistor The cmos and rcmos primitives are the equivalent or nmos and pmos (or rnmos and rpmos) primitives connected back to back. The primitive has four terminals. The port order is output, input, ngate, pgate. Table A-17 Logic Table for cmos Primitive ngate pgate 0 1 x z 0 0 St0 Stl StX HiZ 0 1 HiZ HiZ HiZ HiZ 0 x StL StH StX HiZ 0 z StL StH StX HiZ 1 0 St0 St1 StX HiZ 1 1 St0 St1 StX HiZ 1 x St0 St1 StX HiZ 1 Z St0 St1 StX HiZ x 0 St0 St1 StX HiZ x 1 StL StH StX HiZ x x StL StH StX HiZ x z StL StH StX HiZ z 0 St0 Stl StX HiZ zz 1 StL StH StX HiZ z x StL StH StX HiZ z z StL StH StX HiZ Gate-Level Details 293 Table A-18 Loaic Table for rcmos Primitive ngate pgate 0 1 x z 0 0 Pu0 Pul Pu0 HiZ 0 1 HiZ HiZ HiZ HiZ 0 x PuL PuH PuX HiZ 0 z PuL PuH PuX HiZ 1 0 Pu0 Pul PuX HiZ 1 1 Pu0 Pul PuX HiZ 1 x Pu0 Pul PuX HiZ 1 z Pu0 Pul PuX HiZ x 0 Pu0 Pu1 PuX HiZ x 1 PuL PuH PuX HiZ x x PuL PuH PuX HiZ x z PuL PuH PuX HiZ z 0 Pu0 Pul PuX HiZ z 1 PuL PuH PuX HiZ z x PuL PuH PuX HiZ z z PuL PuH PuX HiZ TRAN and RTRAN The tran and rtran primitives are bidirectional pass gates.
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